CN102170645A - Hardware device of time division multiple access (TDMA)-based multi-terminal real-time simulation system - Google Patents
Hardware device of time division multiple access (TDMA)-based multi-terminal real-time simulation system Download PDFInfo
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- CN102170645A CN102170645A CN2011100568158A CN201110056815A CN102170645A CN 102170645 A CN102170645 A CN 102170645A CN 2011100568158 A CN2011100568158 A CN 2011100568158A CN 201110056815 A CN201110056815 A CN 201110056815A CN 102170645 A CN102170645 A CN 102170645A
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Abstract
The invention discloses a hardware device of a time division multiple access (TDMA)-based multi-terminal real-time simulation system, which aims to provide the device capable of studying the characteristics comprising multi-terminal performance and real-time performance of a TDMA communication system. Key points of the technical scheme are that: terminal equipment performs multi-terminal simulation by Cortex; relay equipment comprises a field programmable gate array (FPGA) for the relay processing of data; and link equipment comprises 100-mega Ethernet and low voltage differential signaling (LVDS) concatenation, and realizes data transmission, and inter-board concatenation is realized by an LVDS serial concatenation method, so that all the terminals can be ensured to be equal, and simultaneously, the anti-jamming capability of the system can be improved.
Description
Technical field
The present invention relates to a kind of hardware unit of the multiple terminals real-time emulation system based on TDMA.
Background technology
Along with the development of communication engineering technology is maked rapid progress, various communication systems emerge in an endless stream, and the TDMA technology can realize that hundreds of users are shared and use a radio net simultaneously owing to it, and advantage that can the phase mutual interference becomes very important technology in the communication system, so the various characteristics of research tdma system becomes main flow, and the tdma communication system of building a reality is both uneconomical also unpractical, so just become the focus of studying based on the building of communicatrion emulator of TDMA.At present, emulation based on the communication system of TDMA pattern has a variety of methods, as based on the MATLAB software view, based on OPNET half aspect in kind, these emulation all can only be reproduced the characteristic of tdma communication system to a certain extent, for the multiple terminals real-time of tdma communication system be have very big circumscribed.
Summary of the invention
Main purpose of the present invention is to provide the hardware unit of a kind of TDMA multiple terminals real-time emulation system.
In order to reach above purpose, a kind of device that type of the present invention provides comprises terminal equipment, trunking and chain pipeline equipment.Terminal equipment carries out the multiple terminals simulation by flush bonding processor, and trunking comprises that FPGA carries out the relay process of data; The chain pipeline equipment comprises that 100 m ethernet, LVDS cascade carry out the transmission of data.
More existing technology, type of the present invention are to utilize 100 m ethernet, LVDS bus to reduce the time-delay on the link, realize real-time emulation truly; The device that the LVDS bus level is linked to each terminal guarantees the equality of each terminal in the TDMA network, and this structure also makes multiple terminals message multiple connection oversimplify simultaneously; FPGA has programmability flexibly as the relay of up-downgoing data, has also guaranteed the little time-delay in the link simultaneously; The communication controler of flush bonding processor simulation has good data-handling capacity and relaying action; The terminal of flush bonding processor simulation is both economical small and exquisite, and the area that takies is little, has guaranteed the disposal ability timely fast of terminal again; The hardware unit of whole simulation system is very economical, again good simulation has been carried out in the real-time and the multiple terminals of tdma system, is used for any tdma communication systematic research, can also simulate a plurality of TDMA networks, has realized the versatility of analogue system.
In order to solve the technical problem of above-mentioned existence, the present invention has adopted following technical proposals:
The present invention includes two parts: terminal equipment, trunking and chain pipeline equipment.
Data interaction between the communication controler that described terminal equipment and the chain pipeline equipment terminal by flush bonding processor simulation and flush bonding processor are simulated, uplink downlink is made of 100 m ethernet and LVDS cascade, FPGA is as the repeater on the data link, and whole system has been finished the real time communication of data between the multiple terminals.
The hardware unit of described multiple terminals real-time emulation system based on TDMA, in order to guarantee the disposal ability of data, communication controler and all terminal equipments all are to be simulated by flush bonding processor.
The hardware unit of described multiple terminals real-time emulation system based on TDMA, for the multiple connection of the mutual and terminal message of realizing data, all terminal equipments all are to connect by the LVDS cascade bus.
The hardware unit of described multiple terminals real-time emulation system based on TDMA, for the real-time that guarantees system reduces time-delay, the bus of chain pipeline equipment is made of 100 m ethernet and LVDS bus.
The hardware unit of described multiple terminals real-time emulation system based on TDMA, FPGA is as the trunking on the link, guaranteed the time-delay on the link,, the data form has been changed accordingly and encrypted simultaneously also as the data processing equipment on terminal equipment and the communication controler link.
The hardware unit of described multiple terminals real-time emulation system based on TDMA, it is mutual immediately trunking and terminal equipment to be carried out the address after powering on, and add up and constitute the full address of a terminal and be uploaded to communication controler by spi bus in two addresses.
Description of drawings
Fig. 1 is basic conception figure of the present invention.
Fig. 2 is a structural representation of the present invention.
Fig. 3 is downlink data interaction diagrams of the present invention.
Fig. 4 is upstream data interaction diagrams of the present invention.
Embodiment
Fig. 1 illustrates the present invention and comprises three parts: terminal equipment 1, trunking 2, chain pipeline equipment 3.Wherein terminal equipment comprises CC and terminal, and the chain pipeline equipment comprises Ethernet and LVDS bus interface.
Fig. 2 illustrates structure of the present invention.Respectively terminal equipment, trunking and chain pipeline equipment are described in detail.
Terminal equipment comprises: parts such as data source 11, CC (communication controler) 12, terminal 1～(8N+8) 13; Trunking mainly is to be made of FPGA end plaste 1～N21 and FPGA decoding deck 22; The chain pipeline equipment comprises: parts such as Ethernet 31, LVDS32 and SPI33.
The message that data source produces is issued to above the CC (communication controller is a communication controler) by network interface, FPGA the inside on the decoding deck, decoding deck is issued to message in the FPGA on the end plaste by the LVDS universal serial bus, FPGA receives issuing message, and message is divided by the SPI mouth and give relevant terminal on this plate according to the terminal address in the message number, simultaneously, with issuing message by passing to next FPGA under the LVDS mouth, adopt this structure, just realized the point-to-point high speed data transfer of LVDS, and can guarantee that each FPGA is independently, this in theory structure can connect many arbitrarily terminals; And when uploading, if each terminal has message to send, send to the FPGA the inside by the SPI serial ports, FPGA is multiplexed into same time slot the inside with the message of same frame the inside, upload to decoding deck by the LVDS mouth, after the message of decoding deck after to multiple connection is decoded, message is uploaded to data source by network interface, like this, message is got back to data source again after transmitting through FPGA, at this moment, data source just can be calculated the error rate of message, and can calculate the distance of whole link according to issuing message and the time-delay of uploading message.
Fig. 3 illustrates downlink data reciprocal process of the present invention
1, power on after data source prediction scheme is sent to CC by Ethernet, if sends successfully then transmission once more; After prediction scheme sent successfully, data source then sent initiation command.
2, after the success of transmission initiation command, data source sends issuing message to CC.
3, CC conversion issuing message form is issued on the FPGA end plaste by LVDS, and FPGA sends the data to corresponding terminal to message relay and with message sink by spi bus, and terminal receives corresponding issuing message under the control of interrupt signal.
Fig. 4 illustrates upstream data reciprocal process of the present invention
1, power on after each terminal remove to detect frame pulse signal (being the frame pulse of stipulating in the prediction scheme), detect terminal after the frame pulse and will upload message and send to RAM in the FPGA by spi bus.
2, FPGA sends the concurrent messages that receives by the serial of TDMA form.
3, decoding deck reception serial is uploaded message and is decoded and is sent to CC by Ethernet, and CC is uploaded to data source with source codec and by Ethernet, adds up the performance of whole system.
Claims (7)
1. the hardware unit of a TDMA multiple terminals real-time emulation system comprises three parts: terminal equipment, trunking and chain pipeline equipment.It is characterized in that: terminal equipment carries out the multiple terminals simulation by flush bonding processor, and trunking comprises that FPGA carries out the relay process of data; The chain pipeline equipment comprises that 100 m ethernet, LVDS cascade carry out the transmission of data, and the LVDS cascade structure has been simplified the multiple connection of multiple terminals message.
2. according to the hardware unit of right 1 described TDMA multiple terminals real-time emulation system, it is characterized in that: all end plastes all are to connect by the cascade of LVDS bus, make multiple terminals message subframe multiple connection to realize with hardware simply.
3. according to the hardware unit of right 1,2 described TDMA multiple terminals real-time emulation systems, it is characterized in that: the bus of chain pipeline equipment is made of 100 m ethernet and LVDS bus.
4. according to the hardware unit of right 1,2,3 described TDMA multiple terminals real-time emulation systems, it is characterized in that: FPGA is as the trunking on the link, guaranteed the time-delay on the link, also as the data processing equipment on terminal equipment and the communication controler link, the data form is changed accordingly and encrypted simultaneously.
5. according to the hardware unit of right 1,2,3,4 described TDMA multiple terminals real-time emulation systems, it is characterized in that: communication controler and all terminal equipments all are to be simulated by flush bonding processor.
6. according to the hardware unit of right 1,2,3,4,5 described TDMA multiple terminals real-time emulation systems, it is characterized in that: it is mutual immediately trunking and terminal equipment to be carried out the address after powering on, and adds up and constitute the full address of a terminal and be uploaded to communication controler by spi bus in two addresses.
7. according to the hardware unit of right 1,2,3,4,5,6 described TDMA multiple terminals real-time emulation systems, it is characterized in that: this analogue system can be simulated a plurality of TDMA networks simultaneously, has versatility.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100568158A CN102170645A (en) | 2011-03-10 | 2011-03-10 | Hardware device of time division multiple access (TDMA)-based multi-terminal real-time simulation system |
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| CN2011100568158A CN102170645A (en) | 2011-03-10 | 2011-03-10 | Hardware device of time division multiple access (TDMA)-based multi-terminal real-time simulation system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102932276A (en) * | 2012-10-09 | 2013-02-13 | 无锡江南计算技术研究所 | Computing node cluster system and data relay |
| CN108476150A (en) * | 2015-11-16 | 2018-08-31 | 布尔简易股份公司 | Equipment for analogue communication relaying |
| CN113595843A (en) * | 2021-07-28 | 2021-11-02 | 浙江中控技术股份有限公司 | Control system based on BLVDS signal relay device |
| CN115314070A (en) * | 2022-08-09 | 2022-11-08 | 浙江中控信息产业股份有限公司 | Cascade type high-speed long-line transmission device |
-
2011
- 2011-03-10 CN CN2011100568158A patent/CN102170645A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102932276A (en) * | 2012-10-09 | 2013-02-13 | 无锡江南计算技术研究所 | Computing node cluster system and data relay |
| CN102932276B (en) * | 2012-10-09 | 2015-01-14 | 无锡江南计算技术研究所 | Computing node cluster system and data relay |
| CN108476150A (en) * | 2015-11-16 | 2018-08-31 | 布尔简易股份公司 | Equipment for analogue communication relaying |
| CN113595843A (en) * | 2021-07-28 | 2021-11-02 | 浙江中控技术股份有限公司 | Control system based on BLVDS signal relay device |
| CN115314070A (en) * | 2022-08-09 | 2022-11-08 | 浙江中控信息产业股份有限公司 | Cascade type high-speed long-line transmission device |
| CN115314070B (en) * | 2022-08-09 | 2024-02-09 | 浙江中控信息产业股份有限公司 | Cascaded high-speed long-line transmission device |
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Application publication date: 20110831 |