CN102170645A

CN102170645A - Hardware device of time division multiple access (TDMA)-based multi-terminal real-time simulation system

Info

Publication number: CN102170645A
Application number: CN2011100568158A
Authority: CN
Inventors: 李绍胜; 唐辉艳
Original assignee: Beijing University of Posts and Telecommunications
Current assignee: Beijing University of Posts and Telecommunications
Priority date: 2011-03-10
Filing date: 2011-03-10
Publication date: 2011-08-31

Abstract

The invention discloses a hardware device of a TDMA-based multi-terminal real-time simulation system, aiming at providing a device capable of studying the characteristics (including multi-terminal and real-time) of the TDMA communication system. The main point of its technical solution is that the terminal equipment performs multi-terminal simulation through Cortex, the relay equipment includes FPGA for data relay processing; the link equipment includes Fast Ethernet and LVDS cascading for data transmission, and all inter-board cascading The method adopts the LVDS serial cascading method, which can ensure that all terminals are in an equal position, and can also improve the anti-interference ability of the system.

Description

The hardware unit of a kind of TDMA multiple terminals real-time emulation system

Technical field

The present invention relates to a kind of hardware unit of the multiple terminals real-time emulation system based on TDMA.

Background technology

Along with the development of communication engineering technology is maked rapid progress, various communication systems emerge in an endless stream, and the TDMA technology can realize that hundreds of users are shared and use a radio net simultaneously owing to it, and advantage that can the phase mutual interference becomes very important technology in the communication system, so the various characteristics of research tdma system becomes main flow, and the tdma communication system of building a reality is both uneconomical also unpractical, so just become the focus of studying based on the building of communicatrion emulator of TDMA.At present, emulation based on the communication system of TDMA pattern has a variety of methods, as based on the MATLAB software view, based on OPNET half aspect in kind, these emulation all can only be reproduced the characteristic of tdma communication system to a certain extent, for the multiple terminals real-time of tdma communication system be have very big circumscribed.

Summary of the invention

Main purpose of the present invention is to provide the hardware unit of a kind of TDMA multiple terminals real-time emulation system.

In order to reach above purpose, a kind of device that type of the present invention provides comprises terminal equipment, trunking and chain pipeline equipment.Terminal equipment carries out the multiple terminals simulation by flush bonding processor, and trunking comprises that FPGA carries out the relay process of data; The chain pipeline equipment comprises that 100 m ethernet, LVDS cascade carry out the transmission of data.

More existing technology, type of the present invention are to utilize 100 m ethernet, LVDS bus to reduce the time-delay on the link, realize real-time emulation truly; The device that the LVDS bus level is linked to each terminal guarantees the equality of each terminal in the TDMA network, and this structure also makes multiple terminals message multiple connection oversimplify simultaneously; FPGA has programmability flexibly as the relay of up-downgoing data, has also guaranteed the little time-delay in the link simultaneously; The communication controler of flush bonding processor simulation has good data-handling capacity and relaying action; The terminal of flush bonding processor simulation is both economical small and exquisite, and the area that takies is little, has guaranteed the disposal ability timely fast of terminal again; The hardware unit of whole simulation system is very economical, again good simulation has been carried out in the real-time and the multiple terminals of tdma system, is used for any tdma communication systematic research, can also simulate a plurality of TDMA networks, has realized the versatility of analogue system.

In order to solve the technical problem of above-mentioned existence, the present invention has adopted following technical proposals:

The present invention includes two parts: terminal equipment, trunking and chain pipeline equipment.

Data interaction between the communication controler that described terminal equipment and the chain pipeline equipment terminal by flush bonding processor simulation and flush bonding processor are simulated, uplink downlink is made of 100 m ethernet and LVDS cascade, FPGA is as the repeater on the data link, and whole system has been finished the real time communication of data between the multiple terminals.

The hardware unit of described multiple terminals real-time emulation system based on TDMA, in order to guarantee the disposal ability of data, communication controler and all terminal equipments all are to be simulated by flush bonding processor.

The hardware unit of described multiple terminals real-time emulation system based on TDMA, for the multiple connection of the mutual and terminal message of realizing data, all terminal equipments all are to connect by the LVDS cascade bus.

The hardware unit of described multiple terminals real-time emulation system based on TDMA, for the real-time that guarantees system reduces time-delay, the bus of chain pipeline equipment is made of 100 m ethernet and LVDS bus.

The hardware unit of described multiple terminals real-time emulation system based on TDMA, FPGA is as the trunking on the link, guaranteed the time-delay on the link,, the data form has been changed accordingly and encrypted simultaneously also as the data processing equipment on terminal equipment and the communication controler link.

The hardware unit of described multiple terminals real-time emulation system based on TDMA, it is mutual immediately trunking and terminal equipment to be carried out the address after powering on, and add up and constitute the full address of a terminal and be uploaded to communication controler by spi bus in two addresses.

Description of drawings

Fig. 1 is basic conception figure of the present invention.

Fig. 2 is a structural representation of the present invention.

Fig. 3 is downlink data interaction diagrams of the present invention.

Fig. 4 is upstream data interaction diagrams of the present invention.

Embodiment

Fig. 1 illustrates the present invention and comprises three parts: terminal equipment 1, trunking 2, chain pipeline equipment 3.Wherein terminal equipment comprises CC and terminal, and the chain pipeline equipment comprises Ethernet and LVDS bus interface.

Fig. 2 illustrates structure of the present invention.Respectively terminal equipment, trunking and chain pipeline equipment are described in detail.

Terminal equipment comprises: parts such as data source 11, CC (communication controler) 12, terminal 1～(8N+8) 13; Trunking mainly is to be made of FPGA end plaste 1～N21 and FPGA decoding deck 22; The chain pipeline equipment comprises: parts such as Ethernet 31, LVDS32 and SPI33.

The message that data source produces is issued to above the CC (communication controller is a communication controler) by network interface, FPGA the inside on the decoding deck, decoding deck is issued to message in the FPGA on the end plaste by the LVDS universal serial bus, FPGA receives issuing message, and message is divided by the SPI mouth and give relevant terminal on this plate according to the terminal address in the message number, simultaneously, with issuing message by passing to next FPGA under the LVDS mouth, adopt this structure, just realized the point-to-point high speed data transfer of LVDS, and can guarantee that each FPGA is independently, this in theory structure can connect many arbitrarily terminals; And when uploading, if each terminal has message to send, send to the FPGA the inside by the SPI serial ports, FPGA is multiplexed into same time slot the inside with the message of same frame the inside, upload to decoding deck by the LVDS mouth, after the message of decoding deck after to multiple connection is decoded, message is uploaded to data source by network interface, like this, message is got back to data source again after transmitting through FPGA, at this moment, data source just can be calculated the error rate of message, and can calculate the distance of whole link according to issuing message and the time-delay of uploading message.

Fig. 3 illustrates downlink data reciprocal process of the present invention

1, power on after data source prediction scheme is sent to CC by Ethernet, if sends successfully then transmission once more; After prediction scheme sent successfully, data source then sent initiation command.

2, after the success of transmission initiation command, data source sends issuing message to CC.

3, CC conversion issuing message form is issued on the FPGA end plaste by LVDS, and FPGA sends the data to corresponding terminal to message relay and with message sink by spi bus, and terminal receives corresponding issuing message under the control of interrupt signal.

Fig. 4 illustrates upstream data reciprocal process of the present invention

1, power on after each terminal remove to detect frame pulse signal (being the frame pulse of stipulating in the prediction scheme), detect terminal after the frame pulse and will upload message and send to RAM in the FPGA by spi bus.

2, FPGA sends the concurrent messages that receives by the serial of TDMA form.

3, decoding deck reception serial is uploaded message and is decoded and is sent to CC by Ethernet, and CC is uploaded to data source with source codec and by Ethernet, adds up the performance of whole system.

Claims

1. A hardware device of a TDMA multi-terminal real-time simulation system, comprising three parts: terminal equipment, relay equipment and link equipment. Its characteristics are: the terminal device performs multi-terminal simulation through the embedded processor, the relay device includes FPGA for data relay processing; the link device includes 100M Ethernet and LVDS cascade for data transmission, and the LVDS cascade structure is simplified Multi-terminal message multiplexing.

2. according to the hardware device of the described TDMA multi-terminal real-time emulation system of right 1, it is characterized in that: all terminal boards are all connected by LVDS bus cascading, so that multi-terminal message subframe multiplexing can be realized with hardware simply .

3. according to the hardware device of the described TDMA multi-terminal real-time emulation system of right 1,2, it is characterized in that: the bus of link equipment is made of Fast Ethernet and LVDS bus.

4. according to the hardware device of the described TDMA multi-terminal real-time emulation system of right 1,2,3, it is characterized in that: FPGA is as the relay equipment on the link, has guaranteed the delay on the link, also as terminal equipment simultaneously and the data processing equipment on the link of the communication controller to convert and encrypt the data format accordingly.

5. according to the hardware device of the described TDMA multi-terminal real-time emulation system of right 1,2,3,4, it is characterized in that: communication controller and all terminal equipments are all simulated by embedded processor.

6. according to the hardware device of the described TDMA multi-terminal real-time emulation system of right 1,2,3,4,5, it is characterized in that: relay equipment and terminal equipment are carried out address interaction immediately after power-on, two addresses add up The complete address of a terminal is formed and uploaded to the communication controller through the SPI bus.

7. According to the hardware device of the TDMA multi-terminal real-time simulation system described in claims 1, 2, 3, 4, 5, 6, it is characterized in that: the simulation system can simultaneously simulate a plurality of TDMA networks, and has versatility.