CN109361581A - A kind of one master and multiple slaves formula high-speed serial communication system and the means of communication - Google Patents
A kind of one master and multiple slaves formula high-speed serial communication system and the means of communication Download PDFInfo
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- CN109361581A CN109361581A CN201811054183.XA CN201811054183A CN109361581A CN 109361581 A CN109361581 A CN 109361581A CN 201811054183 A CN201811054183 A CN 201811054183A CN 109361581 A CN109361581 A CN 109361581A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/4013—Management of data rate on the bus
- H04L12/40136—Nodes adapting their rate to the physical link properties
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
- H04L12/4035—Bus networks with centralised control, e.g. polling in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit
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Abstract
The present invention discloses a kind of one master and multiple slaves formula high-speed serial communication system based on timeslice and connects several slaves in each communication leg including the host containing multi-path serial processing module and several communication legs.The multi-path serial processing module of host, is realized by FPGA, can sending and receiving with all branch messages of synchronization process, guarantee all branches can with parallel communications, improve communication bandwidth.Host realizes the accurate clock synchronization of slave by FPGA.A kind of method of one master and multiple slaves formula high-speed serial communication based on timeslice is also disclosed simultaneously.The present invention can be obviously improved the efficiency of serial communication, improve system response time.
Description
Technical field
The invention belongs to network communication fields, in particular to master-slave mode high-speed serial communication system in industrial process control field
System structures and methods.
Background technique
Serial communication is widely used in industrial process control field, such as thermal power plant main auxiliary machine DCS control
(Distributed Control System), hydroelectric power plant LCU control the prison of (Local Control Unit), Processes and apparatus
Depending on and control, city water process and pumping plant pipe network control etc..The switching value and analog signals of Process Control System acquisition, pass through
Controller is sent in serial communication；The control instruction of controller is issued to I/O-unit by serial communication, exports switching value or simulation
Amount realizes the control run to field device.
A kind of communication solution of the serial communication bus as high performance-price ratio obtains extensively in industrial process control field
Application.As on-scene communication data volume increases the raising with requirement of real-time, conventional low (being not more than 115200bps) is serial
Bus is difficult to meet demand, and live I/O-unit quantity increases problem and more highlights.Need to design a kind of high-speed serial communication system,
Thus this case generates.
Existing implementation, as shown in Figure 1, specific as follows:
(1) communication system host passes through a communication link and n(n=1,2,3 ...) a slave communicates.
(2) non-broadcasting message, a certain moment host are only capable of communicating with a slave.
As it can be seen that communication efficiency is lower in above-mentioned process, it is not able to satisfy the field demand that data volume is big, real-time is high.
Summary of the invention
The purpose of the present invention, is to provide a kind of one master and multiple slaves formula high-speed serial communication system and the means of communication, system are adopted
It is logical to improve system to make full use of the bandwidth of high-speed serial communication with the high-speed serial communication mode of the multiple slaves of host
The real-time of letter.
In order to achieve the above objectives, the technical scheme is that a kind of one master and multiple slaves formula high-speed serial communication system, packet
Host and one or more communication leg are included, several slaves are connected in the communication leg；
The host includes multi-path serial processing module；
The serial communication module is realized by FPGA, for sending and receiving for all branch messages of synchronization process, is guaranteed all
Communication leg parallel communications improves communication bandwidth.
Further, the communication leg is communicated simultaneously, and communication is independent of each other between branch.
Further, the host realizes the accurate clock synchronization of slave by serial ports message by FPGA.
The present invention proposes a kind of communication means of above-mentioned one master and multiple slaves formula high-speed serial communication system simultaneously, comprising:
Mutually indepedent, communication isolating, all communication legs can carry out communication friendship simultaneously between the communication leg of the communication system
Mutually, communication leg internal communication process uses time sheet mode, and time division multiplexing occupies communication bus；
Each communication process is initiated by host, request or order of the slave only in response to host；
In a communication process, host sends request or command message immediately treats after slave receives complete frame message
And it sends back multiple message and is responded；After host computer side receives response message, a framing interval is waited, is started immediately next logical
Letter process.
When host sends broadcasting packet or multicast message to slave, slave is not responded.
Further, sending and receiving for message is completed by the multi-path serial processing module in host.
Further, message is received from pusher side using DMA mode, or receives serial message using FPGA；Complete one
After the reception of frame message, interrupt processing request or command message are triggered immediately, improves the response efficiency of slave.
Further, the communication leg that amount of communication data is big and real-time is high, serial communication baud rate selection 1M ~
10Mbps。
Further, the communication baud rate of each communication leg can be respectively set.
Further, in particular moment, host is synchronized to all communication legs transmissions pair by FPGA serial communication module
When message, will the UTC second of sending instant and microsecond number filling message in；When slave receives clock synchronization message, parse UTC seconds and
Microsecond number, and be delayed according to message transmissions, Accurate Estimation goes out current time, realizes accurate clock synchronization.
The beneficial effects of the present invention are: all communication legs in this programme can improve communication bandwidth with parallel communications.
After adopting the above scheme, the bandwidth and efficiency that can effectively improve serial communication, improve system response time.
Detailed description of the invention
Fig. 1 is existing communication system structure diagram；
Fig. 2 is communication system architecture schematic diagram of the present invention.
Specific embodiment
Below with reference to attached drawing, technical solution of the present invention is described in detail.Following embodiment is only used for more clear
Illustrate to Chu technical solution of the present invention, and cannot be limited the scope of the invention with this.
As shown in Fig. 2, a kind of one master and multiple slaves formula high-speed serial communication system, including contain host and M(M=1,2,3 ...
...) branch, several slaves are connected in each communication leg.Generally, controller is as host, and I/O-unit is as slave.
Host includes multi-path serial processing module, and the serial communication module is realized by FPGA, can provide communication bandwidth,
It is time-consuming to reduce the processor that message sends and receivees；Can request or command message be sent to all branches simultaneously；It can also be same
When handle the response messages of all road slaves, guarantee that all branches can improve communication bandwidth with parallel communications.Communication leg
It is communicated simultaneously, communication is independent of each other between branch.Host realizes the accurate clock synchronization of slave by serial ports message by FPGA.
The means of communication of above-mentioned one master and multiple slaves formula high-speed serial communication system, comprising:
(1) mutually indepedent, communication isolating, all communication legs can carry out communication friendship simultaneously between the communication leg of communication system
Mutually.Communication leg internal communication process uses time sheet mode, and time division multiplexing occupies communication bus.
This system can be formed by one to a plurality of branch, electrical isolation between branch, independently of each other.The quantity of communication leg,
The quantity of slave needs reasonable Arrangement in every communication leg, to guarantee the real-time of communication.
All branches can communicate simultaneously, greatly improve communication bandwidth.Branch internal communication is main by the way of timeslice
When machine sends message, slave can only receive message.In addition to broadcast or multicast message, after slave receives the message of host, need
Request or the command message of host are responded within the set time.
(2) communication process is initiated by host every time, request or order of the slave only in response to host.
The communication system uses one master and multiple slaves mode, and communication process is initiated by host, and slave cannot actively initiate to communicate.
(3) in a communication process, host sends request or command message, after slave receives complete frame message,
It immediately treats and sends back multiple message and responded.After host computer side receives response message.A framing interval is waited, is started immediately
Next communication process.Sending and receiving for message is completed by the multi-path serial processing module in host.
Preferentially, message is received from pusher side using DMA mode, or receives serial message using FPGA.Complete a frame
After the reception of message, interrupt processing request or command message are triggered immediately, the response efficiency of slave can be improved.
Preferably, host computer side using FPGA realize multi-path serial processing module, guarantee all branches can send simultaneously and
Receive serial message.
After host receives the reply message of slave, a framing interval is waited, so that other slaves can distinguish two frames
Different messages.Be not easy with division frame interval it is too long, to improve communication efficiency.
Preferably, the communication leg that amount of communication data is big and real-time is high, serial communication baud rate be typically chosen 1M ~
10Mbps.The communication baud rate of each communication leg can be respectively set, and in the case where meeting the requirements, can reduce wave respectively
Special rate improves communications anti-jamming.
(4) host can send broadcasting packet to slave or multicast message, slave are not responding to.
For being not required to the specific function message of response, host can send broadcasting packet or multicast message to slave, to mention
High communication efficiency.
(5) host realizes the accurate clock synchronization of slave by FPGA.
In particular moment, host is synchronized to all branches by FPGA serial communication module and sends clock synchronization message, will send
In the UTC second at moment and microsecond number filling message.When slave receives clock synchronization message, UTC seconds and microsecond number are parsed, and according to
Message transmissions delay, Accurate Estimation go out current time, realize accurate clock synchronization.
The above examples only illustrate the technical idea of the present invention, and this does not limit the scope of protection of the present invention, all
According to the technical idea provided by the invention, any changes made on the basis of the technical scheme each falls within the scope of the present invention
Within.
Claims (9)
1. a kind of one master and multiple slaves formula high-speed serial communication system, which is characterized in that including host and one or more communication leg, institute
It states and connects several slaves in communication leg；
The host includes multi-path serial processing module；
The serial communication module is realized by FPGA, for sending and receiving for all branch messages of synchronization process, is guaranteed all
Communication leg parallel communications improves communication bandwidth.
2. a kind of one master and multiple slaves formula high-speed serial communication system according to claim 1, it is characterised in that: the communication branch
Road is communicated simultaneously, and communication is independent of each other between branch.
3. a kind of one master and multiple slaves formula high-speed serial communication system according to claim 1, it is characterised in that: the host is borrowed
FPGA is helped to realize the accurate clock synchronization of slave by serial ports message.
4. a kind of communication means of one master and multiple slaves formula high-speed serial communication system as described in any one of claims 1 to 3, special
Sign is: including,
Mutually indepedent, communication isolating, all communication legs can carry out communication friendship simultaneously between the communication leg of the communication system
Mutually, communication leg internal communication process uses time sheet mode, and time division multiplexing occupies communication bus；
Each communication process is initiated by host, request or order of the slave only in response to host；
In a communication process, host sends request or command message immediately treats after slave receives complete frame message
And it sends back multiple message and is responded；After host computer side receives response message, a framing interval is waited, is started immediately next logical
Letter process.
When host sends broadcasting packet or multicast message to slave, slave is not responded.
5. the communication means of one master and multiple slaves formula high-speed serial communication system as claimed in claim 4, which is characterized in that message
It sends and receives and is completed by the multi-path serial processing module in host.
6. the communication means of one master and multiple slaves formula high-speed serial communication system as claimed in claim 4, which is characterized in that from pusher side
Message is received using DMA mode, or receives serial message using FPGA；After the reception for completing a frame message, trigger immediately
Interrupt processing request or command message improve the response efficiency of slave.
7. the communication means of one master and multiple slaves formula high-speed serial communication system as claimed in claim 4, which is characterized in that communication number
According to the communication leg that amount is big and real-time is high, serial communication baud rate selects 1M~10Mbps.
8. the communication means of one master and multiple slaves formula high-speed serial communication system as claimed in claim 4, which is characterized in that Mei Getong
The communication baud rate of letter branch can be respectively set.
9. the communication means of one master and multiple slaves formula high-speed serial communication system as claimed in claim 4, which is characterized in that specific
At the moment, host is synchronized to all communication legs by FPGA serial communication module and sends clock synchronization message, by the UTC second of sending instant
In microsecond number filling message；When slave receives clock synchronization message, UTC seconds and microsecond number are parsed, and prolong according to message transmissions
When, Accurate Estimation goes out current time, realizes accurate clock synchronization.
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| CN201811054183.XA CN109361581A (en) | 2018-09-11 | 2018-09-11 | A kind of one master and multiple slaves formula high-speed serial communication system and the means of communication |
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Cited By (2)
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| CN110492965A (en) * | 2019-09-05 | 2019-11-22 | 南京南瑞继保电气有限公司 | The method and apparatus of serial message clock synchronization in a kind of master-slave system |
| CN112436970A (en) * | 2020-11-24 | 2021-03-02 | 深圳市易优电气有限公司 | Communication method, equipment slave machine, building equipment management system and storage medium |
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Application publication date: 20190219 |
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