CN102170229B - Balancing circuit configurable with threshold voltage - Google Patents
Balancing circuit configurable with threshold voltage Download PDFInfo
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- CN102170229B CN102170229B CN 201010622687 CN201010622687A CN102170229B CN 102170229 B CN102170229 B CN 102170229B CN 201010622687 CN201010622687 CN 201010622687 CN 201010622687 A CN201010622687 A CN 201010622687A CN 102170229 B CN102170229 B CN 102170229B
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Abstract
A balancing circuit configurable with threshold voltage comprises a threshold imbalance detector, a three state buffer and a selection circuit. An output signal Vout of the threshold imbalance detector and an output signal Vbody of the three state buffer are predesigned as Vdd/2. The Vout is fluctuated as technology and temperature change, the three state buffer detects and amplifies the Vout amplitude, the output signal Vbody provides offset body voltage of a logic gate, and adjustment values are fed back to body ends of a PMOS tube and an NMOS tube of the threshold imbalance detector to make the threshold imbalance detector adjust the PMOS/NMOS tube threshold voltage balance. The invention can relieve threshold voltage imbalance caused by technology deviation and support super wide voltage adjustment ranging from normal power supply voltage to sub-threshold power supply voltage.
Description
Technical field
The present invention relates to reduce in the integrated circuit (IC) design process deviation to the circuit of the impact of subthreshold value circuit, especially a kind of configurable threshold voltage balancing circuit simple in structure, high performance, it can alleviate technique change to the impact of subthreshold value design, and significantly improves the yield of subthreshold value design.
Background technology
Along with the development of integrated circuit (IC) design technology and integrated circuit fabrication process, the portable set demand that improves constantly is had higher requirement to reducing the power consumption designing technique.The subthreshold value design is the hot topic of current ultralow Consumption, the subthreshold value that enters circuit by reduction supply voltage (Vdd) is regional---and Vdd is less than threshold voltage (Vth), so that system works is at the linear zone of circuit, so significantly reduce system dynamically, quiescent dissipation.But this design has also been introduced a series of classes such as the problem to the tolerance variation of process deviation in concrete implementation procedure.Because in drive current and the threshold voltage exponent function relation of subthreshold value zone device, this is so that process deviation and device mismatch also are exponential variation to the impact of design performance.
The present invention focuses on and alleviates process deviation to the impact of subthreshold value design.Because the main source of technological parameter deviation is: (1) supply voltage Vdd fluctuation; (2) how much Leff fluctuations; (3) threshold voltage vt h fluctuation; And the fluctuation of the transistor performance that is wherein caused by threshold voltage fluctuation has occupied absolute important position, and the threshold voltage fluctuation that therefore reduces in the subthreshold value design has crucial meaning to the yield that improves the subthreshold value circuit.
Summary of the invention
The technical problem to be solved in the present invention is: there be the problem poor to the process deviation tolerance in existing subthreshold value design, need to alleviate process deviation to the impact of subthreshold value design, passing threshold voltage fluctuation of the present invention provides a kind of configurable threshold voltage balancing circuit.
Technical scheme of the present invention is: a kind of configurable threshold voltage balancing circuit, for digital circuit unit provides body bias, the body bias of the digital circuit unit that the regulation output end connects, described threshold voltage balancing circuit is made of the uneven detector of threshold value, tristate buffer and three parts of selection circuit, and the uneven detector of threshold value is provided with a PMOS pipe P1 and a NMOS pipe N1; Tristate buffer is provided with two PMOS pipes P2, P3, two NMOS pipe N2, N3 and a logic switch S0; Select circuit to be provided with a NMOS pipe N4 and a PMOS pipe P4, two logic switch S1, S2, concrete circuit is connected to:
The body end of the PMOS pipe P1 of the uneven detector of threshold value is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N1 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, the grid of PMOS pipe P1 links to each other with supply voltage Vdd with source class, the grid of NMOS pipe N1 links to each other with ground gnd with source class, the drain electrode that NMOS pipe N1 and PMOS the manage P1 output signal Vout that links together;
The output signal Vout of the uneven detector of threshold value links to each other with the PMOS pipe P2 of tristate buffer and the grid of NMOS pipe N2, the drain electrode of PMOS pipe P2 and NMOS pipe N2 links together, and link to each other with the grid of PMOS pipe P3 and NMOS pipe N3, the drain electrode of PMOS pipe P3 and the NMOS pipe N3 rear output signal Vbody that links together, PMOS manages P2, after linking together, the source class of P3 links to each other with the end of logic switch S0, the other end of logic switch S0 links to each other with supply voltage Vdd, NMOS manages N2, the source class of N3 links to each other with ground gnd, the body end of PMOS pipe P2 is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N2 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, and PMOS manages P3, the body end of N3 respectively with supply voltage Vdd, ground gnd links to each other.
The output signal Vbody of tristate buffer respectively with the logic switch S1 that selects circuit, the end of S2 links to each other, the other end of logic switch S1 links to each other with the drain electrode of PMOS pipe P4, the other end of logic switch S2 links to each other with the drain electrode of NMOS pipe N4, source class and the body end of PMOS pipe P4 are connected to supply voltage Vdd, drain electrode is connected with the PMOS body bias that is conditioned digital circuit unit, the mode select signal Ctrl control that grid is provided by the outside, source class and the body end of NMOS pipe N4 are connected to ground gnd, drain electrode is connected the mode select signal that grid is provided by the outside with the NMOS body bias that is conditioned digital circuit unit
Control.
Compared with prior art, the present invention has the following advantages and remarkable result:
(1) voltage-regulation of super wide range, through configuration, threshold voltage balancing circuit of the present invention can be supported the super wide range voltage-regulation from normal power voltage to subthreshold value supply voltage convergent-divergent, and namely threshold voltage balancing circuit of the present invention can work in superthreshold zone and subthreshold value zone;
(2) after the employing threshold voltage balancing, the imbalance of the threshold voltage of PMOS and nmos pass transistor is confined to a tighter zone, and namely threshold voltage balancing circuit of the present invention can effectively reduce the threshold voltage mismatch that process deviation causes;
(3) expense of the present invention is less, only is the circuit that is comprised of three negligible inverters, successful, and cost is little.And when system, can copy this scheme at whole chip block as required, to reduce in the wafer process deviation to the impact of system performance.
Description of drawings
Fig. 1 is configurable threshold voltage balancing circuit of the present invention.
Fig. 2 is the schematic diagram of transistor body effect biasing technique, (a) is the physical connection schematic diagram of transistor body effect, (b) is the circuit connection diagram of transistor body effect.
Fig. 3 is the threshold voltage fluctuation range that adopts configurable threshold voltage balancing circuit of the present invention and custom circuit under the condition of 3 σ process deviations.
Fig. 4 is the comparison diagram that a inverter adopts configurable threshold voltage balancing circuit of the present invention and conventional inverter transmission delay.
Embodiment
The objective of the invention is to overcome the defective of prior art, a kind of configurable voltage balancing circuit simple in structure, high performance is provided, threshold voltage balancing circuit of the present invention is to provide body bias for other digital circuit unit, by the control agent biasing, realizes the purpose of threshold voltage balance.In order to reduce in the subthreshold value design process deviation to the impact of circuit performance, transistorized threshold voltage mismatch in the design of balance subthreshold value, the fact that the present invention is directed to subthreshold device threshold voltage mismatch has designed a kind of configurable voltage balancing circuit simple in structure, high performance, this circuit can improve performance and the technique robustness of subthreshold value circuit, and then promotes the yield of subthreshold value design.
Referring to Fig. 1, configurable threshold voltage balancing circuit simple in structure, high performance of the present invention is made of the uneven detector of threshold value, tristate buffer and three parts of selection circuit, and the uneven detector of threshold value is provided with a PMOS pipe P1 and a NMOS pipe N1; Tristate buffer is provided with two PMOS pipes P2, P3, two NMOS pipe N2, N3 and a logic switch S0; Select circuit to be provided with a NMOS pipe N4 and a PMOS pipe P4, two logic switch S1, S2, concrete circuit is connected to:
The body end of the PMOS pipe P1 of the uneven detector of threshold value is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N1 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, the grid of PMOS pipe P1 links to each other with supply voltage Vdd with source class, the grid of NMOS pipe N1 links to each other with ground gnd with source class, the drain electrode that NMOS pipe N1 and PMOS the manage P1 output signal Vout that links together;
The output signal Vout of the uneven detector of threshold value links to each other with the PMOS pipe P2 of tristate buffer and the grid of NMOS pipe N2, the drain electrode of PMOS pipe P2 and NMOS pipe N2 links together, and link to each other with the grid of PMOS pipe P3 and NMOS pipe N3, the drain electrode of PMOS pipe P3 and the NMOS pipe N3 rear output signal Vbody that links together, PMOS manages P2, after linking together, the source class of P3 links to each other with the end of logic switch S0, the other end of logic switch S0 links to each other with supply voltage Vdd, NMOS manages N2, the source class of N3 links to each other with ground gnd, the body end of PMOS pipe P2 is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N2 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, and PMOS manages P3, the body end of N3 respectively with supply voltage Vdd, ground gnd links to each other.
The output signal Vbody of tristate buffer respectively with the logic switch S1 that selects circuit, the end of S2 links to each other, the other end of logic switch S1 links to each other with the drain electrode of PMOS pipe P4, the other end of logic switch S2 links to each other with the drain electrode of NMOS pipe N4, source class and the body end of PMOS pipe P4 are connected to supply voltage Vdd, drain electrode is connected with the PMOS body bias that is conditioned digital circuit unit, the mode select signal Ctrl control that grid is provided by the outside, NMOS pipe N4 source class and body end are connected to ground gnd, drain electrode is connected the mode select signal that grid is provided by the outside with the NMOS body bias that is conditioned digital circuit unit
Control.The Ctrl signal here is the signal that is provided by the external control logic, and control logic is according to need of work control Ctrl signal, and when Ctrl is low level (and switch S 0 disconnects S1, S2 closure), circuit working of the present invention is in the superthreshold pattern; Otherwise be operated in the subthreshold value pattern.
In the operating process of reality of the present invention, the present invention can enter according to different supply voltages different mode of operations.When the superthreshold pattern, logic switch S0 turn-offs, and therefore is configured in high impedance status at Three-State.At this moment, power switch transistor P4 and N4 open, and logic switch S1, S2 shutoff, be connected to Vdd so be conditioned the PMOS transistor body end of digital circuit unit, and NMOS pipe transistor body end are connected to gnd.Circuit of the present invention is when the subthreshold value pattern, and logic switch S0 opens, the tristate buffer normal operation, and under this pattern, logic switch S1, S2 open, and transistor P4 and N4 turn-off.Therefore, the output voltage V body of this buffering area provides the body bias of Digital Logic through S1, S2.
Specific works principle simple in structure, high performance configurable threshold voltage balancing circuit of the present invention is as follows:
In preamble, the present invention is the importance of clear and definite balance PMOS and nmos pass transistor threshold voltage.Consider that PMOS pipe threshold voltage Vthp is by different doping process control with NMOS pipe threshold voltage Vthn, the present invention utilizes transistorized bulk effect to adjust transistorized threshold voltage biasing.The adjustment principle of the threshold voltage that Fig. 2 shows, wherein V
BPAt the transistorized bias voltage of PMOS, V
BNVoltage is the bias voltage of NMOS pipe.
A simple threshold voltage balancing that the present invention proposes is referring to Fig. 1.The supply voltage of considering the subthreshold value circuit design is all the time less than | V
Th|, junction diode can not be opened, and the uneven detector of threshold voltage is comprised of the inverter that PMOS pipe and NMOS pipe all turn-off.Under typical process angle (TT), the output signal Vout of the uneven detector of threshold value and the output signal Vbody of tristate buffer are designed to Vdd/2 in advance.Vout fluctuates with the variation of flow-route and temperature, tristate buffer detects and the amplification Vout amplitude of oscillation, its output signal Vbody provides the offset body that is conditioned digital circuit unit voltage, this adjusted value can feed back to the PMOS pipe of the uneven detector of threshold value and the body end of NMOS pipe, further impels the uneven detector of threshold value to adjust PMOS/NMOS pipe threshold voltage Vth balance.For example, if the pull-down capability of NMOS network greater than drawing ability on the PMOS network, Vout will descend, and cause larger Vbody and descend.This decline will cause that the Vth of NMOS increases and the Vth of PMOS reduces, and alleviates the threshold voltage imbalance that process deviation causes.Through configuration, the design's threshold voltage balancing circuit can support the super wide voltage from normal power voltage to subthreshold value supply voltage convergent-divergent to regulate.
A, superthreshold operation
When the superthreshold pattern, logic switch S0 turn-offs, and therefore is configured in high impedance status at Three-State.At this moment, power switch transistor P4 and N4 open, and S1, S2 shutoff, so the digital circuit unit PMOS transistor body end that is conditioned is connected to Vdd, and NMOS pipe transistor body end is connected to gnd.Therefore configurable threshold voltage balancing circuit simple in structure, high performance of the present invention can not have a negative impact to the superthreshold performance of system.
B, subthreshold value operation
When the subthreshold value pattern, logic switch S0 opens, the Three-State normal operation.Under this pattern, logic switch S1, S2 open, and transistor P4 and N4 turn-off.Threshold voltage balance detection device is surveyed current threshold voltage mismatch situation, and the size that is converted into the Vout signal is exported, tristate buffer is accepted the input of Vout signal, and with the signal shaping amplification, the Vbody signal of output provides the body bias that is conditioned digital circuit unit through logic switch S1, S2 at last.For example, when the threshold voltage of NMOS hour, the magnitude of voltage of Vout can descend, and then causing the larger decline of Vbody value through after the amplification of tristate buffer, the threshold voltage rising that bias voltage descends and causes the NMOS pipe, the threshold voltage of PMOS pipe descends, and unbalanced like this threshold voltage is compensated.It should be noted that the necessary carefully size of design logic switch S 0, S1, S2 size is so that their equivalent conducting resistance Ron is enough little in order to avoid larger transistor voltage drop.What it must be admitted that is that less Ron has also improved the settling time of system.In the subthreshold value zone, the same transistorized equivalent conducting resistance Ron of scale becomes hundreds of times to its size in the superthreshold zone.If still adopt the PMOS transistor as the supply voltage switching transistor, it is very large that its size must arrange, and the area that brings thus and power consumption penalty will be that the designer is intolerable.Because nmos pass transistor has better current characteristics than PMOS transistor, the excessive driving transistors of grid terminal voltage of its raising, Ron and transistorized area just can greatly reduce, and have avoided simultaneously transistorized current potential to descend.Therefore, in design of the present invention, the small size NMOS that adopts grid to overdrive, the grid terminal voltage that improves here is to obtain from other high voltage.
The present invention ξ=(V
Out-V
Dd/ 2)/V
DdCharacterize Vth uneven, Vout is the uneven detector output of threshold voltage, referring to content shown in Figure 1.That is ξ is the degree that Vout departs from Vdd/2, and obviously, ξ is larger, and the Vth imbalance is larger.Fig. 3 has showed that existing design and the present invention adopt the fluctuation range of the threshold voltage of design under 3 σ process deviation conditions of threshold voltage balancing to compare.From figure, can obviously find out, after the employing threshold voltage balancing, be confined to a tighter zone after the threshold voltage imbalance of PMOS and nmos pass transistor.The more important thing is the circuit of expense for only being formed by three negligible inverters of design of the present invention, successful, cost is little.During system, can copy this scheme at whole chip block as required, to reduce in the wafer process deviation to the impact of system performance.
For further verifying the validity of the threshold voltage balancing that the present invention proposes, the below describes as an example of a inverter example, and the breadth length ratio of this inverter is as follows: (W/L)
p/ (W/L)
n=(280nm/120nm)/(200nm/120nm).Table 1 shown under the same conditions, with threshold voltage balancing and the minimum power supply voltage, that can not work with this inverter under the threshold voltage balancing condition.
The minimum power source voltage of table 1 130nm CMOS inverter
Obviously, the minimum power source voltage value with the threshold voltage balancing is starkly lower than the minimum power source voltage value of not being with the threshold voltage balancing.The main cause that causes this phenomenon is that the introducing of threshold voltage balancing is so that the V of inverter
Thn'+Δ
Thn=-(V
Thp'+Δ
Thp), as long as and then satisfy supply voltage
Inverter can work.When being the threshold voltage balance of PMOS and nmos pass transistor, required supply voltage value is minimum.
It is the main cause that causes thrashing that the gate transmission delay fluctuates with the impact of process deviation.The present invention investigate respectively as an example of inverter example equally with the threshold voltage balancing and not with same process deviation under the threshold voltage balancing condition on the impact of gate transmission delay.
Fig. 4 has represented (W/L)
p/ (W/L)
n=(1100nm/120nm)/(400nm/120nm) inverter considers when supply voltage is 200mV between wafer in the deviation and wafer under the condition of deviation, drives the transmission delay of a 5fF capacitive load.Can know discovery from figure, than original design, after the introducing threshold voltage balancing, inverter transmission delay standard deviation sigma has reduced by 4.7 times, and coefficient of variation σ/μ has reduced by 3.6 times.
Claims (1)
1. configurable threshold voltage balancing circuit, it is characterized in that providing body bias for digital circuit unit, the body bias of the digital circuit unit that the regulation output end connects, described threshold voltage balancing circuit is made of the uneven detector of threshold value, tristate buffer and three parts of selection circuit, and the uneven detector of threshold value is provided with a PMOS pipe P1 and a NMOS pipe N1; Tristate buffer is provided with two PMOS pipes P2, P3, two NMOS pipe N2, N3 and a logic switch S0; Select circuit to be provided with a NMOS pipe N4 and a PMOS pipe P4, two logic switch S1, S2, concrete circuit is connected to:
The body end of the PMOS pipe P1 of the uneven detector of threshold value is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N1 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, the grid of PMOS pipe P1 links to each other with supply voltage Vdd with source class, the grid of NMOS pipe N1 links to each other with ground gnd with source class, the drain electrode that NMOS pipe N1 and PMOS the manage P1 output signal Vout that links together;
The output signal Vout of the uneven detector of threshold value links to each other with the PMOS pipe P2 of tristate buffer and the grid of NMOS pipe N2, the drain electrode of PMOS pipe P2 and NMOS pipe N2 links together, and link to each other with the grid of PMOS pipe P3 and NMOS pipe N3, the drain electrode of PMOS pipe P3 and the NMOS pipe N3 rear output signal Vbody that links together, PMOS manages P2, after linking together, the source class of P3 links to each other with the end of logic switch S0, the other end of logic switch S0 links to each other with supply voltage Vdd, NMOS manages N2, the source class of N3 links to each other with ground gnd, the body end of PMOS pipe P2 is connected with the drain electrode of the PMOS pipe P4 that selects circuit, the body end of NMOS pipe N2 is connected with the drain electrode of the NMOS pipe N4 that selects circuit, and PMOS manages P3, the body end of N3 respectively with supply voltage Vdd, ground gnd links to each other;
The output signal Vbody of tristate buffer respectively with the logic switch S1 that selects circuit, the end of S2 links to each other, the other end of logic switch S1 links to each other with the drain electrode of PMOS pipe P4, the other end of logic switch S2 links to each other with the drain electrode of NMOS pipe N4, source class and the body end of PMOS pipe P4 are connected to supply voltage Vdd, the drain electrode be conditioned digital circuit unit in the PMOS body bias be connected, the mode select signal Ctrl control that grid is provided by the outside, source class and the body end of NMOS pipe N4 are connected to ground gnd, drain electrode is connected the mode select signal that grid is provided by the outside with the NMOS body bias that is conditioned digital circuit unit
Control.
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| CN102751979B (en) * | 2012-07-13 | 2016-01-20 | 上海交通大学 | A kind of full adder of subthreshold value low-power consumption |
| CN106712754B (en) * | 2015-08-04 | 2023-10-20 | 意法半导体研发(深圳)有限公司 | Dynamic threshold generator for adaptive body biasing of MOS |
| EP3611841B1 (en) * | 2018-08-13 | 2023-11-29 | Avago Technologies International Sales Pte. Limited | System and method for controlling the impact of process and temperature in passive signal detector for automotive ethernet |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101470459A (en) * | 2007-12-26 | 2009-07-01 | 中国科学院微电子研究所 | Low-voltage low-power consumption CMOS voltage reference circuit |
| CN101729027A (en) * | 2009-10-30 | 2010-06-09 | 华南理工大学 | High gain amplifier circuit |
| CN202043038U (en) * | 2010-12-31 | 2011-11-16 | 东南大学 | Configurable threshold voltage balancing circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101470459A (en) * | 2007-12-26 | 2009-07-01 | 中国科学院微电子研究所 | Low-voltage low-power consumption CMOS voltage reference circuit |
| CN101729027A (en) * | 2009-10-30 | 2010-06-09 | 华南理工大学 | High gain amplifier circuit |
| CN202043038U (en) * | 2010-12-31 | 2011-11-16 | 东南大学 | Configurable threshold voltage balancing circuit |
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