CN102751979B - A kind of full adder of subthreshold value low-power consumption - Google Patents
A kind of full adder of subthreshold value low-power consumption Download PDFInfo
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Abstract
The full adder that the invention provides a kind of subthreshold value low-power consumption has the first to the 3rd input, carry output and adds and output, the minimum operating voltage of described full adder is less than or equal to 0.21V, described full adder comprises, first order circuit, it exports termination first node, and described first order circuit is used for output carry coherent signal; Buffer, first node described in its input termination, it exports termination Section Point, and described Section Point connects described carry output; Second level circuit, Section Point described in its input termination, described second level circuit is used for output and adds and coherent signal.The full adder of subthreshold value low-power consumption of the present invention is applicable to subthreshold value low-voltage condition, circuit operating conditions covers all process corner and harsh temperature range (-40 DEG C to 100 DEG C), overcome the circuit characteristic deviation that process deviation in manufacture process brings, make circuit normally to work under various circumstances simultaneously, be applicable to the node circuit of radio sensing network.
Description
Technical field
The basic circuit unit in involved in the present invention is a kind of digital integrated circuit field, especially relates to a kind of full adder circuit of subthreshold value low-power consumption.
Background technology
Radio sensing network (WirelessSensorNetwork, be called for short WSN) be the current research field received much concern in the world, it combines sensor technology, embedding assembly technology, distributed information processing and wireless communication technique etc., by a large amount of, the network with the microsensor node composition of microprocessing capability carrys out Real-Time Monitoring synergistically, the information of various environment or monitoring target in perception and collection network overlay area, it is processed, information after these process is wirelessly sent out, and to be sent to user terminal from the network mode of group multi-hop, utilize to supply observer and analyze.These sensor nodes constitute the elementary cell of radio sensing network.
In wireless sensing network system, due to the finite capacity of battery, the processor in system node needs to have the life-span that extremely low power consumption could extend node.Less demanding for speed of the processor of these network nodes, we can design the node of circuit application in radio sensing network of subthreshold value like this.So-called subthreshold value circuit, refers to the Near Threshold or following of the operating voltage of circuit at transistor.
Fig. 1 is the structural representation of the present invention's full adder of the prior art, as shown in Figure 1, basic CMOS full adder main circuit is divided into first order circuit and second level circuit, the output Cob of first order circuit links output Co after an inverter, and the output Sb of second level circuit links output S after an inverter.
Data path is the core of processor, and typical data path is combined by such as arithmetic unit or logical-arithmetic unit, and wherein adder (being often referred to full adder) is the most frequently used in data path is also one of most crucial unit.Therefore the power consumption that its power consumption can reduce whole processor circuit is effectively reduced.The logic function of a full adder can be represented by following two Boolean expressions:
Wherein, A, B, Ci represent two inputs and carry input (carryin) of full adder respectively, and S, Co represent exporting with (sum) of full adder respectively and carry exports (carryout).
Due to square being directly proportional of dynamic power consumption and its supply power voltage (VDD) of CMOS (ComplementaryMetalOxideSemiconductor) door, the operating voltage therefore reducing circuit can effectively reduce the power consumption of circuit.Based on this reason, subthreshold value circuit has extremely low power consumption usually, and the speed of circuit is also slow simultaneously.
The method being designed with complete set of subthreshold value circuit and flow process.A set of ratio more complete subthreshold value circuit unit storehouse is devised based on this method and SMIC0.18 micron (μm) technology library.Wherein the minimum operating voltage of most of unit can reach 0.21 volt (Volts is called for short V), and the minimum operating voltage of full adder is at 0.23V, causes the minimum operating voltage of whole circuit to arrive 0.23V.The definition of minimum operating voltage is that under (-40 DEG C to 100 DEG C) and all process corner, circuit has the minimum value of the supply power voltage of correct logic function in certain temperature range.
Summary of the invention
The invention is intended to solve the problem, a kind of full adder is provided, enable its minimum operating voltage arrive below 0.21V.
For solving the problems of the technologies described above, the invention provides a kind of full adder of subthreshold value low-power consumption, have the first to the 3rd input, carry output and add and output, the minimum operating voltage of described full adder is less than or equal to 0.21V, and described full adder comprises,
First order circuit, it exports termination first node, and described first order circuit is used for output carry coherent signal;
Buffer, first node described in its input termination, it exports termination Section Point, and described Section Point connects described carry output;
Second level circuit, Section Point described in its input termination, described second level circuit is used for output and adds and coherent signal.
Further, described first order circuit comprises first order pull-up unit and first order drop-down unit, described first order pull-up unit is connected between high level end and described first node, described first order drop-down unit is connected between low level end and described first node, described first order pull-up unit is for exporting the carry signal of high level state, and described first order drop-down unit is used for the carry signal of output low level state.
Further, described first order pull-up unit comprises the first to the 5th transistor, wherein,
The source electrode of the first transistor connects high level end, and its grid connects first input end;
The source electrode of transistor seconds connects the drain electrode of described the first transistor, and the grid of described transistor seconds connects the second input;
The source electrode of third transistor connects the drain electrode of described transistor seconds, and the drain electrode of described third transistor connects described first node, and the grid of described third transistor connects first input end;
The source electrode of the 4th transistor connects high level end, and its drain electrode connects the drain electrode of described the first transistor, and the grid of described 4th transistor connects the second input;
The source electrode of the 5th transistor connects the drain electrode of described 4th transistor, and the drain electrode of described 5th transistor connects described first node, and the grid of described 5th transistor connects the 3rd input.
Further, the breadth length ratio of described the first transistor is 6 ~ 10, and the breadth length ratio of described transistor seconds and third transistor is 14 ~ 18, and the breadth length ratio of described 4th transistor and the 5th transistor is 6 ~ 10.
Further, the described first to the 5th transistor is PMOS.
Further, described first order drop-down unit comprises the 6th to the tenth transistor, wherein,
The drain electrode of the 6th transistor connects first node, and its grid connects the 3rd input;
The drain electrode of the 7th transistor connects the source electrode of the 6th transistor, and the source electrode of described 7th transistor connects low level end, and the grid of described 7th transistor connects first input end;
The drain electrode of the 8th transistor connects the source electrode of the 6th transistor, and the source electrode of described 8th transistor connects low level end, and the grid of described 8th transistor connects the second input;
The drain electrode of the 9th transistor connects first node, and its grid connects first input end;
The drain electrode of the tenth transistor connects the source electrode of described 9th transistor, and the source ground of described tenth transistor, the grid of described tenth transistor connects the second input.
Further, described 6th transistor is 2 ~ 6 to the breadth length ratio of the tenth transistor.
Further, described 6th to the tenth transistor is NMOS tube.
Further, described second level circuit comprises second level pull-up unit and second level drop-down unit, described second level pull-up unit is connected between high level end and the 3rd node, described second level drop-down unit is connected between low level end and described 3rd node, described second level pull-up unit is for exporting adding and signal of high level state, described second level drop-down unit is used for adding and signal of output low level state, adds and output described in described 3rd node connects.
Further, described second level pull-up unit comprises the 11 to the 17 transistor, wherein,
The source electrode of the 11 transistor connects high level end, and its grid connects the 3rd input;
The source electrode of the tenth two-transistor connects the drain electrode of described 11 transistor, and the grid of described tenth two-transistor connects Section Point, and the drain electrode of described tenth two-transistor connects the 3rd node;
The source electrode of the 13 transistor connects high level, and its grid connects first input end, and the drain electrode of described 13 transistor connects the drain electrode of described tenth two-transistor;
The source electrode of the 14 transistor connects high level, and its grid connects the second input, and its drain electrode connects the drain electrode of described 13 transistor;
The source electrode of the 15 transistor connects the drain electrode of described 14 transistor, and the grid of described 15 transistor connects first input end;
The source electrode of the 16 transistor connects the drain electrode of described 15 transistor, and the grid of the 16 transistor connects described second input;
The source electrode of the 17 transistor connects the drain electrode of described 16 transistor, and the grid of the 17 transistor connects described 3rd input, and the drain electrode of described 17 transistor connects described 3rd node.
Further, described 11 transistor is 6 ~ 10 to the breadth length ratio of the 14 transistor, and described 15 transistor is 20 ~ 28 to the breadth length ratio of the 17 transistor.
Further, described 11 to the 17 transistor is PMOS.
Further, described second level drop-down unit comprises the 18 to the 24 transistor, wherein,
The drain electrode of the 18 transistor connects the 3rd node, and its grid connects Section Point;
The drain electrode of the 19 transistor connects the source electrode of described 18 transistor, and the grid of described 19 transistor connects first input end, and the source electrode of described 19 transistor connects low level end;
The drain electrode of the 20 transistor connects the source electrode of described 18 transistor, and the grid of described 20 transistor connects the second input, and the source electrode of described 20 transistor connects low level end;
The drain electrode of the 21 transistor connects the source electrode of described 18 transistor, and the grid of described 21 transistor connects the 3rd input, and the source electrode of described 21 transistor connects low level end;
The drain electrode of the 20 two-transistor connects the 3rd node, and its grid connects the 3rd input;
The drain electrode of the 23 transistor connects the source electrode of described 20 two-transistor, and the grid of described 23 transistor connects described first input end;
The drain electrode of the 24 transistor connects the source electrode of described 23 transistor, and the grid of described 24 transistor connects described second input, and the drain electrode of described 24 transistor connects low level end.
Further, the breadth length ratio of described 18 transistor is 6 ~ 10, and described 19 transistor is 2 ~ 6 to the breadth length ratio of the 21 transistor, and described 20 two-transistor is 3 ~ 7 to the breadth length ratio of the 24 transistor.
Further, described 18 to the 24 transistor is nmos pass transistor.
Further, described 3rd node is connected with output with described adding by a CMOS reverser, described in add with coherent signal by after a described CMOS reverser from described add and output export sum output signal.
Further, described Section Point is connected with described carry output by the 2nd CMOS reverser, and described carry coherent signal is by outputing signal from described carry output output carry after described 2nd CMOS inverter.
Further, described buffer is formed by the cascade of even number CMOS reverser.
Further, described full adder is used for normally working in all process corner and-40 DEG C ~ 80 DEG C.
In sum, the present invention is compared with full adder in prior art, and circuit tool of the present invention has the following advantages:
Can carry out work under extremely low supply power voltage condition, this design is applicable to subthreshold value low-voltage condition.In the present invention, by the emulation of SPICE model, to guarantee the accurate of circuit function and stability.
Circuit operating conditions covers all process corner and harsh temperature range (-40 DEG C to 100 DEG C), this just overcomes the circuit characteristic deviation that process deviation in manufacture process brings, make circuit normally to work under various circumstances simultaneously, be applicable to the node circuit of radio sensing network.
The minimum operating voltage of this circuit can reach 0.21V.The reduction of minimum voltage can make the operating voltage in whole subthreshold value circuit unit storehouse reduce, and brings the reduction of integrated circuit power consumption.
Accompanying drawing explanation
Fig. 1 is the structural representation of full adder of the prior art.
Fig. 2 is the full adder structural representation of subthreshold value low-power consumption in one embodiment of the invention.
Fig. 3 is the structural representation of a CMOS reverser in one embodiment of the invention.
Fig. 4 is the structural representation of the 2nd CMOS reverser in one embodiment of the invention.
Fig. 5 is the structural representation of buffer in one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
In the present embodiment, the following stated high level end connects external power source usually, the usual ground connection of described low level end.
Fig. 2 is the structural representation of the full adder of subthreshold value low-power consumption in one embodiment of the invention.Composition graphs 2, the invention provides a kind of full adder of subthreshold value low-power consumption, there is first input end A, the second input B, the 3rd input Ci, carry output Co and add and output S, the minimum operating voltage of full adder of the present invention is less than or equal to 0.21V, described full adder comprises: first order circuit 100, second level circuit 200 and buffer 300, described first order circuit 100 exports termination first node N1, and described first order circuit 100 is for output carry coherent signal; First node N1 described in the input termination of described buffer 300; Section Point N2 described in the input termination of described second level circuit 200, described second level circuit 200 adds and coherent signal for exporting; The output termination Section Point N2 of described buffer 300, described Section Point N2 meets described carry output Co.
Further, described first order circuit comprises first order pull-up unit PU1 and first order drop-down unit PD1, described first order pull-up unit PU1 is connected between high level end and described first node N1, described first order drop-down unit PD1 is connected between low level end and described first node N1, described first order pull-up unit PU1 is for exporting the carry signal of high level state, and described first order drop-down unit PD1 is used for the carry signal of output low level state.
In the present embodiment, described first order pull-up unit PU1 comprises the first to the 5th transistor, and the described first to the 5th transistor is PMOS, wherein,
The source electrode of the first transistor M1 connects high level end, and its grid meets first input end A;
The source electrode of transistor seconds M2 connects the drain electrode of described the first transistor M1, and the grid of described transistor seconds M2 meets the second input B;
The source electrode of third transistor M3 connects the drain electrode of described transistor seconds M2, and the drain electrode of described third transistor M3 meets described first node N1, and the grid of described third transistor meets first input end A;
The source electrode of the 4th transistor M4 connects high level end, and its drain electrode connects the drain electrode of described the first transistor M1, and the grid of described 4th transistor M4 meets the second input B;
The source electrode of the 5th transistor M5 connects the drain electrode of described 4th transistor M4, and the drain electrode of described 5th transistor M5 meets described first node N1, and the grid of described 5th transistor M5 meets the 3rd input Ci.
In the present embodiment, described first order drop-down unit PD1 comprises the 6th to the tenth transistor, and described 6th to the tenth transistor is NMOS tube, wherein,
The drain electrode of the 6th transistor M6 meets first node N1, and its grid meets the 3rd input Ci;
The drain electrode of the 7th transistor M7 connects the source electrode of the 6th transistor M6, and the source electrode of described 7th transistor M7 connects low level end, and the grid of described 7th transistor M7 meets first input end A;
The drain electrode of the 8th transistor M8 connects the source electrode of the 6th transistor M6, and the source electrode of described 8th transistor M8 connects low level end, and the grid of described 8th transistor M8 meets the second input B;
The drain electrode of the 9th transistor M9 meets first node N1, and its grid meets first input end A;
The drain electrode of the tenth transistor M10 connects the source electrode of described 9th transistor M3, and the source ground of described tenth transistor M10, the grid of described tenth transistor M10 meets the second input B.
Further, described second level circuit comprises second level pull-up unit PU2 and second level drop-down unit PD2, described second level pull-up unit PU2 is connected between high level end and described 3rd node N3, described second level drop-down unit PD2 is connected between low level end and described 3rd node N3, described second level pull-up unit PU2 is for exporting adding and signal of high level state, described second level drop-down unit PD2 is used for adding and signal of output low level state, adds and output described in described 3rd node N3 connects.
In the present embodiment, described second level pull-up unit PU2 comprises the 11 to the 17 transistor, and described 11 to the 17 transistor is PMOS, wherein,
The source electrode of the 11 transistor M11 connects high level end, and its grid meets the 3rd input Ci;
The source electrode of the tenth two-transistor M12 connects the drain electrode of described 11 transistor M11, and the grid of described tenth two-transistor M12 meets Section Point N2, and the drain electrode of described tenth two-transistor M12 meets the 3rd node N3;
The source electrode of the 13 transistor M13 connects high level, and its grid meets first input end A, and the drain electrode of described 13 transistor M13 connects the drain electrode of described tenth two-transistor M12;
The source electrode of the 14 transistor M14 connects high level, and its grid meets the second input B, and its drain electrode connects the drain electrode of described 13 transistor M13;
The source electrode of the 15 transistor M15 connects the drain electrode of described 14 transistor M14, and the grid of described 15 transistor M15 meets first input end A;
The source electrode of the 16 transistor M16 connects the drain electrode of described 15 transistor M15, and the grid of the 16 transistor M16 meets described second input B;
The source electrode of the 17 transistor M17 connects the drain electrode of described 16 transistor M16, and the grid of the 17 transistor M17 meets described 3rd input Ci, and the M17 drain electrode of described 17 transistor meets described 3rd node N3.
In an embodiment, described second level drop-down unit PD2 comprises the 18 to the 24 transistor, and described 18 to the 24 transistor is nmos pass transistor, wherein,
The drain electrode of the 18 transistor M18 meets the 3rd node N3, and its grid meets Section Point N2;
The drain electrode of the 19 transistor M19 connects the source electrode of described 18 transistor M18, and the grid of described 19 transistor M19 meets first input end A, and the source electrode of described 19 transistor M19 connects low level end;
The drain electrode of the 20 transistor M20 connects the source electrode of described 18 transistor, and the grid of described 20 transistor M20 meets the second input B, and the source electrode of described 20 transistor M20 connects low level end;
The drain electrode of the 21 transistor M21 connects the source electrode of described 18 transistor M18, and the grid of described 21 transistor M21 connects the 3rd input, and the source electrode of described 21 transistor M21 connects low level end;
The drain electrode of the 20 two-transistor M22 meets the 3rd node N3, and its grid meets the 3rd input Ci;
The drain electrode of the 23 transistor M23 connects the source electrode of described 20 two-transistor M22, and the grid of described 23 transistor M23 meets described first input end A;
The drain electrode of the 24 transistor M24 connects the source electrode of described 23 transistor M23, and the grid of described 24 transistor M24 meets described second input B, and the drain electrode of described 24 transistor M24 connects low level end.
Fig. 3 is the structural representation of a CMOS reverser in one embodiment of the invention.Composition graphs 2 and Fig. 3, further, described 3rd node N3 is connected with output with described adding by a CMOS reverser INV1, described add with coherent signal by after a described CMOS reverser INV1 from described add and output S export sum output signal, a described CMOS reverser INV1 comprises the 25 transistor M25 and the 26 transistor M26, described 25 transistor M25 is PMOS transistor, its source electrode connects high level end, its grid meets the 3rd node N3, add and output S described in its drain electrode connects, 26 transistor M26 is nmos pass transistor, its drain electrode is connected with the drain electrode of described 25 transistor M25, the source electrode of described 26 transistor M26 connects low level end, the grid of described 26 transistor M26 meets the 3rd node N3.
Fig. 4 is the structural representation of the 2nd CMOS reverser in one embodiment of the invention.Composition graphs 2 and Fig. 4, further, described Section Point N2 is connected with described carry output Co2 by the 2nd CMOS reverser INV2, described carry coherent signal is by outputing signal from described carry output Co output carry after described 2nd CMOS inverter INV2, described 2nd CMOS reverser INV2 comprises the 27 transistor M27 and the 28 transistor M28, described 27 transistor M27 is PMOS transistor, its source electrode connects high level, its grid meets Section Point N2, its drain electrode meets described carry output Co, 28 transistor M28 is nmos pass transistor, its drain electrode is connected with the drain electrode of described 27 transistor M27, the source electrode of described 28 transistor M28 connects low level end, the grid of described 28 transistor M28 meets Section Point N2.
Fig. 5 is the structural representation of buffer in one embodiment of the invention.In the present embodiment, described buffer is formed by the cascade of even number CMOS reverser, and in preferred embodiment, described buffer is formed by two CMOS reverser-three CMOS reverser INV3 and the 4th CMOS reverser INV4 successively cascade.Further, described 3rd CMOS reverser INV3 comprises the 29 transistor M29 and the 30 transistor M30, described 29 transistor M29 is PMOS transistor, its source electrode connects high level, its grid meets first node N1, and the 30 transistor M30 is nmos pass transistor, and its drain electrode is connected with the drain electrode of described 29 transistor M29, the source electrode of described 30 transistor M30 connects low level end, and the grid of described 30 transistor M30 meets first node N1; Described 4th CMOS reverser INV4 comprises the 31 transistor M31 and the 30 two-transistor M32, described 31 transistor M31 is PMOS transistor, its source electrode connects high level, its grid connects the drain electrode of described 29 transistor M29,30 two-transistor M32 is nmos pass transistor, its drain electrode is connected with the drain electrode of described 31 transistor M31, and the source electrode of described 30 two-transistor M32 connects low level end, and the grid of described 30 two-transistor M32 meets Section Point N2.
Full adder of the present invention is used for normally working in all process corner and-40 DEG C ~ 100 DEG C.The circuit design of described full adder take into account the impact that process corner and temperature deviation bring, the size of transistor is redesigned, circuit passes through the emulation of SPICE model under all process corner and harsh temperature range (-40 DEG C to 100 DEG C), to guarantee the accurate of circuit function and stability.
In preferred embodiment, the breadth length ratio of each transistor is as shown in table 1.The breadth length ratio of the 18 transistor M18 is 3 ~ 5 in the prior art, and the breadth length ratio of the 18 transistor M18 of the present invention is 6 ~ 10.The M18 increased can increase the pull-down capability of PD2 network, thus can to correct under SF process corner and 100 DEG C time, the output Sb of second level circuit exports the failure conditions for not reaching low level logic swing time low.
Table 1
| MOSFET | M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 | M9 | M10 | M11 |
| W/L | 6～10 | 14～18 | 14～18 | 6～10 | 6～10 | 2～6 | 2～6 | 2～6 | 2～6 | 2～6 | 6～10 |
| MOSFET | M12 | M13 | M14 | M15 | M16 | M17 | M18 | M19 | M20 | M21 | M22 |
| W/L | 6～10 | 6～10 | 6～10 | 20～28 | 20～28 | 20～28 | 6～10 | 2～6 | 2～6 | 2～6 | 3～7 |
| MOSFET | M23 | M24 | M25 | M26 | M27 | M28 | M29 | M30 | M31 | M32 | |
| W/L | 3～7 | 3～7 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 |
In order to achieve the above object, present invention employs technical scheme.
1) make the breadth length ratio of each transistor of basic CMOS full adder according to subthreshold value circuit design method, the minimum operating voltage of this structure is 0.21V after tested.Under the supply power voltage of 0.21V, this structure is emulated, find out the phenomenon of its lost efficacy (i.e. occurrence logic mistake).Always have two kinds of failure conditions.
2) the first failure conditions occurs in carry output Co, proposes modified node method for this kind of failure conditions.The buffer that the inverter adding two series connection between first order circuit and second level circuit is formed.Before improvement, the output Cob of first order circuit exports as time low level, and now the level of the output Cob of first order circuit maintains 15.44mV.After adding the inverter (Buffer) of two series connection, under this kind of condition, the low level of the output Cob of first order circuit is 5.4mV, is greatly improved, and does not also destroy the level index under other conditions simultaneously.
3) the second failure conditions occurs in and adds and output S, proposes modified node method for this kind of failure conditions.By 2 times that the adjusted size of second level M21 transistor is original.Before improvement, the output Sb of second level circuit exports as time low level, and now the level of the output Sb of second level circuit maintains 22mV.After doubling the size of M21 transistor, under this kind of condition, the low level of the output Sb of second level circuit is 16.4mV, is greatly improved, and does not also destroy the level index under other conditions simultaneously.
In sum, the present invention is compared with full adder in prior art, and circuit tool of the present invention has the following advantages:
Can carry out work under extremely low supply power voltage condition, this design is applicable to subthreshold value low-voltage condition.In the present invention, by the emulation of SPICE model, to guarantee the accurate of circuit function and stability.
Circuit operating conditions covers all process corner and harsh temperature range (-40 DEG C to 100 DEG C), this just overcomes the circuit characteristic deviation that process deviation in manufacture process brings, make circuit normally to work under various circumstances simultaneously, be applicable to the node circuit of radio sensing network.
The minimum operating voltage of this circuit can reach 0.21V.The reduction of minimum voltage can make the operating voltage in whole subthreshold value circuit unit storehouse reduce, and brings the reduction of integrated circuit power consumption.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (13)
1. a full adder for subthreshold value low-power consumption, have the first to the 3rd input, carry output and add and output, it is characterized in that, the minimum operating voltage of described full adder is less than or equal to 0.21V, and described full adder comprises,
First order circuit, it exports termination first node, and described first order circuit is used for output carry coherent signal;
Buffer, first node described in its input termination, it exports termination Section Point, and described Section Point connects described carry output;
Second level circuit, Section Point described in its input termination, described second level circuit is used for output and adds and coherent signal;
Described first order circuit comprises first order pull-up unit and first order drop-down unit, described first order pull-up unit is connected between high level end and described first node, described first order drop-down unit is connected between low level end and described first node, described first order pull-up unit is for exporting the carry signal of high level state, and described first order drop-down unit is used for the carry signal of output low level state;
Described first order pull-up unit comprises the first to the 5th transistor, and wherein, the source electrode of the first transistor connects high level end, and its grid connects first input end; The source electrode of transistor seconds connects the drain electrode of described the first transistor, and the grid of described transistor seconds connects the second input; The source electrode of third transistor connects the drain electrode of described transistor seconds, and the drain electrode of described third transistor connects described first node, and the grid of described third transistor connects first input end; The source electrode of the 4th transistor connects high level end, and its drain electrode connects the drain electrode of described the first transistor, and the grid of described 4th transistor connects the second input; The source electrode of the 5th transistor connects the drain electrode of described 4th transistor, and the drain electrode of described 5th transistor connects described first node, and the grid of described 5th transistor connects the 3rd input;
Described first order drop-down unit comprises the 6th to the tenth transistor, and wherein, the drain electrode of the 6th transistor connects first node, and its grid connects the 3rd input; The drain electrode of the 7th transistor connects the source electrode of the 6th transistor, and the source electrode of described 7th transistor connects low level end, and the grid of described 7th transistor connects first input end; The drain electrode of the 8th transistor connects the source electrode of the 6th transistor, and the source electrode of described 8th transistor connects low level end, and the grid of described 8th transistor connects the second input; The drain electrode of the 9th transistor connects first node, and its grid connects first input end; The drain electrode of the tenth transistor connects the source electrode of described 9th transistor, the source ground of described tenth transistor, and the grid of described tenth transistor connects the second input;
Described second level circuit comprises second level pull-up unit and second level drop-down unit, described second level pull-up unit is connected between high level end and the 3rd node, described second level drop-down unit is connected between low level end and the 3rd node, described second level pull-up unit is for exporting adding and signal of high level state, described second level drop-down unit is used for adding and signal of output low level state, adds and output described in the 3rd node connects;
Described second level pull-up unit comprises the 11 to the 17 transistor, and wherein, the source electrode of the 11 transistor connects high level end, and its grid connects the 3rd input; The source electrode of the tenth two-transistor connects the drain electrode of described 11 transistor, and the grid of described tenth two-transistor connects Section Point, and the drain electrode of described tenth two-transistor connects the 3rd node; The source electrode of the 13 transistor connects high level, and its grid connects first input end, and the drain electrode of described 13 transistor connects the drain electrode of described tenth two-transistor; The source electrode of the 14 transistor connects high level, and its grid connects the second input, and its drain electrode connects the drain electrode of described 13 transistor; The source electrode of the 15 transistor connects the drain electrode of described 14 transistor, and the grid of described 15 transistor connects first input end; The source electrode of the 16 transistor connects the drain electrode of described 15 transistor, and the grid of the 16 transistor connects described second input; The source electrode of the 17 transistor connects the drain electrode of described 16 transistor, and the grid of the 17 transistor connects described 3rd input, and the drain electrode of described 17 transistor connects the 3rd node;
Described second level drop-down unit comprises the 18 to the 24 transistor, and wherein, the drain electrode of the 18 transistor connects the 3rd node, and its grid connects Section Point; The drain electrode of the 19 transistor connects the source electrode of described 18 transistor, and the grid of described 19 transistor connects first input end, and the source electrode of described 19 transistor connects low level end; The drain electrode of the 20 transistor connects the source electrode of described 18 transistor, and the grid of described 20 transistor connects the second input, and the source electrode of described 20 transistor connects low level end; The drain electrode of the 21 transistor connects the source electrode of described 18 transistor, and the grid of described 21 transistor connects the 3rd input, and the source electrode of described 21 transistor connects low level end; The drain electrode of the 20 two-transistor connects the 3rd node, and its grid connects the 3rd input; The drain electrode of the 23 transistor connects the source electrode of described 20 two-transistor, and the grid of described 23 transistor connects described first input end; The drain electrode of the 24 transistor connects the source electrode of described 23 transistor, and the grid of described 24 transistor connects described second input, and the drain electrode of described 24 transistor connects low level end.
2. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, the breadth length ratio of described the first transistor is 6 ~ 10, and the breadth length ratio of described transistor seconds and third transistor is 14 ~ 18, and the breadth length ratio of described 4th transistor and the 5th transistor is 6 ~ 10.
3. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, the described first to the 5th transistor is PMOS.
4. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 6th transistor is 2 ~ 6 to the breadth length ratio of the tenth transistor.
5. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 6th to the tenth transistor is NMOS tube.
6. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 11 transistor is 6 ~ 10 to the breadth length ratio of the 14 transistor, and described 15 transistor is 20 ~ 28 to the breadth length ratio of the 17 transistor.
7. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 11 to the 17 transistor is PMOS.
8. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, the breadth length ratio of described 18 transistor is 6 ~ 10, described 19 transistor is 2 ~ 6 to the breadth length ratio of the 21 transistor, and described 20 two-transistor is 3 ~ 7 to the breadth length ratio of the 24 transistor.
9. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 18 to the 24 transistor is nmos pass transistor.
10. the full adder of subthreshold value low-power consumption as claimed in claim 1, it is characterized in that, described 3rd node is connected with output with described adding by a CMOS reverser, described in add with coherent signal by after a described CMOS reverser from described add and output export sum output signal.
11. as the full adder of the subthreshold value low-power consumption in claim 1 to 10 as described in any one, it is characterized in that, described Section Point is connected with described carry output by the 2nd CMOS reverser, and described carry coherent signal is by outputing signal from described carry output output carry after described 2nd CMOS inverter.
12. as the full adder of the subthreshold value low-power consumption in claim 1 to 10 as described in any one, and it is characterized in that, described buffer is formed by the cascade of even number CMOS reverser.
13., as the full adder of the subthreshold value low-power consumption in claim 1 to 10 as described in any one, is characterized in that, described full adder is used for normally working in all process corner and-40 DEG C ~ 80 DEG C.
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| US9471278B2 (en) * | 2014-09-25 | 2016-10-18 | Texas Instruments Incorporated | Low area full adder with shared transistors |
| CN104467815B (en) * | 2014-12-05 | 2017-12-15 | 北京大学 | A kind of double track preliminary filling logic p-type and N-type full adder circuit based on delay |
| CN107403052B (en) * | 2017-08-03 | 2019-11-01 | 电子科技大学 | A kind of design method of the Low dark curient standard block suitable for nearly threshold value and subthreshold value |
| CN113590082A (en) * | 2021-06-28 | 2021-11-02 | 杭州电子科技大学 | Three-value memory resistance full adder circuit based on character operation |
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