CN102751979A - Full adder with sub-threshold and low power consumption - Google Patents
Full adder with sub-threshold and low power consumption Download PDFInfo
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- CN102751979A CN102751979A CN2012102435418A CN201210243541A CN102751979A CN 102751979 A CN102751979 A CN 102751979A CN 2012102435418 A CN2012102435418 A CN 2012102435418A CN 201210243541 A CN201210243541 A CN 201210243541A CN 102751979 A CN102751979 A CN 102751979A
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Abstract
The invention provides a full adder with sub-threshold and low power consumption, which is provided with a first input end, a second input end, a third input end, a carry output end and a sum output end; the lowest working voltage of the full adder is less than or equal to 0.21V; the full adder comprises a first-level circuit, a buffer and a second-level circuit; the output end of the first-level circuit is connected with a first node; the first-level circuit is used for outputting a carry related signal; the input end of the buffer is connected with the first node; the output end of the buffer is connected with a second node; the second node is connected with the carry output end; the input end of the second-level circuit is connected with the second node; and the second-level circuit is used for outputting a sum related signal. The full adder with sub-threshold and low power consumption provided by the invention is suitable for the conditions of sub-threshold and low voltage; a circuit working condition covers all the technical angles and a harsh temperature scope (minus 40 DEG C to 100 DEG C); the circuit characteristic deviation brought by the technical deviation in a manufacturing process is overcome; the circuit can normally work under different conditions; and the full adder is suitable for a node circuit of a wireless sensing network.
Description
Technical field
Involved in the present invention is the basic circuit unit in a kind of digital integrated circuit field, especially relates to a kind of full adder circuit of subthreshold value low-power consumption.
Background technology
Radio sensing network (Wireless Sensor Network; Be called for short WSN) be the current research field that receives much concern in the world; It combines sensor technology, embedded computing technique, distributed information processing and wireless communication technique etc.; The network of forming through microsensor node a large amount of, that have microprocessing capability to monitor in real time synergistically, the information of various environment or monitoring target in perception and the collection network overlay area, and it is handled, and the information after these are handled is sent out through wireless mode; And be sent to user terminal with the network mode of organizing multi-hop certainly, utilize and analyze to supply with the observer.These sensor nodes have constituted the elementary cell of radio sensing network.
In wireless sensing network system, because the finite capacity of battery, the processor in the system node need have the life-span that extremely low power consumption could prolong node.The processor of these network nodes is less demanding for speed, and we can design the node of the circuit application of subthreshold value in radio sensing network like this.So-called subthreshold value circuit, the operating voltage that is meant circuit near the transistorized threshold value or below.
Fig. 1 is the structural representation of the present invention's full adder of the prior art; As shown in Figure 1; Basic CMOS full adder main circuit is divided into first order circuit and second level circuit; The output Cob of first order circuit links output Co behind an inverter, the output Sb of second level circuit links output S behind an inverter.
Data path is the core of processor, and typical data path is by combining like arithmetic unit or logical-arithmetic unit, wherein adder (being often referred to full adder) be the most frequently used in the data path also be one of most crucial unit.Therefore reduce the power consumption that its power consumption can reduce entire process device circuit effectively.The logic function of a full adder can be represented by following two Boolean expressions:
Wherein, A, B, Ci represent two inputs and the carry input (carry in) of full adder respectively, and what S, Co represented full adder respectively exports (carry out) with (sum) output with carry.
Because square being directly proportional of the dynamic power consumption of a CMOS (Complementary Metal Oxide Semiconductor) door and its supply power voltage (VDD), so the operating voltage that reduces circuit can effectively reduce the power consumption of circuit.Based on this reason, the subthreshold value circuit has extremely low power consumption usually, and the speed of circuit is also slow simultaneously.
The subthreshold value circuit be designed with complete method and the flow process of a cover.Designed the more complete subthreshold value circuit unit storehouse of a cover based on this method and 0.18 micron (μ m) technology library of SMIC.Wherein the minimum operating voltage of most of unit can reach 0.21 volt (Volts is called for short V), and the minimum operating voltage of full adder causes the minimum operating voltage of entire circuit can only arrive 0.23V at 0.23V.The definition of minimum operating voltage be in certain temperature range under (40 ℃ to 100 ℃) and all process corner circuit have the minimum value of the supply power voltage of correct logic functions.
Summary of the invention
The invention is intended to address the above problem, a kind of full adder is provided, its minimum operating voltage can be arrived below the 0.21V.
For solving the problems of the technologies described above, the present invention provides a kind of full adder of subthreshold value low-power consumption, has first to the 3rd input, carry output and adds and output, and the minimum operating voltage of said full adder is smaller or equal to 0.21V, and said full adder comprises,
First order circuit, its output termination first node, said first order circuit is used for the output carry coherent signal;
Buffer, the said first node of its input termination, its output termination Section Point, said Section Point connects said carry output;
Second level circuit, the said Section Point of its input termination, said second level circuit is used for output and adds and coherent signal.
Further; Said first order circuit comprises first order pull-up unit and the drop-down unit of the first order; Said first order pull-up unit is connected between high level end and the said first node; The drop-down unit of the said first order is connected between low level end and the said first node, and said first order pull-up unit is used to export the carry signal of high level state, and the drop-down unit of the said first order is used for the carry signal of output low level state.
Further, said first order pull-up unit comprises first to the 5th transistor, wherein,
The source electrode of the first transistor connects the high level end, and its grid connects first input end;
The source electrode of transistor seconds connects the drain electrode of said the first transistor, and the grid of said transistor seconds connects second input;
The 3rd transistorized source electrode connects the drain electrode of said transistor seconds, and said the 3rd transistor drain connects said first node, and the said the 3rd transistorized grid connects first input end;
The 4th transistorized source electrode connects the high level end, and its drain electrode connects the drain electrode of said the first transistor, and the said the 4th transistorized grid connects second input;
The 5th transistorized source electrode connects said the 4th transistor drain, and said the 5th transistor drain connects said first node, and the said the 5th transistorized grid connects the 3rd input.
Further, the breadth length ratio of said the first transistor is 6～10, and said transistor seconds and the 3rd transistorized breadth length ratio are 14～18, and said the 4th transistor and the 5th transistorized breadth length ratio are 6～10.
Further, said first to the 5th transistor is the PMOS pipe.
Further, the drop-down unit of the said first order comprises the 6th to the tenth transistor, wherein,
The 6th transistor drain connects first node, and its grid connects the 3rd input;
The 7th transistor drain connects the 6th transistorized source electrode, and the said the 7th transistorized source electrode connects low level end, and the said the 7th transistorized grid connects first input end;
The 8th transistor drain connects the 6th transistorized source electrode, and the said the 8th transistorized source electrode connects low level end, and the said the 8th transistorized grid connects second input;
The 9th transistor drain connects first node, and its grid connects first input end;
The tenth transistor drain connects the said the 9th transistorized source electrode, the said the tenth transistorized source ground, and the said the tenth transistorized grid connects second input.
Further, said the 6th transistor to the ten transistorized breadth length ratios are 2～6.
Further, said the 6th to the tenth transistor is the NMOS pipe.
Further; Said second level circuit comprises the drop-down unit of the second level pull-up unit and the second level; Said first order pull-up unit is connected between high level end and said the 3rd node, and drop-down unit, the said second level is connected between low level end and said the 3rd node, and said second level pull-up unit is used to export adding and signal of high level state; Drop-down unit, the said second level is used for adding of output low level state and signal, and said the 3rd node connects said adding and output.
Further, said second level pull-up unit comprises the 11 to the 17 transistor, wherein,
The 11 transistorized source electrode connects the high level end, and its grid connects the 3rd input;
The source electrode of the tenth two-transistor connects said the 11 transistor drain, and the grid of said the tenth two-transistor connects Section Point, and the drain electrode of said the tenth two-transistor connects the 3rd node;
The 13 transistorized source electrode connects high level, and its grid connects first input end, and said the 13 transistor drain connects the drain electrode of said the tenth two-transistor;
The 14 transistorized source electrode connects high level, and its grid connects second input, and its drain electrode connects said the 13 transistor drain;
The 15 transistorized source electrode connects said the 14 transistor drain, and the said the 15 transistorized grid connects first input end;
The 16 transistorized source electrode connects said the 15 transistor drain, and the 16 transistorized grid connects said second input;
The 17 transistorized source electrode connects said the 16 transistor drain, and the 17 transistorized grid connects said the 3rd input, and said the 17 transistor drain connects said the 3rd node.
Further, said the 11 transistor to the 14 transistorized breadth length ratios are 6～10, and said the 15 transistor to the 17 transistorized breadth length ratios are 20～28.
Further, said the 11 to the 17 transistor is the PMOS pipe.
Further, drop-down unit, the said second level comprises the 18 to the 24 transistor, wherein,
The 18 transistor drain connects the 3rd node, and its grid connects Section Point;
The 19 transistor drain connects the said the 18 transistorized source electrode, and the said the 19 transistorized grid connects first input end, and the said the 19 transistorized source electrode connects low level end;
The 20 transistor drain connects the said the 18 transistorized source electrode, and the said the 20 transistorized grid connects second input, and the said the 20 transistorized source electrode connects low level end;
The 21 transistor drain connects the said the 18 transistorized source electrode, and the said the 21 transistorized grid connects the 3rd input, and the said the 21 transistorized source electrode connects low level end;
The drain electrode of the 20 two-transistor connects the 3rd node, and its grid connects the 3rd input;
The 23 transistor drain connects the source electrode of said the 20 two-transistor, and the said the 23 transistorized grid connects said first input end;
The 24 transistor drain connects the said the 23 transistorized source electrode, and the said the 24 transistorized grid connects said second input, and said the 24 transistor drain connects low level end.
Further, the said the 18 transistorized breadth length ratio is 6～10, and said the 19 transistor to the 21 transistorized breadth length ratios are 2～6, and said the 20 two-transistor to the 24 transistorized breadth length ratios are 3～7.
Further, said the 18 to the 24 transistor is a nmos pass transistor.
Further, said the 3rd node links to each other with said adding with output through a CMOS reverser, and said adding with coherent signal adds and output output sum output signal from said after through a said CMOS reverser.
Further, said Section Point links to each other with said carry output through the 2nd CMOS reverser, and said carry coherent signal is exported signal from said carry output output carry after through said the 2nd CMOS inverter.
Further, said buffer is formed by the cascade of even number CMOS reverser.
Further, said full adder is used for operate as normal in all process corner reach-40 ℃～80 ℃.
In sum, full adder is compared in the present invention and the prior art, and circuit of the present invention has following advantage:
Can under extremely low supply power voltage condition, carry out work, this design is applicable to the subthreshold value low.In the present invention, through the emulation of SPICE model, to guarantee the accurate and stable of circuit function.
The circuit working condition covers all process corner and harsh temperatures scope (40 ℃ to 100 ℃); This has just overcome the circuit characteristic deviation that process deviation brings in the manufacture process; Make circuit to be applicable to the node circuit of radio sensing network simultaneously in operate as normal under the varying environment.
The minimum operating voltage of this circuit can reach 0.21V.The reduction of minimum voltage can make the operating voltage in whole subthreshold value circuit unit storehouse reduce the reduction that brings the integrated circuit power consumption.
Description of drawings
Fig. 1 is the structural representation of full adder of the prior art.
Fig. 2 is the full adder structural representation of subthreshold value low-power consumption in one embodiment of the invention.
Fig. 3 is the structural representation of a CMOS reverser in one embodiment of the invention.
Fig. 4 is the structural representation of the 2nd CMOS reverser in one embodiment of the invention.
Fig. 5 is the structural representation of buffer in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Certainly the present invention is not limited to this specific embodiment, and the general replacement that those skilled in the art knew also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes sketch map to carry out detailed statement, and when instance of the present invention was detailed, for the ease of explanation, sketch map did not amplify according to general ratio is local, should be with this as to qualification of the present invention.
In the present embodiment, the following stated high level end connects external power source usually, the common ground connection of said low level end.
Fig. 2 is the structural representation of the full adder of subthreshold value low-power consumption in one embodiment of the invention.In conjunction with Fig. 2; The present invention provides a kind of full adder of subthreshold value low-power consumption; Have first input end A, the second input B, the 3rd input Ci, carry output Co and add and output S, the minimum operating voltage of full adder according to the invention is smaller or equal to 0.21V, and said full adder comprises: first order circuit 100, second level circuit 200 and buffer 300; Said first order circuit 100 output termination first node N1, said first order circuit 100 is used for the output carry coherent signal; The said first node N1 of the input termination of said buffer 300; The said Section Point N2 of the input termination of said second level circuit 200, said second level circuit 200 are used for output and add and coherent signal; The output termination Section Point N2 of said buffer 300, said Section Point N2 meets said carry output Co.
Further; Said first order circuit comprises first order pull-up unit PU1 and the drop-down unit PD1 of the first order; Said first order pull-up unit PU1 is connected between high level end and the said first node N1; The drop-down unit PD1 of the said first order is connected between low level end and the said first node N1, and said first order pull-up unit PU1 is used to export the carry signal of high level state, and the drop-down unit PD1 of the said first order is used for the carry signal of output low level state.
In the present embodiment, said first order pull-up unit PU1 comprises first to the 5th transistor, and said first to the 5th transistor is the PMOS pipe, wherein,
The source electrode of the first transistor M1 connects the high level end, and its grid meets first input end A;
The source electrode of transistor seconds M2 connects the drain electrode of said the first transistor M1, and the grid of said transistor seconds M2 meets the second input B;
The source electrode of the 3rd transistor M3 connects the drain electrode of said transistor seconds M2, and the drain electrode of said the 3rd transistor M3 meets said first node N1, and the said the 3rd transistorized grid meets first input end A;
The source electrode of the 4th transistor M4 connects the high level end, and its drain electrode connects the drain electrode of said the first transistor M1, and the grid of said the 4th transistor M4 meets the second input B;
The source electrode of the 5th transistor M5 connects the drain electrode of said the 4th transistor M4, and the drain electrode of said the 5th transistor M5 meets said first node N1, and the grid of said the 5th transistor M5 meets the 3rd input Ci.
In the present embodiment, the drop-down unit PD1 of the said first order comprises the 6th to the tenth transistor, and said the 6th to the tenth transistor is the NMOS pipe, wherein,
The drain electrode of the 6th transistor M6 meets first node N1, and its grid meets the 3rd input Ci;
The drain electrode of the 7th transistor M7 connects the source electrode of the 6th transistor M6, and the source electrode of said the 7th transistor M7 connects low level end, and the grid of said the 7th transistor M7 meets first input end A;
The drain electrode of the 8th transistor M8 connects the source electrode of the 6th transistor M6, and the source electrode of said the 8th transistor M8 connects low level end, and the grid of said the 8th transistor M8 meets the second input B;
The drain electrode of the 9th transistor M9 meets first node N1, and its grid meets first input end A;
The drain electrode of the tenth transistor M10 connects the source electrode of said the 9th transistor M3, and the source ground of said the tenth transistor M10, the grid of said the tenth transistor M10 meet the second input B.
Further; Said second level circuit comprises second level pull-up unit PU2 and the drop-down unit PD2 in the second level; Said first order pull-up unit PU2 is connected between high level end and said the 3rd node N3; The drop-down unit PD2 in the said second level is connected between low level end and said the 3rd node N3; Said second level pull-up unit PU2 is used to export adding and signal of high level state, and the drop-down unit PD2 in the said second level is used for adding of output low level state and signal, and said the 3rd node N3 connects said adding and output.
In the present embodiment, said second level pull-up unit PU2 comprises the 11 to the 17 transistor, and said the 11 to the 17 transistor is the PMOS pipe, wherein,
The source electrode of the 11 transistor M11 connects the high level end, and its grid meets the 3rd input Ci;
The source electrode of the tenth two-transistor M12 connects the drain electrode of said the 11 transistor M11, and the grid of said the tenth two-transistor M12 meets Section Point N2, and the drain electrode of said the tenth two-transistor M12 meets the 3rd node N3;
The source electrode of the 13 transistor M13 connects high level, and its grid meets first input end A, and the drain electrode of said the 13 transistor M13 connects the drain electrode of said the tenth two-transistor M12;
The source electrode of the 14 transistor M14 connects high level, and its grid meets the second input B, and its drain electrode connects the drain electrode of said the 13 transistor M13;
The source electrode of the 15 transistor M15 connects the drain electrode of said the 14 transistor M14, and the grid of said the 15 transistor M15 meets first input end A;
The source electrode of the 16 transistor M16 connects the drain electrode of said the 15 transistor M15, and the grid of the 16 transistor M16 meets the said second input B;
The source electrode of the 17 transistor M17 connects the drain electrode of said the 16 transistor M16, and the grid of the 17 transistor M17 meets said the 3rd input Ci, and the said the 17 transistorized M17 drain electrode meets said the 3rd node N3.
In an embodiment, the drop-down unit PD2 in the said second level comprises the 18 to the 24 transistor, and said the 18 to the 24 transistor is a nmos pass transistor, wherein,
The drain electrode of the 18 transistor M18 meets the 3rd node N3, and its grid meets Section Point N2;
The drain electrode of the 19 transistor M19 connects the source electrode of said the 18 transistor M18, and the grid of said the 19 transistor M19 meets first input end A, and the source electrode of said the 19 transistor M19 connects low level end;
The drain electrode of the 20 transistor M20 connects the said the 18 transistorized source electrode, and the grid of said the 20 transistor M20 meets the second input B, and the source electrode of said the 20 transistor M20 connects low level end;
The drain electrode of the 21 transistor M21 connects the source electrode of said the 18 transistor M18, and the grid of said the 21 transistor M21 connects the 3rd input, and the source electrode of said the 21 transistor M21 connects low level end;
The drain electrode of the 20 two-transistor M22 meets the 3rd node N3, and its grid meets the 3rd input Ci;
The drain electrode of the 23 transistor M23 connects the source electrode of said the 20 two-transistor M22, and the grid of said the 23 transistor M23 meets said first input end A;
The drain electrode of the 24 transistor M24 connects the source electrode of said the 23 transistor M23, and the grid of said the 24 transistor M24 meets the said second input B, and the drain electrode of said the 24 transistor M24 connects low level end.
Fig. 3 is the structural representation of a CMOS reverser in one embodiment of the invention.In conjunction with Fig. 2 and Fig. 3, further, said the 3rd node N3 links to each other with said adding with output through a CMOS reverser INV1; Said adding with coherent signal, add and output S output sum output signal from said after through a said CMOS reverser INV1; A said CMOS reverser INV1 comprises the 25 transistor M25 and the 26 transistor M26, and said the 25 transistor M25 is the PMOS transistor, and its source electrode connects the high level end; Its grid meets the 3rd node N3; Its drain electrode connects said adding and output S, and the 26 transistor M26 is a nmos pass transistor, and its drain electrode links to each other with the drain electrode of said the 25 transistor M25; The source electrode of said the 26 transistor M26 connects low level end, and the grid of said the 26 transistor M26 meets the 3rd node N3.
Fig. 4 is the structural representation of the 2nd CMOS reverser in one embodiment of the invention.In conjunction with Fig. 2 and Fig. 4, further, said Section Point N2 links to each other with said carry output Co2 through the 2nd CMOS reverser INV2; Said carry coherent signal through said the 2nd CMOS inverter INV2 after from said carry output Co output carry output signal; Said the 2nd CMOS reverser INV2 comprises the 27 transistor M27 and the 28 transistor M28, and said the 27 transistor M27 is the PMOS transistor, and its source electrode connects high level; Its grid meets Section Point N2; Its drain electrode meets said carry output Co, and the 28 transistor M28 is a nmos pass transistor, and its drain electrode links to each other with the drain electrode of said the 27 transistor M27; The source electrode of said the 28 transistor M28 connects low level end, and the grid of said the 28 transistor M28 meets Section Point N2.
Fig. 5 is the structural representation of buffer in one embodiment of the invention.In the present embodiment, said buffer is formed by the cascade of even number CMOS reverser, and in preferred embodiment, said buffer is formed by two CMOS reverser-Di, three CMOS reverser INV3 and the 4th CMOS reverser INV4 cascade successively.Further, said the 3rd CMOS reverser INV3 comprises the 29 transistor M29 and the 30 transistor M30, and said the 29 transistor M29 is the PMOS transistor; Its source electrode connects high level; Its grid meets first node N1, and the 30 transistor M30 is a nmos pass transistor, and its drain electrode links to each other with the drain electrode of said the 29 transistor M29; The source electrode of said the 30 transistor M30 connects low level end, and the grid of said the 30 transistor M30 meets first node N1; Said the 4th CMOS reverser INV4 comprises the 31 transistor M31 and the 30 two-transistor M32; Said the 31 transistor M31 is the PMOS transistor, and its source electrode connects high level, and its grid connects the drain electrode of said the 29 transistor M29; The 30 two-transistor M32 is a nmos pass transistor; Its drain electrode links to each other with the drain electrode of said the 31 transistor M31, and the source electrode of said the 30 two-transistor M32 connects low level end, and the grid of said the 30 two-transistor M32 meets Section Point N2.
Full adder according to the invention is used for operate as normal in all process corner reach-40 ℃～100 ℃.The circuit design of said full adder has been considered the influence that process corner and temperature deviation bring; Transistorized size is designed again; Circuit passes through the emulation of SPICE model under all process corner and harsh temperatures scope (40 ℃ to 100 ℃), to guarantee the accurate and stable of circuit function.
In preferred embodiment, each transistorized breadth length ratio is as shown in table 1.The breadth length ratio of the 18 transistor M18 is 3～5 in the prior art, and the breadth length ratio of the 18 transistor M18 according to the invention is 6～10.The M18 that increases can increase the pull-down capability of PD2 network, thereby can correct under the SF process corner with 100 ℃ the time, the output Sb of second level circuit is output as the failure conditions that does not reach low level logic swing when low.
Table 1
| MOSFET | M1 | M2 | M3 | M4 | M5 | M6 | M7 | M8 | M9 | M10 | M11 |
| W/L | 6～10 | 14～18 | 14～18 | 6～10 | 6～10 | 2～6 | 2～6 | 2～6 | 2～6 | 2～6 | 6～10 |
| MOSFET | M12 | M13 | M14 | M15 | M16 | M17 | M18 | M19 | M20 | M21 | M22 |
| W/L | 6～10 | 6～10 | 6～10 | 20～28 | 20～28 | 20～28 | 6～10 | 2～6 | 2～6 | 2～6 | 3～7 |
| MOSFET | M23 | M24 | M25 | M26 | M27 | M28 | M29 | M30 | M31 | M32 | |
| W/L | 3～7 | 3～7 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 | 8～12 | 1.5～2.5 |
In order to achieve the above object, the present invention has adopted technical scheme.
1) making each transistorized breadth length ratio of basic CMOS full adder according to the subthreshold value circuit design method, is 0.21V through the minimum operating voltage of this structure of test.Under the supply power voltage of 0.21V, this structure is carried out emulation, find out the phenomenon of its inefficacy (being the occurrence logic mistake).Always have two kinds of failure conditions.
2) first kind of failure conditions occurs in carry output Co, proposes to improve structure to this kind failure conditions.The buffer that between first order circuit and second level circuit, adds the inverter formation of two series connection.Before the improvement, the output Cob of first order circuit is output as low level the time, and this moment, the level of output Cob of first order circuit maintained 15.44mV.After adding the inverter (Buffer) of two series connection, the low level of the output Cob of first order circuit is 5.4mV under this kind condition, is greatly improved, and does not also destroy the level index under other conditions simultaneously.
3) second kind of failure conditions occurs in and adds and output S, proposes to improve structure to this kind failure conditions.With the transistorized adjusted size of second level M21 is original 2 times.Before the improvement, the output Sb of second level circuit is output as low level the time, and this moment, the level of output Sb of second level circuit maintained 22mV.After the transistorized size of M21 doubled, the low level of the output Sb of second level circuit was 16.4mV under this kind condition, was greatly improved, and did not also destroy the level index under other conditions simultaneously.
In sum, full adder is compared in the present invention and the prior art, and circuit of the present invention has following advantage:
Can under extremely low supply power voltage condition, carry out work, this design is applicable to the subthreshold value low.In the present invention, through the emulation of SPICE model, to guarantee the accurate and stable of circuit function.
The circuit working condition covers all process corner and harsh temperatures scope (40 ℃ to 100 ℃); This has just overcome the circuit characteristic deviation that process deviation brings in the manufacture process; Make circuit to be applicable to the node circuit of radio sensing network simultaneously in operate as normal under the varying environment.
The minimum operating voltage of this circuit can reach 0.21V.The reduction of minimum voltage can make the operating voltage in whole subthreshold value circuit unit storehouse reduce the reduction that brings the integrated circuit power consumption.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (19)
1. the full adder of a subthreshold value low-power consumption has first to the 3rd input, carry output and adds and output, it is characterized in that, the minimum operating voltage of said full adder is smaller or equal to 0.21V, and said full adder comprises,
First order circuit, its output termination first node, said first order circuit is used for the output carry coherent signal;
Buffer, the said first node of its input termination, its output termination Section Point, said Section Point connects said carry output;
Second level circuit, the said Section Point of its input termination, said second level circuit is used for output and adds and coherent signal.
2. the full adder of subthreshold value low-power consumption as claimed in claim 1; It is characterized in that; Said first order circuit comprises first order pull-up unit and the drop-down unit of the first order, and said first order pull-up unit is connected between high level end and the said first node, and the drop-down unit of the said first order is connected between low level end and the said first node; Said first order pull-up unit is used to export the carry signal of high level state, and the drop-down unit of the said first order is used for the carry signal of output low level state.
3. the full adder of subthreshold value low-power consumption as claimed in claim 2 is characterized in that, said first order pull-up unit comprises first to the 5th transistor, wherein,
The source electrode of the first transistor connects the high level end, and its grid connects first input end;
The source electrode of transistor seconds connects the drain electrode of said the first transistor, and the grid of said transistor seconds connects second input;
The 3rd transistorized source electrode connects the drain electrode of said transistor seconds, and said the 3rd transistor drain connects said first node, and the said the 3rd transistorized grid connects first input end;
The 4th transistorized source electrode connects the high level end, and its drain electrode connects the drain electrode of said the first transistor, and the said the 4th transistorized grid connects second input;
The 5th transistorized source electrode connects said the 4th transistor drain, and said the 5th transistor drain connects said first node, and the said the 5th transistorized grid connects the 3rd input.
4. the full adder of subthreshold value low-power consumption as claimed in claim 3; It is characterized in that; The breadth length ratio of said the first transistor is 6～10, and said transistor seconds and the 3rd transistorized breadth length ratio are 14～18, and said the 4th transistor and the 5th transistorized breadth length ratio are 6～10.
5. the full adder of subthreshold value low-power consumption as claimed in claim 3 is characterized in that, said first to the 5th transistor is the PMOS pipe.
6. the full adder of subthreshold value low-power consumption as claimed in claim 2 is characterized in that, the drop-down unit of the said first order comprises the 6th to the tenth transistor, wherein,
The 6th transistor drain connects first node, and its grid connects the 3rd input;
The 7th transistor drain connects the 6th transistorized source electrode, and the said the 7th transistorized source electrode connects low level end, and the said the 7th transistorized grid connects first input end;
The 8th transistor drain connects the 6th transistorized source electrode, and the said the 8th transistorized source electrode connects low level end, and the said the 8th transistorized grid connects second input;
The 9th transistor drain connects first node, and its grid connects first input end;
The tenth transistor drain connects the said the 9th transistorized source electrode, the said the tenth transistorized source ground, and the said the tenth transistorized grid connects second input.
7. the full adder of subthreshold value low-power consumption as claimed in claim 6 is characterized in that, said the 6th transistor to the ten transistorized breadth length ratios are 2～6.
8. the full adder of subthreshold value low-power consumption as claimed in claim 6 is characterized in that, said the 6th to the tenth transistor is the NMOS pipe.
9. the full adder of subthreshold value low-power consumption as claimed in claim 1; It is characterized in that; Said second level circuit comprises the drop-down unit of the second level pull-up unit and the second level; Said first order pull-up unit is connected between high level end and said the 3rd node, and drop-down unit, the said second level is connected between low level end and said the 3rd node, and said second level pull-up unit is used to export adding and signal of high level state; Drop-down unit, the said second level is used for adding of output low level state and signal, and said the 3rd node connects said adding and output.
10. the full adder of subthreshold value low-power consumption as claimed in claim 9 is characterized in that, said second level pull-up unit comprises the 11 to the 17 transistor, wherein,
The 11 transistorized source electrode connects the high level end, and its grid connects the 3rd input;
The source electrode of the tenth two-transistor connects said the 11 transistor drain, and the grid of said the tenth two-transistor connects Section Point, and the drain electrode of said the tenth two-transistor connects the 3rd node;
The 13 transistorized source electrode connects high level, and its grid connects first input end, and said the 13 transistor drain connects the drain electrode of said the tenth two-transistor;
The 14 transistorized source electrode connects high level, and its grid connects second input, and its drain electrode connects said the 13 transistor drain;
The 15 transistorized source electrode connects said the 14 transistor drain, and the said the 15 transistorized grid connects first input end;
The 16 transistorized source electrode connects said the 15 transistor drain, and the 16 transistorized grid connects said second input;
The 17 transistorized source electrode connects said the 16 transistor drain, and the 17 transistorized grid connects said the 3rd input, and said the 17 transistor drain connects said the 3rd node.
11. the full adder of subthreshold value low-power consumption as claimed in claim 10 is characterized in that, said the 11 transistor to the 14 transistorized breadth length ratios are 6～10, and said the 15 transistor to the 17 transistorized breadth length ratios are 20～28.
12. the full adder of subthreshold value low-power consumption as claimed in claim 10 is characterized in that, said the 11 to the 17 transistor is the PMOS pipe.
13. the full adder of subthreshold value low-power consumption as claimed in claim 9 is characterized in that, drop-down unit, the said second level comprises the 18 to the 24 transistor, wherein,
The 18 transistor drain connects the 3rd node, and its grid connects Section Point;
The 19 transistor drain connects the said the 18 transistorized source electrode, and the said the 19 transistorized grid connects first input end, and the said the 19 transistorized source electrode connects low level end;
The 20 transistor drain connects the said the 18 transistorized source electrode, and the said the 20 transistorized grid connects second input, and the said the 20 transistorized source electrode connects low level end;
The 21 transistor drain connects the said the 18 transistorized source electrode, and the said the 21 transistorized grid connects the 3rd input, and the said the 21 transistorized source electrode connects low level end;
The drain electrode of the 20 two-transistor connects the 3rd node, and its grid connects the 3rd input;
The 23 transistor drain connects the source electrode of said the 20 two-transistor, and the said the 23 transistorized grid connects said first input end;
The 24 transistor drain connects the said the 23 transistorized source electrode, and the said the 24 transistorized grid connects said second input, and said the 24 transistor drain connects low level end.
14. the full adder of subthreshold value low-power consumption as claimed in claim 13; It is characterized in that; The said the 18 transistorized breadth length ratio is 6～10; Said the 19 transistor to the 21 transistorized breadth length ratios are 2～6, and said the 20 two-transistor to the 24 transistorized breadth length ratios are 3～7.
15. the full adder of subthreshold value low-power consumption as claimed in claim 13 is characterized in that, said the 18 to the 24 transistor is a nmos pass transistor.
16. the full adder of subthreshold value low-power consumption as claimed in claim 9; It is characterized in that; Said the 3rd node links to each other with said adding with output through a CMOS reverser, and said adding with coherent signal adds and output output sum output signal from said after through a said CMOS reverser.
17. full adder like any described subthreshold value low-power consumption in the claim 1 to 16; It is characterized in that; Said Section Point links to each other with said carry output through the 2nd CMOS reverser, and said carry coherent signal is exported signal from said carry output output carry after through said the 2nd CMOS inverter.
18. the full adder like any described subthreshold value low-power consumption in the claim 1 to 16 is characterized in that, said buffer is formed by the cascade of even number CMOS reverser.
19. the full adder like any described subthreshold value low-power consumption in the claim 1 to 16 is characterized in that, said full adder is used for operate as normal in all process corner reach-40 ℃～80 ℃.
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