CN102169463A - Inter-integrated circuit (IIC) bus-based manufacturing information acquisition method and equipment - Google Patents
Inter-integrated circuit (IIC) bus-based manufacturing information acquisition method and equipment Download PDFInfo
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- CN102169463A CN102169463A CN2011101083563A CN201110108356A CN102169463A CN 102169463 A CN102169463 A CN 102169463A CN 2011101083563 A CN2011101083563 A CN 2011101083563A CN 201110108356 A CN201110108356 A CN 201110108356A CN 102169463 A CN102169463 A CN 102169463A
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Abstract
The invention discloses an inter-integrated circuit (IIC) bus-based manufacturing information acquisition method and equipment. The method comprises the following steps: when the IIC control equipment detects that an electrically erasable programmable read-only memory (EEPROM) connected with an IIC bus is on site by using the IIC bus, the IIC control equipment acquires an IIC equipment address of the EEPROM and the length of manufacturer manufacturing information; and the IIC control equipment acquires the manufacturer manufacturing information stored in the EEPROM through the IIC equipment address of the EEPROM, the read operation starting address and the length of the manufacturer manufacturing information. In the method and the equipment disclosed by the invention, the starting time of data communication equipment is shortened.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of acquisition methods and equipment of the manufacturing information based on iic bus.
Background technology
IIC (Inter-Integrated Circuit, two-wire serial bus are called I2C again) bus is the twin wire universal serial bus, is used to connect CPU (Central Processing Unit, central processing unit) and peripherals thereof.Iic bus only needs two lines, and the space of having reduced circuit board has reduced the quantity of chip pin, and iic bus supports many master controls (multimastering), and wherein any equipment that can send and receive all can become main bus; Master control can control signal transmission and clock frequency, and a master control can only be arranged at any time.
Concrete, iic bus comprises a SDA (serial data, serial data), a SCL (serial clock, serial clock) can transmit and receive data, and has the connection characteristic of simple, is used widely in the design of electronic equipment internal chip interconnect.Iic bus is between CPU and the controlled IIC equipment, carry out two-way transmission between IIC equipment and the IIC equipment; CPU and IIC equipment are connected in parallel on the iic bus, and each IIC equipment has unique address (IIC device address), and the IIC equipment on same iic bus is independently of one another.
Iic bus data transmission synoptic diagram as shown in Figure 1, when iic bus transmitted data, can be with the next stage: (1) incipient stage (START), when SCL was high level, SDA to low transition, began to transmit data by high level.(2) the transmission objectives IIC device address stage (Calling Address), transmit target IIC device address and read-write sign.(3) acknowledgment phase (ACK), receive target IIC device address after, send specific low level pulse to the CPU that sends data, data have been received in expression; If CPU does not receive answer signal, then be judged as target IIC equipment and do not exist or fault.(4) data phase (Data) if CPU writes IIC equipment, after then CPU receives ACK, sends data; If CPU reads IIC equipment, after then IIC equipment was sent and replied, IIC equipment sent data.(5) ending phase (STOP), when SCL was low level, SDA to the high level saltus step, finished to transmit data by low level.
In the prior art, data communications equipment is the main application fields of iic bus, CPU connects various EEPROM (Electrically Erasable Programmable Read-Only Memory by iic bus, electricallyerasable ROM (EEROM)), RTC (real-time clock real-time clock), temperature sensor equipment such as (can contain fan governor), EEPROM is the most general IIC equipment that uses in the data communications equipment.
Centralized data communications equipment IIC as shown in Figure 2 uses synoptic diagram, CPU connects each EEPROM by iic bus, data communication facilities can have 10 several EEPROM (respectively at master control borad, fixed service interface, can plug on the modules such as interface module), and each EEPROM has stored manufacturer's manufacturing information (as master control borad EEPROM stored manufacturer's manufacturing information of master control borad) of place module.
As shown in Figure 2, all EEPROM all are articulated on the iic bus with CPU in the current design, the visit of all EEPROM all needs CPU and participates in, all initial work are all finished by the CPU of operational system startup software, the CPU operational system starts software, various hardware and software resources of initialization successively, wherein manufacturer's manufacturing information (must read manufacturer's manufacturing information during the system software initialization) of EEPROM is read in initialization, whether CPU is at first on the throne by the EEPROM of the signal detection module that is associated with module, if on the throne, CPU need read corresponding manufacturer manufacturing information by iic bus from the EEPROM of different IIC interfaces; Under the situation that a plurality of modules are arranged, can carry out aforesaid operations successively.
But, because the visit of EEPROM needs CPU and participates in, iic bus is a bus (frequency is the 10-100kHz magnitude) at a slow speed, then CPU reads the data volume of manufacturer's manufacturing information about 10-100kByte, therefore can cause CPU to read manufacturer's manufacturing information 10s of surpassing consuming time, CPU participates in the read operation of manufacturer's manufacturing information of EEPROM for a long time, influences the toggle speed of data communications equipment.
Summary of the invention
The invention provides a kind of acquisition methods and equipment of the manufacturing information based on iic bus, to improve the toggle speed of data communications equipment.
In order to achieve the above object, the invention provides a kind of acquisition methods of the manufacturing information based on the two-wire serial bus iic bus, one side of iic bus is connected with the uncertain electricallyerasable ROM (EEROM) EEPROM of quantity, opposite side is connected with the IIC opertaing device, store manufacturer's manufacturing information of place module among the described EEPROM, this method may further comprise the steps: detect EEPROM that iic bus connects when on the throne when described IIC opertaing device uses iic bus, described IIC opertaing device obtains the IIC device address of described EEPROM and the length of manufacturer's manufacturing information; Described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM by the length of IIC device address, read operation start address and the manufacturer's manufacturing information of described EEPROM; The process that described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM is independent of system start-up software, and carries out with the system start-up software parallel.
Described IIC opertaing device uses iic bus to detect the EEPROM process on the throne that iic bus connects, be specially: described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address to assigned I IC device address, if assigned I IC device address has ACK to reply, it is on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects.
Described assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF; Described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address to assigned I IC device address, specifically comprises: described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF to assigned I IC device address.
Described IIC opertaing device obtains the process of the IIC device address of described EEPROM, be specially: when the EEPROM of the iic bus connection that detects assigned I IC device address was on the throne, the IIC device address that described IIC opertaing device obtains described EEPROM was described assigned I IC device address.
Described IIC opertaing device obtains the process of length of manufacturer's manufacturing information of described EEPROM, when the EEPROM of the iic bus connection that detects assigned I IC device address was on the throne, described IIC opertaing device obtained the length of manufacturer's manufacturing information of described EEPROM by the operation of reading default byte.
Described default byte comprises 2 bytes, and these 2 bytes are byte 0 and byte 1, if read designated identification from byte 0, then obtains the length of manufacturer's manufacturing information of described EEPROM by byte 1; Otherwise, obtain the length of manufacturer's manufacturing information of described EEPROM by byte 0.
Described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM by the length of IIC device address, read operation start address and the manufacturer's manufacturing information of described EEPROM, also comprises afterwards: described IIC opertaing device stores described manufacturer manufacturing information in internal random access memory RAM or the Installed System Memory into; To be used for when CPU need be known described manufacturer manufacturing information, in described internal RAM or Installed System Memory, reading described manufacturer manufacturing information.
Described IIC opertaing device is integrated in complex programmable logic device (CPLD) or the on-site programmable gate array FPGA, and described IIC opertaing device is independent of the CPU that operational system starts software; Perhaps, described IIC opertaing device is integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and this nuclear is independent of the nuclear of operational system startup software in the multi-core CPU.
The invention provides a kind of two-wire serial bus IIC opertaing device, one side of iic bus is connected with the uncertain electricallyerasable ROM (EEROM) EEPROM of quantity, opposite side is connected with described IIC opertaing device, store manufacturer's manufacturing information of place module among the described EEPROM, this equipment comprises: EEPROM in-place detection submodule is used to use iic bus to detect the situation on the throne of the EEPROM of iic bus connection; The core controlling sub, be used for when the EEPROM that detects the iic bus connection is on the throne, obtain the IIC device address of described EEPROM and the length of manufacturer's manufacturing information, and the length of IIC device address, read operation start address and manufacturer's manufacturing information by described EEPROM is obtained manufacturer's manufacturing information of storing among the described EEPROM; The process of obtaining manufacturer's manufacturing information of storing among the described EEPROM is independent of system start-up software, and carries out with the system start-up software parallel.
Described EEPROM in-place detection submodule, specifically be used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address, if assigned I IC device address has ACK to reply, it is on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects.
Described assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF; Described EEPROM in-place detection submodule is further used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF.
Described core controlling sub specifically is used for when the EEPROM of the iic bus connection that detects assigned I IC device address is on the throne, and the IIC device address that obtains described EEPROM is described assigned I IC device address.
Described core controlling sub specifically is used for obtaining the length of manufacturer's manufacturing information of described EEPROM by the operation of reading default byte when the EEPROM of the iic bus connection that detects assigned I IC device address is on the throne.
Described default byte comprises 2 bytes, and these 2 bytes are byte 0 and byte 1, if read designated identification from byte 0, then obtains the length of manufacturer's manufacturing information of described EEPROM by byte 1; Otherwise, obtain the length of manufacturer's manufacturing information of described EEPROM by byte 0.
This IIC opertaing device also comprises: internal RAM and Installed System Memory visit submodule; Described core controlling sub also is used for described manufacturer manufacturing information is stored into internal RAM or stores described manufacturer manufacturing information into Installed System Memory by Installed System Memory visit submodule; Described internal RAM is used to preserve manufacturer's manufacturing information, to be used for reading described manufacturer manufacturing information in described internal RAM when CPU need be known described manufacturer manufacturing information; Described Installed System Memory visit submodule is used for storing described manufacturer manufacturing information into Installed System Memory, to be used for reading described manufacturer manufacturing information in described Installed System Memory when CPU need be known described manufacturer manufacturing information.
Described IIC opertaing device is integrated in complex programmable logic device (CPLD) or the on-site programmable gate array FPGA, and described IIC opertaing device is independent of the CPU that operational system starts software; Perhaps, described IIC opertaing device is integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and this nuclear is independent of the nuclear of operational system startup software in the multi-core CPU.
Compared with prior art, the present invention has the following advantages at least: whether can being independent of system start-up software, to learn on the iic bus each EEPROM automatically on the throne, and the length of the IIC device address of EEPROM and manufacturer's manufacturing information, thereby can read manufacturer's manufacturing information automatically; The CPU operational system starts software no longer directly from reading manufacturing information the EEPROM at a slow speed, but reads manufacturer's manufacturing information from internal RAM at a high speed or Installed System Memory, shortens data communications equipment start-up time.
Description of drawings
Fig. 1 is an iic bus data transmission synoptic diagram in the prior art;
Fig. 2 is that centralized data communications equipment IIC uses synoptic diagram in the prior art;
Fig. 3 is that the IIC opertaing device is integrated in synoptic diagram on logic chip or the FPGA among the present invention;
Fig. 4 is that the IIC opertaing device is integrated in synoptic diagram on the nuclear of multi-core CPU among the present invention;
Fig. 5 is the process flow figure of a kind of manufacturing information based on iic bus provided by the invention;
Fig. 6 is that synoptic diagram is formed in the IIC device address of EEPROM in the prior art;
Fig. 7 is the synoptic diagram that byte 0 is used to preserve effective manufacturer manufacturing information length in the prior art;
Fig. 8 is the synoptic diagram that byte 1 is used to preserve the EEPROM total volume in the prior art;
Fig. 9 is a kind of IIC opertaing device structural representation provided by the invention.
Embodiment
The invention provides a kind of acquisition methods of the manufacturing information based on iic bus, cause the slow problem of data communications equipment toggle speed at the manufacturer's manufacturing information that reads EEPROM, by automatic loading manufacturer manufacturing information, make obtaining of manufacturer's manufacturing information be independent of cpu system software, improve the toggle speed of data communications equipment.
Among the present invention, at data communications equipment, one side of iic bus is connected with the uncertain EEPROM of quantity, and (this EEPROM is an IIC equipment, and iic bus connects 8 EEPROM at most, but whether each EEPROM is on the throne uncertain, therefore EEPROM quantity is uncertain), opposite side is connected with the IIC opertaing device.This IIC opertaing device can be integrated in CPLD (Complex Programmable Logic Device, CPLD) or FPGA (Field-Programmable Gate Array, field programmable gate array) in, and is independent of the CPU that operational system starts software; Also can be integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and this nuclear is independent of the nuclear of operational system startup software in the multi-core CPU.IIC opertaing device as shown in Figure 3 is integrated in the synoptic diagram in the synoptic diagram of CPLD or FPGA and the nuclear that IIC opertaing device shown in Figure 4 is integrated in inoperative system start-up software in the multi-core CPU.
It should be noted that, need to change existing iic bus connected mode among the present invention, when the IIC opertaing device is integrated in CPLD or FPGA, iic bus one side is connected on the EEPROM of IIC equipment, opposite side is connected on the CPLD or FPGA that is integrated with the IIC opertaing device.When the IIC opertaing device is integrated in nuclear of inoperative system start-up software in the multi-core CPU, iic bus one side is connected on the EEPROM of IIC equipment, opposite side is connected on the nuclear of the inoperative system start-up software that is integrated with the IIC opertaing device.
Among the present invention, store manufacturer's manufacturing information of place module among this EEPROM, this manufacturer's manufacturing information includes but not limited to: trade name, sequence number, the date of production, coded message, information of check code etc.With Fig. 3 and scene shown in Figure 4 is example, the EEPROM of module includes but not limited to: memory bar EEPROM, master control borad EEPROM, optical module EEPROM and interface card EEPROM, it is manufacturer's manufacturing information of having stored memory bar among the memory bar EEPROM, stored manufacturer's manufacturing information of master control borad among the master control borad EEPROM, optical module EEPROM has stored manufacturer's manufacturing information of optical module, has stored manufacturer's manufacturing information of interface card among the interface card EEPROM.
As shown in Figure 5, this acquisition methods based on the manufacturing information of iic bus may further comprise the steps:
Whether the EEPROM that step 501, IIC opertaing device use iic bus (promptly not needing by other signals) detection iic bus to connect is on the throne, if, execution in step 502, otherwise, continue execution in step 501, until detecting, finish all EEPROM that iic bus connects.In the practical application, an iic bus can connect 8 EEPROM, when needs connect more EEPROM, can realize that the processing procedure of every iic bus is identical by many iic bus, and connecting 8 EEPROM at most with an iic bus is that example describes.
Concrete, the IIC device address of considering IIC interface EEPROM is positioned at fixing position, by basic constraint condition in conjunction with the IIC transferring ACK, the IIC opertaing device can (this read operation start address be an agreed address from the read operation start address to the execution of assigned I IC device address, as to arrange the read operation start address be 0 address) operation that begins to read default byte (as 2Bytes), if assigned I IC device address has ACK to reply, it is on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects.
It should be noted that, this assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF, and promptly the IIC opertaing device can be carried out the operation that begins to read default byte from the read operation start address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF to assigned I IC device address; As long as carry out the operation that begins to read default byte from the read operation start address to above-mentioned 8 IIC device addresses, execution sequence can be selected according to actual needs in the practical application.For carrying out the example that is operating as that begins to read default byte from the read operation start address to the IIC device address of 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF successively, then this step comprises with predefined procedure:
The IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address to the IIC device address of 0xA1, if there is not ACK to reply, the EEPROM that the iic bus of assigned I IC device address 0xA1 connects is not on the throne, carries out the operation that begins to read default byte from the read operation start address to the IIC device address of 0xA3; If there is ACK to reply, the EEPROM that the iic bus of assigned I IC device address 0xA1 connects is on the throne, carry out subsequent step 502-505, after subsequent step 502-505 is complete, carry out the operation that begins to read default byte from the read operation start address to the IIC device address of 0xA3; By that analogy, until the operation of the IIC device address of 0xAF is complete, repeat no more among the present invention.
To it should be noted that manufacturer's manufacturing information of storing among the EEPROM in order reading, to need to obtain IIC device address, the length of manufacturer's manufacturing information, the read operation start address of EEPROM.The read operation start address is agreed address (is 0 address as agreement read operation start address); The hardware design of data communications equipment is depended in the IIC device address of EEPROM, can't unify agreement; The length of manufacturer's manufacturing information also depends on the application (manufacturer's manufacturing information of each IIC equipment can be inequality) of concrete IIC equipment, can't unify agreement; Therefore the IIC opertaing device need obtain the IIC device address of EEPROM and the length of manufacturer's manufacturing information.
The composition synoptic diagram of the IIC device address of EEPROM as shown in Figure 6, the 0b1010 of high 4bit are the unified signs of IIC interface EEPROM; (value is 0-7 to the chip selection signal that middle 3bit stipulates when being hardware design, promptly on an iic bus 8 EEPROM can only be arranged at most, many iic bus of needs when connecting more EEPROM), during the design of hardware line, need distribute different chip selection signals for the EEPROM of different IIC interfaces, last 1bit is read-write sign (is read operation when being 1, be 0 o'clock be write operation).When chip selection signal was set to 000, then the IIC device address of EEPROM was 0xA1, and when chip selection signal was set to 001, then the IIC device address of EEPROM was 0xA3, by that analogy.
In order to obtain the IIC device address of EEPROM, when the EEPROM that connects when the iic bus that detects assigned I IC device address was on the throne, then to obtain the IIC device address be assigned I IC device address to the IIC opertaing device.For example, when the EEPROM that connects when the iic bus of assigned I IC device address 0xA1 was on the throne, then the IIC device address was 0xA1.
In order to obtain the length of manufacturer's manufacturing information, when the EEPROM of the iic bus connection that detects assigned I IC device address was on the throne, then the IIC opertaing device obtained the length of manufacturer's manufacturing information of EEPROM by the operation of reading default byte; Default byte comprises 2 bytes, and these 2 bytes are byte 0 and byte 1, if read designated identification (as identifying 0) from byte 0, then obtains the length of manufacturer's manufacturing information of EEPROM by byte 1; Otherwise, obtain the length of manufacturer's manufacturing information of EEPROM by byte 0.
Concrete, can expand existing SPD (Serial Presence Detect, the serial of the existence detects) method of standard among the present invention and obtain the length of manufacturer's manufacturing information.Existing DDR (Double Data Rate, Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) SPD is a kind of EEPROM of IIC interface, is used to deposit manufacturer's proposed arrangement information of DDRSDRAM, and is as shown in table 1.For byte 0, be used to preserve the length of manufacturer's manufacturing information of EEPROM, the synoptic diagram of the length of manufacturer's manufacturing information of preservation EEPROM as shown in Figure 7; For byte 1, be used to preserve the EEPROM total volume, the synoptic diagram of preservation EEPROM total volume as shown in Figure 8.
Table 1
| Byte?0 | The length of manufacturer's manufacturing information of EEPROM |
| Byte?1 | The EEPROM total volume |
As can be seen from Figures 7 and 8, the length of existing manufacturer manufacturing information mostly is 256Bytes most, for DDR SDRAM, manufacturing information length 256Bytes is enough in manufacturer, but for the IIC interface EEPROM of other application, the manufacturing information length 256Bytes of manufacturer also is nowhere near, therefore expanded the definition of SPD standard among the present invention, for the EEPROM of non-DDR SDRAM SPD, Byte 0 deposits 0, and the length of manufacturer's manufacturing information that is used to identify EEPROM is by Byte 1 decision; Byte1 is used to preserve the length of manufacturer's manufacturing information of EEPROM, and is as shown in table 2.
Table 2
| Byte?0 | 0 (length of manufacturer's manufacturing information of sign EEPROM is by Byte 1 decision) |
| Byte?1 | The length of manufacturer's manufacturing information of EEPROM |
In sum, among the present invention, the data (by reading the data of 2 bytes) that the IIC opertaing device is read when on the throne by the EEPROM that detects the IIC interface can obtain the length of manufacturer's manufacturing information of EEPROM.This expanded definition compatibility DDR SDRAM and non-DDR SDRAM, the length of manufacturer's manufacturing information of the byte 0 statement EEPROM of DDR SDRAM, the length of manufacturer's manufacturing information of the byte 1 statement EEPROM of non-DDR SDRAM can obtain the length based on manufacturer's manufacturing information of DDR SDRAM and non-DDR SDRAM when therefore reading the data of 2 bytes.
For example, when the EEPROM of the iic bus connection that detects 0xA1 is on the throne, begin, obtain manufacturer's manufacturing information of storing among the EEPROM by the length of manufacturer's manufacturing information, thereby obtain manufacturer's manufacturing information of 0xA correspondence with the read operation start address.
Step 505 in the data communications equipment start-up course, is obtained manufacturer's manufacturing information if desired, then directly obtains in RAM or the Installed System Memory internally.
Among the present invention, the IIC opertaing device can be saved in manufacturer's manufacturing information in the internal RAM (CPLD, FPGA or multi-core CPU generally are integrated in internal RAM), directly obtains manufacturer's manufacturing information among the RAM internally whenever necessary for cpu system software.For internal RAM, because BIOS (Basic Input Output System, Basic Input or Output System (BIOS)) need obtain SPD information ability initialization system internal memory earlier, then internal RAM is applicable to the SPD information of obtaining DDR SDRAM in advance.
In addition, manufacturer's manufacturing information of different I IC equipment can be kept at address different in the internal RAM (these addresses are what to be made an appointment), when preserving manufacturer's manufacturing information, can preserve the first address of manufacturer's manufacturing information, and deposit and obtain complement mark, in the acquiescence internal RAM all to obtain complement mark all be not finish, after manufacturer's manufacturing information is write internal RAM, revise and obtain complement mark for finishing.
Among the present invention, consider that the internal RAM space is limited, at bigger manufacturer's manufacturing information, the IIC opertaing device can be saved in manufacturer's manufacturing information in the Installed System Memory.Manufacturer's manufacturing information of different I IC equipment can be kept at address different in the Installed System Memory (these addresses are what to be made an appointment), when preserving manufacturer's manufacturing information, can preserve the first address of manufacturer's manufacturing information, and deposit and obtain complement mark, in the default system internal memory all to obtain complement mark all be not finish, after with manufacturer's manufacturing information writing system internal memory, revise and obtain complement mark for finishing.
In sum, among the present invention, after the data communications equipment system software starts, start software in the CPU operational system, during other various hardware and software resource of initialization, whether can being independent of system start-up software, to learn on the iic bus each EEPROM automatically on the throne, and the length of the IIC device address of EEPROM and manufacturer's manufacturing information, thereby can read manufacturer's manufacturing information automatically, be saved in internal RAM or the Installed System Memory, and above-mentioned acquisition process is independent of cpu system software, with the CPU parallel starting of operational system startup software; When cpu system software needs manufacturer's manufacturing information, the CPU operational system starts software no longer directly from reading manufacturing information the EEPROM at a slow speed, but from internal RAM at a high speed or Installed System Memory, read manufacturer's manufacturing information, adopt the operation of work in series parallelization like this, shorten data communications equipment start-up time.
Further, the CPU operational system starts software and read manufacturer's manufacturing information from internal RAM at a high speed or Installed System Memory, with from EEPROM at a slow speed, read manufacturing information and compare, significantly improve the access speed (bringing up to more than the 1Gbps) of cpu system software by 100kbps; Shorten data communications equipment start-up time (having shortened between 5% to 40%); Strengthen the stability of data communications equipment forwarding performance; Applied widely, use the electronic equipment of iic bus all can use technical scheme provided by the invention; Need not CPU and participate in, realizability is strong, and logical design is simple; The user experiences, and need not the user and understands data communications equipment design realization, need not special points for attention.
Based on the inventive concept same with said method, the present invention also provides a kind of IIC opertaing device, one side of iic bus is connected with the uncertain EEPROM of quantity, opposite side is connected with the IIC opertaing device, store manufacturer's manufacturing information of place module among the EEPROM, the IIC opertaing device is integrated among CPLD or the FPGA, and is independent of the CPU that operational system starts software; Or, the IIC opertaing device is integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and be independent of the nuclear of operational system startup software in the multi-core CPU, as shown in Figure 9, this equipment comprises EEPROM in-place detection submodule 11, core controlling sub 12, internal RAM 13, Installed System Memory visit submodule 14 and IIC access interface submodule 15.
This IIC access interface submodule 15 is used to realize the visit to EEPROM, and the EEPROM that EEPROM in-place detection submodule 11 and core controlling sub 12 can be called 15 pairs of IIC interfaces of IIC access interface submodule carries out read operation; In the access process to EEPROM, the length of IIC device address and manufacturer's manufacturing information is issued by EEPROM in-place detection submodule 11 and core controlling sub 12, and the read operation start address of accessed EEPROM is fixed as the 0th byte that is begun by the IIC device address.
EEPROM in-place detection submodule 11 is used to use iic bus to detect the situation on the throne of the EEPROM of iic bus connection; EEPROM in-place detection submodule 11, specifically be used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address, if assigned I IC device address has ACK to reply, it is on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects.
Assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF; EEPROM in-place detection submodule 11 is further used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF.
Concrete, after the IIC opertaing device powers on, EEPROM in-place detection submodule 11 issues and (can be set to 000 by DDR SDRAM SPD chip selection signal in the design of hardware line to IIC device address 0xA1, the IIC device address is 0xA1, gives BIOS initialization DDR internal memory with the information that reads SPD at first) the EEPROM action of reading two bytes give IIC access interface submodule 15; And after the EEPROM that detects the 0xA1 correspondence returns ACK, know that EEPROM is on the throne, two bytes (byte 0 and byte 1) that get access to are reported core controlling sub 12, parse the length of manufacturer's manufacturing information by core controlling sub 12 after, EEPROM at the IIC device address issues the operation of the length of reading manufacturer's manufacturing information to IIC access interface submodule 15, after IIC access interface submodule 15 is finished the IIC read operation, the data of obtaining (being manufacturer's manufacturing information) are reported core controlling sub 12.After manufacturer's manufacturing information of finishing this EEPROM obtained, core controlling sub 12 triggered EEPROM in-place detection submodule 11 and detects next IIC device address 0xA3, and the like, finish 0xAF up to detection.
Further, if many iic bus are arranged, EEPROM in-place detection submodule 11 also needs to search for successively according to every iic bus.In addition, EEPROM in-place detection submodule 11 detects 0xA1 and does not reply ACK, illustrates that then the EEPROM of the IIC interface of 0xA1 address correspondence does not exist, and this EEPROM in-place detection submodule 11 detects 0xA3 automatically, and the like.
Among the present invention, core controlling sub 12 also is used for manufacturer's manufacturing information is stored into internal RAM 13 or stores manufacturer's manufacturing information into Installed System Memory by Installed System Memory visit submodule 14, at this moment:
Installed System Memory visit submodule 14 is used for storing manufacturer's manufacturing information into Installed System Memory, to be used for reading manufacturer's manufacturing information in Installed System Memory when CPU need be known manufacturer's manufacturing information.Because internal RAM 13 spaces are limited, if bigger manufacturer's manufacturing information is arranged, then need to be saved in the Installed System Memory; Core controlling sub 12 is to realize the manufacturer's manufacturing information that obtains is saved in the Installed System Memory by Installed System Memory visit submodule 14.Manufacturer's manufacturing information of different I IC equipment can be kept at addresses different in the Installed System Memory, when preserving manufacturer's manufacturing information, can preserve the first address of manufacturer's manufacturing information, and deposit and obtain complement mark, in the default system internal memory all to obtain complement mark all be not finish, after with manufacturer's manufacturing information writing system internal memory, revise and obtain complement mark for finishing.
Each module of apparatus of the present invention can be integrated in one, and also can separate deployment.Above-mentioned module can be merged into a module, also can further split into a plurality of submodules.
Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, technical scheme of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is the synoptic diagram of a preferred embodiment, module in the accompanying drawing or flow process might not be that enforcement the present invention is necessary.
It will be appreciated by those skilled in the art that the module in the device among the embodiment can be distributed in the device of embodiment according to the embodiment description, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of the foregoing description can be merged into a module, also can further split into a plurality of submodules.
The invention described above sequence number is not represented the quality of embodiment just to description.
More than disclosed only be several specific embodiment of the present invention, still, the present invention is not limited thereto, any those skilled in the art can think variation all should fall into protection scope of the present invention.
Claims (16)
1. acquisition methods based on the manufacturing information of two-wire serial bus iic bus, one side of iic bus is connected with the uncertain electricallyerasable ROM (EEROM) EEPROM of quantity, opposite side is connected with the IIC opertaing device, store manufacturer's manufacturing information of place module among the described EEPROM, it is characterized in that this method may further comprise the steps:
Detect EEPROM that iic bus connects when on the throne when described IIC opertaing device uses iic bus, described IIC opertaing device obtains the IIC device address of described EEPROM and the length of manufacturer's manufacturing information;
Described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM by the length of IIC device address, read operation start address and the manufacturer's manufacturing information of described EEPROM;
The process that described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM is independent of system start-up software, and carries out with the system start-up software parallel.
2. the method for claim 1 is characterized in that, described IIC opertaing device uses iic bus to detect the EEPROM process on the throne that iic bus connects, and is specially:
Described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address to assigned I IC device address, if assigned I IC device address has ACK to reply, it is on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne then to detect the EEPROM that the iic bus of assigned I IC device address connects.
3. method as claimed in claim 2 is characterized in that, described assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF;
Described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address to assigned I IC device address, specifically comprises:
Described IIC opertaing device is carried out the operation that begins to read default byte from the read operation start address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF to assigned I IC device address.
4. as claim 2 or 3 described methods, it is characterized in that described IIC opertaing device obtains the process of the IIC device address of described EEPROM, is specially:
When the EEPROM of the iic bus connection that detects assigned I IC device address was on the throne, the IIC device address that described IIC opertaing device obtains described EEPROM was described assigned I IC device address.
5. as claim 2 or 3 described methods, it is characterized in that described IIC opertaing device obtains the process of length of manufacturer's manufacturing information of described EEPROM, is specially:
When the EEPROM of the iic bus connection that detects assigned I IC device address was on the throne, described IIC opertaing device obtained the length of manufacturer's manufacturing information of described EEPROM by the operation of reading default byte.
6. method as claimed in claim 5 is characterized in that, described default byte comprises 2 bytes, and these 2 bytes are byte 0 and byte 1, if read designated identification from byte 0, then obtains the length of manufacturer's manufacturing information of described EEPROM by byte 1; Otherwise, obtain the length of manufacturer's manufacturing information of described EEPROM by byte 0.
7. the method for claim 1, it is characterized in that, described IIC opertaing device obtains manufacturer's manufacturing information of storing among the described EEPROM by the length of IIC device address, read operation start address and the manufacturer's manufacturing information of described EEPROM, also comprises afterwards:
Described IIC opertaing device stores described manufacturer manufacturing information in internal random access memory RAM or the Installed System Memory into; To be used for when CPU need be known described manufacturer manufacturing information, in described internal RAM or Installed System Memory, reading described manufacturer manufacturing information.
8. the method for claim 1 is characterized in that, described IIC opertaing device is integrated in complex programmable logic device (CPLD) or the on-site programmable gate array FPGA, and described IIC opertaing device is independent of the CPU that operational system starts software; Perhaps,
Described IIC opertaing device is integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and this nuclear is independent of the nuclear of operational system startup software in the multi-core CPU.
9. two-wire serial bus IIC opertaing device, one side of iic bus is connected with the uncertain electricallyerasable ROM (EEROM) EEPROM of quantity, and opposite side is connected with described IIC opertaing device, stores manufacturer's manufacturing information of place module among the described EEPROM, it is characterized in that this equipment comprises:
EEPROM in-place detection submodule is used to use iic bus to detect the situation on the throne of the EEPROM of iic bus connection;
The core controlling sub, be used for when the EEPROM that detects the iic bus connection is on the throne, obtain the IIC device address of described EEPROM and the length of manufacturer's manufacturing information, and the length of IIC device address, read operation start address and manufacturer's manufacturing information by described EEPROM is obtained manufacturer's manufacturing information of storing among the described EEPROM;
The process of obtaining manufacturer's manufacturing information of storing among the described EEPROM is independent of system start-up software, and carries out with the system start-up software parallel.
10. IIC opertaing device as claimed in claim 9 is characterized in that,
Described EEPROM in-place detection submodule, specifically be used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address, if assigned I IC device address has ACK to reply, it is on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects; If assigned I IC device address does not have ACK to reply, it is not on the throne to detect the EEPROM that the iic bus of assigned I IC device address connects.
11. IIC opertaing device as claimed in claim 10 is characterized in that, described assigned I IC device address comprises: 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, 0xAF;
Described EEPROM in-place detection submodule is further used for carrying out the operation that begins to read default byte from the read operation start address to assigned I IC device address according to the predefined procedure between 0xA1,0xA3,0xA5,0xA7,0xA9,0xAB, 0xAD, the 0xAF.
12. as claim 10 or 11 described IIC opertaing devices, it is characterized in that,
Described core controlling sub specifically is used for when the EEPROM of the iic bus connection that detects assigned I IC device address is on the throne, and the IIC device address that obtains described EEPROM is described assigned I IC device address.
13. as claim 10 or 11 described IIC opertaing devices, it is characterized in that,
Described core controlling sub specifically is used for obtaining the length of manufacturer's manufacturing information of described EEPROM by the operation of reading default byte when the EEPROM of the iic bus connection that detects assigned I IC device address is on the throne.
14. IIC opertaing device as claimed in claim 13, it is characterized in that described default byte comprises 2 bytes, these 2 bytes are byte 0 and byte 1, if read designated identification, then obtain the length of manufacturer's manufacturing information of described EEPROM by byte 1 from byte 0; Otherwise, obtain the length of manufacturer's manufacturing information of described EEPROM by byte 0.
15. IIC opertaing device as claimed in claim 9 is characterized in that, this IIC opertaing device also comprises: internal RAM and Installed System Memory visit submodule;
Described core controlling sub also is used for described manufacturer manufacturing information is stored into internal RAM or stores described manufacturer manufacturing information into Installed System Memory by Installed System Memory visit submodule;
Described internal RAM is used to preserve manufacturer's manufacturing information, to be used for reading described manufacturer manufacturing information in described internal RAM when CPU need be known described manufacturer manufacturing information;
Described Installed System Memory visit submodule is used for storing described manufacturer manufacturing information into Installed System Memory, to be used for reading described manufacturer manufacturing information in described Installed System Memory when CPU need be known described manufacturer manufacturing information.
16. IIC opertaing device as claimed in claim 9 is characterized in that, described IIC opertaing device is integrated in complex programmable logic device (CPLD) or the on-site programmable gate array FPGA, and described IIC opertaing device is independent of the CPU that operational system starts software; Perhaps,
Described IIC opertaing device is integrated in the nuclear of inoperative system start-up software in the multi-core CPU, and this nuclear is independent of the nuclear of operational system startup software in the multi-core CPU.
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