CN102165606A - 抑制具有异质结的光电器件中外延生长的方法和光电器件 - Google Patents
抑制具有异质结的光电器件中外延生长的方法和光电器件 Download PDFInfo
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Abstract
本发明涉及一种用于在具有异质结的光电器件中抑制外延生长的方法,该光电器件包括晶体硅基质和至少一个无定形或微晶硅层,其中,所述方法特征在于其包括纹理化晶体硅表面的步骤。
Description
技术领域
本发明涉及光电器件领域,更特别地,涉及用于抑制具有异质结的光电器件中外延生长的方法,该光电器件包括晶体硅基质。本发明还涉及所述光电器件。
本发明对于意欲用于生产电能的光电池发现了特别有意义的应用,但其更普遍地应用于其中将光辐射转化成电信号的任何结构中,例如光检测器。
背景技术
已知,具有异质结的光电器件包括晶体硅基质,该晶体硅基质覆盖有一层或几层无定形硅或微晶硅。由此,此种器件可依次包括晶体硅基质、氢化非晶硅层和氢化微晶硅层。
为了提高具有异质结的包括晶体硅基质的光电器件的性能,尤其是输出电流,已知通过用各向异性蚀刻法形成许多锥形不规则切面来如何修饰晶体硅基质的纹理,正如在美国专利4,137,123中所述。用于形成锥体的在碱性介质中的该各向异性湿化学蚀刻方法可以产生谷,该谷的底部具有陡沿/锐边。将连接锥体基部的区域称作谷。
在某些文献中,尤其是在美国专利6,207,890中,可以看出,在具有陡沿的这些谷中,氢化非晶硅的沉积不够厚,其缺点是减少具有带晶体硅基质的异质结的太阳能电池的开路电压(Voc)和填充系数(FF)。美国专利6,207,890通过以下来解决此问题:提议进行基质的各向异性蚀刻,以将谷的底部磨圆,其效果是能够用等离子体增强化学气相沉积方法(PECVD)来沉积均匀厚度的无定形或微晶硅层。
通过使用本领域技术人员已知的适合沉积条件(PECVD),可能获得具有如下异质结的电池:即使所述基质在使用各向异性蚀刻方法后具有锥形纹理,在该异质结中沉积在晶体硅基质上的无定形或微晶硅层也具有恒定的厚度。然而,如图1所示,在氢化无定形或晶体硅生长期间,在晶体硅基质的具有陡沿的谷中观察到外延过程。实际上,在锥体平面上非常清晰的无定形硅和微晶硅层的界面,在形成于晶体硅基质上的锥体的陡沿谷中变得不清晰。此局部外延生长具有以下缺点:降低具有晶体硅基质的太阳能异质结电池的开路电压(Voc)以及由此降低其效率。
因此,本发明的目的是通过提出方法来克服此缺点,用该方法,在氢化无定形或微晶硅生长期间,在具有异质结的光电器件中,可以使局部外延生长降低和使外延的影响受到抑制,光电器件包括具有锥体纹理的晶体硅基质。
发明内容
为此目的,根据本发明,提出用于在具有异质结的光电器件中抑制外延生长的方法,该光电器件包括晶体硅基质和至少一个无定形或微晶硅层,该方法特征在于其包括使晶体硅表面纹理化的步骤。
在称为选择A的第一个可选择实施方案中,所述纹理化步骤包括在晶体硅基质上形成锥体,所述锥体具有尺寸严格大于5μm的基部。
在称为选择B的第二个可选择实施方案中,所述纹理化步骤包括在晶体硅基质上形成锥体,所述锥体具有规则布局,以便少于20%的晶体硅表面覆盖有具有亚微尺寸的锥体,和至少一半以上晶体硅表面覆盖有如下锥体:基部的平均尺寸b包括在b±5μm的范围内,其中b严格大于1μm。
根据称为选择C的第三个可选择实施方案,所述纹理化步骤包括在晶体硅基质上形成锥体和谷,所述谷具有磨圆的底部。
本发明还涉及具有异质结的光电器件,该光电器件包括晶体硅基质,其中在氢化无定形或微晶硅在所述晶体硅基质上生长期间,根据上述前两种方法A和B之一使外延过程受到抑制。
附图说明
参考附图,阅读后述说明书,本发明其它特征将变得更清楚,在附图中:
图1是通过透射电子显微镜获得的显微照片,其显示在现有技术的具有异质结的光电器件中的外延生长,包括在具有锥体的晶体硅基质上的无定形硅层和微晶硅层,其谷具有陡沿。
图2是显示晶体硅基质的照片,该晶体硅基质表面根据本发明方法的步骤A已纹理化。
图3是显示晶体硅基质的照片,该晶体硅基质表面根据本发明方法的步骤B已纹理化。
图4是通过透射电子显微镜获得的显微照片,其显示在具有异质结的光电器件中外延生长的抑制,包括在晶体硅基质上的无定形硅层和微晶硅层,所述晶体硅基质已根据组合本发明步骤A、B和C的方法纹理化。
具体实施方式
根据本发明,用于抑制在具有异质结的光电器件中外延生长的方法包括晶体硅表面的纹理化步骤,所述光电器件包括晶体硅基质和至少一个微晶硅或无定形硅层。
在称为选择A的第一个可选择实施方案中,所述纹理化步骤包括在晶体硅基质上形成锥体,所述锥体具有基部,该基部的侧边具有严格大于5μm的尺寸。
优选地,大多数c-Si表面,即,严格地多余一半c-Si表面,覆盖有具有基部的锥体,该基部的侧边具有严格大于5μm的尺寸。优选地,所述锥体基部的侧边具有包括在如下范围内的尺寸:5至25μm,更优选地10(不包括)至20μm。大尺寸锥体的形成允许降低每单位面积的谷的密度。锥体的高度h可以很一般地通过公式tan(54.74)=(2xh)/c与基部的边缘c的尺寸相关。锥体的尺寸和它们的均匀度可以通过扫描显微图像处理或立体重建来容易地确定(Kuchler等人的STEREOSCOPIC RECONSTRUCTION OF RANDOMLY TEXTURED SILICON SURFACES,17th European Photovoltaic Solar Energy Conference,October 22nd to 26th,2001,Munich)。
所述锥体可以通过各向异性蚀刻用例如以下来形成:KOH/IPA混合物或NaOH或TMAH溶液(具有或不具有IPA)或Na2CO3/NaHCO3的混合物。优选地,对于此各向异性蚀刻,使用2-3重量%IPA浓度和6-8体积%的水浓度的KOH溶液,在80℃下蚀刻时间为5-40分钟。锥体的尺寸随着蚀刻时间而增加,并强烈地依赖于所选硅基质的杂质水平和类型。KOH浓度的降低、IPA浓度的降低或蚀刻时间的增加促进大锥体形成。这些参数将根据想要的锥体尺寸来调整。注意,将增加蚀刻时间直至获得想要的锥体尺寸。本领域技术人员控制通过上述方法获得的尺寸以便确定各向异性蚀刻参数。
图2示出晶体硅基质,其表面已根据步骤A纹理化。获得的锥体具有基部,该基部的侧边平均大于20μm,具有良好的均匀度。
在称为选择B的第二个可选择实施方案中,所述纹理化步骤包括在晶体硅基质上形成锥体,所述锥体具有如下定义的规则布局:低百分比的亚微锥体(少于20%的c-Si表面覆盖有具有亚微尺寸的锥体),和至少一半以上c-Si表面覆盖有如下锥体:基部侧边的平均尺寸b包括在b±5μm的范围内,其中b严格大于1μm。优选地,少于10%的c-Si表面覆盖有具有亚微尺寸的锥体,超过2/3的c-Si表面覆盖有如下锥体:基部侧边的平均尺寸b包括在b±2.5μm的范围内。使用此步骤,通过一方面抑制亚微纹理元件和另一方面抑制嵌套锥体,可以降低每单位表面的谷密度。
因此,相对于选择A,选择B特征在于锥体尺寸的更好均匀度,与选择A不同,锥体尺寸小于5μm,但具有小比例的具有亚微尺寸的锥体。图3示出晶体硅基质,其表面已根据步骤B纹理化。锥体较小并具有基部,该基部的侧边平均小于5μm,很少有锥体具有亚微尺寸。
所述锥体基部的侧边的平均尺寸优选包括在如下范围内:3μm至25μm,更优选5μm(不包括)至20μm。
步骤B可以通过各向异性蚀刻来实现,例如用KOH/IPA混合物,并注意温度的均匀性(例如根据描述于如下文件中的方法:W.Sparber等人的《Comparison of Texturing Methods for Monocrystalline Silicon Solar Cells using KOH and Na2CO3》”,Proc.of the 3rd World Conf.on Photovoltaic,Osaka,2003),或用NaOH或TMAH溶液(具有或不具有IPA)或Na2CO3/NaHCO3的混合物。蚀刻方法的参数根据晶体硅基质的初始表面情况来调整。优选地,将使用类似于用于选择A的一个方法的KOH/IPA溶液,同时注意KOH浓度的降低、IPA浓度的降低或蚀刻时间的增加促进大锥体形成。因此,对于选择B来说,如果想要获得小尺寸锥体,通常将使用比选择A所用的蚀刻时间更短的蚀刻时间。对于选择B来说,温度和搅拌的均匀度是根本的,以便锥体尺寸具有更好的均匀度。
在称为选择C的第三个可选择实施方案中,所述纹理化步骤包括在晶体硅基质上形成锥体和谷,所述谷具有磨圆的底部。
所述谷磨圆的底部具有大于0.005μm的曲率半径,优选0.05μm至15μm的曲率半径。至少50%的锥体应当具有此磨圆的底部,优选至少它们的75%。
该步骤可以通过各向异性蚀刻来实现,例如,用所谓的CP133溶液,即HF(50%在去离子水中),HNO3(100%发烟酸)和CH3COOH(100%),比例为1∶3∶3的混合物。还可以使用仅含有HF和HNO3的溶液。处理时间优选为3至20秒,同样依赖于所选的硅基质。
依赖于晶体硅基质的初始表面情况,该步骤可以分解成两个步骤,首先在晶体硅基质上形成不规则锥体,例如根据描述于如下出版物中的方法:W.Sparber等人的《Comparison of Texturing Methods for Monocrystalline Silicon Solar Cells using KOH and Na2CO3》,Proc.of the 3rd World Conf.on Photovoltaic,Osaka,2003,然后通过各向异性蚀刻将谷的底部磨圆。
本领域技术人员掌握用于形成锥体的方法,根据两者中的任何一个,他们知道如何调整这些不同方法的参数以便获得具有所追求特征锥体。本发明不是基于用于形成锥体的方法,而是基于利用这些锥体的尺寸和分布,来降低在氢化无定形或微晶硅生长期间在具有异质结的光电器件中在具有锥体纹理的晶体管基质上的局部外延生长。注意,本领域技术人员可以参考以下出版物:W Sparber,O.Schultz,D.Biro,G.Emanuel,R.Preu,A.Poddey and D.Borchert,“Comparison of Texturing Methods for Monocrystalline Silicon Solar Cells Using KOH and Na2CO3”,Proc.of the 3rd World Conf.on Photovoltaic,Osaka,2003。此外,温度和搅拌的均匀度对于获得均匀的结构是至关重要的。
这三个可选择实施方案A、B和C可以彼此、其中两个或三个组合。
因此,可以通过如下方式来应用本发明的方法:单独应用选择A、B或C中的任何一个,或组合A和B、A和C、B和C、或A、B和C。A和B的组合步骤可以在单个步骤中实现。
图4示出通过透射电子显微镜获得的照片,其显示在具有异质结的光电器件中外延生长的抑制,包括在晶体硅基质上的无定形硅层和微晶硅层,所述晶体硅基质已根据组合本发明步骤A、B和C的方法纹理化。在此图中,晶体硅层、无定形硅层和微晶硅层之间的界面可以清楚地看出,这显示外延生长的降低。
在用于纹理化晶体硅表面的步骤之后,将至少一个无定形或微晶硅层沉积在由此纹理化的晶体硅基质上,以便根据本领域技术人员已知的方法获得具有异质结的光电器件。
本发明涉及具有异质结的光电器件,该光电器件包括晶体硅基质,其中在氢化无定形或微晶硅在所述晶体硅基质上生长期间,根据上述前两种方法A和B之一使外延过程受到抑制。根据第一个可选择实施方案,此器件可包括纹理化的晶体硅基质,在该晶体硅基质表面上具有锥体,锥体具体基部,该基部具有严格大于5μm的尺寸,优选5μm至25μm,更优选地10至20μm。
根据另一可选择实施方案,本发明的光电器件包括纹理化的晶体硅基质,在该晶体硅基质表面上具有锥体,锥体的规则布局如下:低百分比的亚微锥体(少于20%的c-Si表面覆盖有具有亚微尺寸的锥体),和至少一半以上c-Si表面覆盖有如下锥体:基部侧边的平均尺寸b包括在b±5μm的范围内,其中b严格大于1μm。优选地,至少10%的c-Si表面覆盖有具有亚微尺寸的锥体,超过2/3的c-Si表面覆盖有如下锥体:基部的尺寸b包括在b±2.5μm的范围内。
另外,根据所述两个方案中的任何一个,所述纹理化的晶体硅基质可包括具有磨圆底部的谷。所述谷的磨圆底部具有大于0.005μm的曲率半径,优选具有0.05μm至15μm的曲率半径。该谷的磨圆底部根据上述方法C获得。
此外,可将上述限定的两个可选方案合并以获得包括纹理化晶体硅基质的器件,在该晶体硅基质表面具有锥体,锥体带基部,该基部的尺寸严格大于5μm,并且具有如下定义的规则布局:低百分比的亚微锥体(少于20%的c-Si表面覆盖有具有亚微尺寸的锥体),和至少一半以上c-Si表面覆盖有如下锥体:基部的尺寸b包括在b±5μm的范围内。优选地,少于10%的c-Si表面覆盖有具有亚微尺寸的锥体,超过2/3的c-Si表面覆盖有如下锥体:基部的尺寸b包括在b±2.5μm的范围内。
另外,如上所述,此处所述的纹理化的晶体硅基质可以包括具有磨圆的底部的谷。
此外,如果控制各向同性蚀刻时间,磨圆谷底部的步骤还给出以下可能:通过控制该过程来磨圆锥体的顶部从而不降低捕获的光。这能够提高装配期间太阳能电池的稳健性。实际上,通过减少可能破损的锥体尖顶的数量,特别是当这些尖顶是特别锐利的时候,磨圆锥体的顶部能够显著降低电池在装配期间的机械损坏。
由此,根据本发明优选的可选实施方案,可获得具有异质结的光电器件,该光电器件包括纹理化的晶体硅基质,在该晶体硅基质表面具有锥体和谷,所述锥体具有基部,该基部的尺寸b严格大于5μm,所述锥体具有如下定义的规则布局:低百分比的亚微锥体(少于20%的c-Si表面覆盖有具有亚微尺寸的锥体),和至少一半以上c-Si表面覆盖有如下锥体:基部的尺寸b包括在b±5μm的范围内。优选地,少于10%的c-Si表面覆盖有具有亚微尺寸的锥体,超过2/3的c-Si表面覆盖有如下锥体:基部的尺寸b包括在b±2.5μm的范围内,所述谷具有磨圆的底部,该底部的曲率半径大于0.005μm,优选0.05μm至15μm。
根据本发明获得的器件的效率大于现有异质结器件的效率。
实施例
通过用于纹理化晶体硅基质的步骤A,B,A和B,以及A、B和C制备3个具有异质结的光电池。
步骤A和B根据以下出版物实现:W.Sparber,O.Schultz,D.Biro,G.Emanuel,R.Preu,A.Poddey and D.Borchert,″Comparision of Texturing Methods for Monocrystalline Silicon Solar Cells Using KOH and Na2CO3”,Proc.of the 3rd World Conf.on Photovoltaic,Osaka,2003,以便获得本发明的特征。
至于步骤C,将基质浸入新鲜制备的包括以下的水溶液:50%氟化氢(HF)、硝酸(100%发烟酸)和100%乙酸(CH3COOH),比例:1∶3∶3,浸入约5秒或约1分钟。
作为对比,根据描述于以下出版物的方法:″ Experimental Optimization of an Anisotropic etching process for random texturization of silicon so
测量以下参数:按照AM1.5标准的开路电压(Voc)、填充系数(FF)、短路电流密度(Jsc)和效率。
结果示于下表:
实施例 | Voc(mV) | FF(%) | Jsc(mA/cm2) | 效率 |
比较 | 601 | 68.4 | 34.5 | 14.2 |
步骤A | 631 | 72.9 | 34.6 | 15.5 |
步骤B | 618 | 69.5 | 34.6 | 14.9 |
步骤A+B | 660 | 68.9 | 35.6 | 16.0 |
步骤A+B+C | 700 | 67.0 | 36.5 | 17.0 |
此表的结果显示:通过本发明的方法,带异质结的光电器件的性能提高了,特别是当将三个步骤A、B和C合并时。
Claims (22)
1.一种用于在具有异质结的光电器件中抑制外延生长的方法,该光电器件包括晶体硅基质和至少一个无定形或晶体硅层,其特征在于:该方法包括用于纹理化所述晶体硅基质表面的步骤。
2.根据权利要求1所述的方法,其特征在于:所述纹理化步骤为步骤A,其包括在该晶体硅基质上形成锥体,所述锥体具有基部,所述基部尺寸严格大于5μm。
3.根据权利要求2所述的方法,其特征在于:所述纹理化步骤A包括在该晶体硅基质上形成锥体,大部分该晶体硅基质表面覆盖有锥体,所述锥体的尺寸严格大于5μm。
4.根据权利要求2和3中任一项所述的方法,其特征在于:所述锥体的基部具有5μm至25μm的尺寸,不包括5μm,更优选10μm至20μm的尺寸。
5.根据前述任一项权利要求中所述的方法,其特征在于:所述晶体硅基质表面的纹理化步骤A通过各向异性蚀刻实现。
6.根据权利要求1所述的方法,其特征在于:所述纹理化步骤为步骤B,包括在所述晶体硅基质上形成锥体,所述锥体具有规则布局,以便少于20%的所述晶体硅表面覆盖有具有亚微尺寸的锥体,至少一半以上所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±5μm的范围内,其中b严格大于1μm。
7.根据权利要求6所述的方法,其特征在于:所述纹理化步骤B包括在所述晶体硅基质上形成锥体,所述锥体具有规则布局,以便少于10%的所述晶体硅表面覆盖有具有亚微尺寸的锥体,至少2/3所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±2.5μm的范围内。
8.根据权利要求6和7中任一项所述的方法,其特征在于:所述晶体硅基质表面的纹理化步骤B通过各向异性蚀刻实现。
9.根据权利要求1所述的方法,其特征在于:所述纹理化步骤为步骤C,包括在所述晶体硅基质上形成锥体和谷,所述谷具有磨圆的底部。
10.根据权利要求9所述的方法,其特征在于:所述谷的磨圆底部具有大于0.005μm的曲率半径,优选0.005μm至15μm的曲率半径。
11.根据权利要求9和10中任一项所述的方法,其特征在于:至少50%的所述锥体通过谷连接,优选至少75%的所述锥体通过谷连接,所述谷的磨圆底部具有大于0.005μm的曲率半径,优选0.05μm至15μm的曲率半径。
12.根据权利要求9和11中任一项所述的方法,其特征在于:所述晶体硅基质表面的纹理化步骤C通过各向同性蚀刻实现。
13.根据权利要求9和11中任一项所述的方法,其特征在于:将所述晶体硅基质表面的纹理化步骤C分解为两个步骤,即,首先,通过各向异性蚀刻在所述晶体硅基质上形成不规则锥体,然后,通过各向同性蚀刻将所述谷底部磨圆。
14.根据前述任一项权利要求中所述的方法,其特征在于:所述晶体硅基质表面的纹理化步骤由合并纹理化步骤A、B和C中的两个或三个组成。
15.根据权利要求14所述的方法,其特征在于包括:
用于纹理化所述晶体硅基质表面的步骤通过各向异性蚀刻实现,以便在所述晶体硅基质表面形成锥体,该锥体具有基部,其尺寸b严格大于5μm,并且该锥体具有规则布局以便少于20%的所述晶体硅表面覆盖有具有亚微尺寸的锥体,至少一半以上所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±5μm的范围内;和
用于纹理化所述晶体硅基质表面的步骤通过各向同性蚀刻实现,以便在所述锥体中获得具有磨圆底部的谷。
16.一种具有异质结的光电器件,该光电器件包括晶体硅基质,该晶体硅基质具有纹理化的表面和至少一个无定形或微晶硅层,其中在所述无定形或微晶硅在所述晶体硅基质上生长期间外延受到抑制,该外延的抑制通过根据权利要求1至15任一项中的方法获得。
17.一种具有异质结的光电器件,该光电器件包括晶体硅基质,该晶体硅基质具有纹理化的表面和至少一个无定形或微晶硅层,其中在所述无定形或微晶硅在所述晶体硅基质上生长期间外延受到抑制,其特征在于:所述纹理化的晶体硅基质在其表面具有锥体,该锥体具有基部,其尺寸b严格大于5μm,优选5μm至25μm,不包括5μm,更优选10μm至20μm。
18.根据权利要求17所述的器件,其特征在于:所述锥体进一步具有规则布局,以便少于20%的所述晶体硅表面覆盖有具有亚微尺寸的锥体,至少一半以上所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±5μm的范围内。
19.一种具有异质结的光电器件,该光电器件包括晶体硅基质表面和至少一个无定形或微晶硅层,其中在所述无定形或微晶硅在所述晶体硅基质上生长期间外延受到抑制,其特征在于:所述纹理化的晶体硅基质在其表面具有锥体,所述锥体具有规则布局,以便少于20%的晶体硅表面覆盖有具有亚微尺寸的锥体,至少一半以上所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±5μm的范围内,其中b严格大于1μm。
20.根据权利要求18和19中任一项所述的器件,其特征在于:少于10%的所述晶体硅表面覆盖有具有亚微尺寸的锥体,和至少2/3所述晶体硅表面覆盖有如下锥体:其基部尺寸b包括在b±2.5μm的范围内。
21.根据权利要求16至20中任一项所述的器件,其特征在于:所述晶体硅基质在所述锥体间具有谷,该谷具有磨圆的底部。
22.根据权利要求21所述的器件,其特征在于:所述谷的所述磨圆底部具有大于0.005μm的曲率半径,优选0.05μm至15μm的曲率半径。
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WO2010023318A1 (fr) | 2010-03-04 |
US20110174371A1 (en) | 2011-07-21 |
EP2332182A1 (fr) | 2011-06-15 |
EP2159851A1 (fr) | 2010-03-03 |
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