EP2332182A1 - Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectrique - Google Patents
Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectriqueInfo
- Publication number
- EP2332182A1 EP2332182A1 EP09782410A EP09782410A EP2332182A1 EP 2332182 A1 EP2332182 A1 EP 2332182A1 EP 09782410 A EP09782410 A EP 09782410A EP 09782410 A EP09782410 A EP 09782410A EP 2332182 A1 EP2332182 A1 EP 2332182A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- pyramids
- crystalline silicon
- silicon substrate
- microns
- covered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 105
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 26
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims description 20
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000000407 epitaxy Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000001788 irregular Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000243 solution Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000000203 mixture Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000001000 micrograph Methods 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- UIIMBOGNXHQVGW-UHFFFAOYSA-M Sodium bicarbonate Chemical compound [Na+].OC([O-])=O UIIMBOGNXHQVGW-UHFFFAOYSA-M 0.000 description 2
- 238000013019 agitation Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004621 scanning probe microscopy Methods 0.000 description 1
- 235000017557 sodium bicarbonate Nutrition 0.000 description 1
- 229910000030 sodium bicarbonate Inorganic materials 0.000 description 1
- 235000017550 sodium carbonate Nutrition 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to the field of photoelectric devices. It relates, more particularly, to a method for limiting epitaxial growth in a heterojunction photoelectric device comprising a crystalline silicon substrate. The present invention also relates to said photoelectric device.
- the present invention finds a particularly interesting application for the production of photovoltaic cells for the production of electrical energy, but it also applies, more generally, to any structure in which a light radiation is converted into a electrical signal, such as photodetectors.
- the heterojunction photoelectric devices comprise a crystalline silicon substrate covered with a layer or several layers of amorphous silicon or microcrystalline silicon.
- a crystalline silicon substrate covered with a layer or several layers of amorphous silicon or microcrystalline silicon.
- Such a device can thus comprise, in order, a crystalline silicon substrate, a hydrogenated amorphous silicon layer and a hydrogenated microcrystalline silicon layer.
- An object of the present invention is therefore to overcome this disadvantage, by providing a method for reducing local epitaxial growth and to limit the influence of epitaxy in a heterojunction photoelectric device, comprising a crystalline silicon substrate. having a pyramidal texture, during the growth of hydrogenated amorphous or microcrystalline silicon. Disclosure of the invention For this purpose, and in accordance with the present invention, there is provided a method for limiting the epitaxial growth in a heterojunction photoelectric device comprising a crystalline silicon substrate and at least one amorphous or microcrystalline silicon layer, this method being characterized in that it comprises a step of texturing the crystalline silicon surface.
- said texturing step comprises the formation of pyramids on the crystalline silicon substrate, said pyramids having a base whose dimensions are strictly greater than 5 microns.
- the texturing step comprises the formation of pyramids on the crystalline silicon substrate, said pyramids having a regular arrangement such that less than 20% of the surface of the crystalline silicon is covered with pyramids having submicron dimensions and more than at least half of the surface of the crystalline silicon is covered with pyramids whose average dimensions b of the base are within a range b ⁇ 5 ⁇ m, where b is strictly greater than 1 ⁇ m .
- the texturing step comprises the formation of pyramids and valleys on the crystalline silicon substrate, said valleys having a rounded bottom.
- the present invention also relates to a heterojunction photoelectric device comprising a crystalline silicon substrate in which the epitaxial process during the growth of hydrogenated amorphous or microcrystalline silicon on said crystalline silicon substrate has been limited according to one of the first two processes A and B described above. Brief description of the drawings
- FIG. 1 is a micrograph obtained by a transmission electron microscope showing the epitaxial growth in a heterojunction photoelectric device of the prior art, comprising an amorphous silicon layer and a microcrystalline silicon layer on a crystalline silicon substrate having pyramids whose valleys are sharp-edged
- - Figure 2 is a photograph showing a substrate of crystalline silicon whose surface has been textured according to step A of the process of the invention
- FIG. 3 is a photograph showing a crystalline silicon substrate whose surface has been textured according to step B of the process of the invention .
- FIG. 4 is a micrograph obtained by a transmission electron microscope showing the limitation of epitaxial growth in a heterojunction photoelectric device comprising an amorphous silicon layer and a microcrystalline silicon layer on a textured crystalline silicon substrate according to the combined method. steps A, B and C of the invention.
- the method for limiting the epitaxial growth in a heterojunction photoelectric device comprising a crystalline silicon substrate and at least one amorphous or microcrystalline silicon layer, comprises a step of texturing the crystalline silicon surface.
- said texturing step comprises the formation of pyramids on the crystalline silicon substrate, said pyramids having a base whose sides have dimensions strictly greater than 5 microns.
- c-Si c-Si
- most of the surface of c-Si, strictly more than half, is covered by pyramids having a base whose sides have dimensions strictly greater than 5 microns.
- the sides of the base of said pyramids have dimensions of between 5 microns and 25 microns, and more preferably between 10 microns excluded and 20 microns.
- the formation of large pyramids makes it possible reduce the density of valleys per unit area.
- the size of pyramids and their uniformity can easily be determined by scanning microscopy or stereoscopic reconstruction (Kuchler et al., STEREOSCOPIC RECONSTRUCTION OF RANDOMLY TEXTURED SILICON SURFACES, 17th European Photovoltaic Solar Energy Conference, October 22nd to 26th 2001, Kunststoff).
- the pyramids can be formed by anisotropic etching, for example by a KOH / IPA mixture or by a solution of NaOH, or of TMAH (with or without IPA) or a Na 2 CO 3 / NaHCO 3 mixture.
- a solution of KOH at weight concentrations of 2-3% IPA at volume concentrations of 6-8% in water and etching times of 5-40 minutes at 80 ° C are used for this anisotropic etching.
- the size of the pyramids increases with the attack time and strongly depends on the type and doping level of the selected silicon substrate. Decreasing the concentration of KOH, decreasing the concentration of IPA or increasing the attack time favor the large pyramids. These parameters will be adjusted according to the desired pyramid sizes. In particular, the attack time will be increased until the desired pyramid sizes are obtained.
- Figure 2 shows a crystalline silicon substrate whose surface has been textured according to this step A. The pyramids obtained have a base whose sides are on average greater than 20 microns, with good uniformity.
- said texturing step comprises the formation of pyramids on the crystalline silicon substrate, said pyramids having a regular arrangement defined by a small presence of submicron pyramids. (Less than 20% of the c-Si surface is covered with submicron-sized pyramids) and more than at least half of the surface of the c-Si is covered with pyramids whose average dimensions b of the sides of the base are in an interval b ⁇ 5 ⁇ m, where b is strictly greater than 1 ⁇ m.
- the surface of the c-Si is covered with pyramids having submicron dimensions and more than 2/3 of the surface of the c-Si is covered with pyramids whose average dimensions b of the sides of the base are included in an interval b ⁇ 2.5 ⁇ m.
- This step makes it possible to reduce the density of valleys per unit area, on the one hand, by limiting the submicron texture elements and on the other hand by limiting the nested pyramids.
- option B is characterized by a better uniformity of the sizes of the pyramids, which may, unlike option A, be smaller than 5 microns, but with a small proportion of pyramids having submicron sizes.
- FIG. 3 represents a crystalline silicon substrate whose surface has been textured according to this step B. The pyramids are smaller and have a base whose sides are on average less than 5 ⁇ m and there are few pyramids of submicron dimensions.
- Step B can be carried out by anisotropic etching, for example by a KOH / IPA mixture with attention to the uniformity of the temperature (for example according to the method described in W. Sparber et al. Texturing Methods for Monocrystalline Silicon Solar CeIIs Using KOH and Na2C ⁇ 3 ", Proc., 3rd World Conf.on Photovoltaic, Osaka, 2003) or with a solution of NaOH, or TMAH (with or without IPA) or a Na2C ⁇ 3 / NaHCO3 mixture .
- the parameters of the etching process are adapted according to the initial surface state of the crystalline silicon substrate.
- a KOH / IPA solution similar to the method used for option A will be used, knowing that the decrease of the concentration of KOH, the decrease of the concentration of IPA or the increase of the attack time favor the large pyramids.
- attack times that are generally shorter than those used for variant A will be used if it is desired to obtain pyramids of small sizes. Uniformity of temperature and agitation are essential for this option B to have a better uniformity in the size of the pyramids.
- said texturing step comprises the formation of pyramids and valleys on the crystalline silicon substrate, said valleys having a rounded bottom.
- the rounded bottom valleys has a radius of curvature greater than 0.005 microns and preferably between 0.05 microns and 15 microns. At least 50% of the pyramids must have such a rounded bottom, preferably at least 75%.
- This step can be carried out by isotropic etching, for example using a so-called CP133 solution or a mixture of HF (50% in deionized H 2 O), HNO 3 (100% fuming) and CH 3 COOH. (100%), in the proportions 1: 3: 3.
- CP133 solution or a mixture of HF 50% in deionized H 2 O
- HNO 3 100% fuming
- CH 3 COOH. 100%
- a solution containing only HF and HNO 3 can also be used.
- the treatment times are preferably between 3 and 20 s and also depend on the Si substrate chosen.
- this step can be broken down into two steps, first of all the formation of irregular pyramids on a crystalline silicon substrate according to, for example, the process described in US Pat. publication W. Sparber et al. "Comparison of Texturing Methods for Monocrystalline Silicon Solar CeIIs Using KOH and Na2CO 3 ", Proc. of the 3rd World Conf. on Photovoltaic, Osaka, 2003 and then the rounding of valley bottoms by isotropic etching.
- Pyramid formation processes are mastered by those skilled in the art who knows how to adapt the parameters of these different processes to obtain pyramids having the desired characteristics according to one or the other variant.
- the invention does not lie in pyramid formation processes but in the use of the dimensions and distribution of these pyramids to reduce local epitaxial growth during the growth of hydrogenated amorphous or microcrystalline silicon on a crystalline silicon substrate having a pyramidal texture in a heterojunction photoelectric device.
- those skilled in the art can refer to the publication W. Sparber, O. Schultz, D. Biro, G. Emanuel, R. Preu, A. Poddey and D. Borchert, "Comparison of Texturing Methods for Monocrystalline Silicon
- the three embodiments A, B and C can be combined with each other, by two or three.
- FIG. 4 represents a micrograph obtained by a transmission electron microscope showing the limitation of the epitaxial growth in a heterojunction photoelectric device comprising an amorphous silicon layer and a microcrystalline silicon layer on a textured crystalline silicon substrate according to FIG. process combining steps A, B and C of the invention.
- This figure clearly shows the interfaces between the layers of crystalline silicon, amorphous silicon and microcrystalline silicon, which shows a reduction in epitaxial growth.
- at least one layer of amorphous silicon or microcrystalline is deposited on the crystalline silicon substrate and texture to obtain a device photoelectric heterojunction according to techniques known to those skilled in the art.
- the present invention relates to a heterojunction photoelectric device comprising a crystalline silicon substrate in which the epitaxial process during the growth of hydrogenated amorphous silicon or microcrystalline on said crystalline silicon substrate has been limited according to one of the two first methods A and B described above.
- a device may comprise a textured crystalline silicon substrate having on its surface pyramids having a base whose sides have dimensions strictly greater than 5 ⁇ m, preferably between 5 ⁇ m and 25 ⁇ m, and more preferably between 10 microns and 20 microns.
- the photoelectric device of the invention comprises a textured crystalline silicon substrate having on its surface pyramids having a regular arrangement defined by a small presence of submicron pyramids (less than 20% of the surface area).
- c-Si is covered with pyramids with submicron dimensions) and more than at least half of the surface of the c-Si is covered with pyramids whose average dimensions b of the sides of the base are within a range b ⁇ 5 ⁇ m where b is strictly greater than 1 ⁇ m.
- said crystalline silicon substrate and texture according to one or the other of said variants may comprise valleys having a rounded bottom.
- the rounded bottom valleys may have a radius of curvature greater than 0.005 microns and preferably between 0.05 microns and 15 microns. The rounded bottom of the valleys is obtained according to process C described above.
- the two variants defined above can be combined so as to obtain a device comprising a substrate of texture crystalline silicon having on its surface pyramids having a base whose dimensions b are strictly greater than 5 ⁇ m and having a regular arrangement defined by a small presence of submicron pyramids (less than 20% of the surface of c-Si is covered with pyramids with submicron dimensions) and more than at least half of the surface of the c-Si is covered with pyramids whose b-dimensions of the base are within a range b ⁇ 5 ⁇ m.
- the surface of the c-Si is covered with pyramids having submicron dimensions and more than 2/3 of the surface of the c-Si is covered with pyramids whose dimensions b of the base are within a range b ⁇ 2.5 ⁇ m.
- said crystalline silicon substrate and texture may comprise valleys having a rounded bottom, as defined above.
- the step of rounding the bottom of the valleys also allows, if one controls the isotropic etching time, to round the top of the pyramids, while controlling the process to not decrease the amount of trapped light. This makes it possible to improve the robustness of the solar cells during the assembly step. Indeed, rounding the top of the pyramids can significantly reduce mechanical defects during assembly of cells by decreasing the number of pyramid peaks that could be broken, especially when these peaks are particularly sharp.
- a heterojunction photoelectric device comprising a textured crystalline silicon substrate having on its surface pyramids and valleys, said pyramids having a base whose dimensions b are strictly greater than 5 ⁇ m and have a regular arrangement defined by a small presence of submicron pyramids (less than 20% of the c-Si surface is covered with pyramids with submicron dimensions) and more than at least half of the surface c-Si is covered with pyramids whose dimensions b of the base are in a range b ⁇ 5 ⁇ m.
- the surface of the c-Si is covered with pyramids having submicron dimensions and more than 2/3 of the surface of the c-Si is covered with pyramids whose b-dimensions of the base are within a range b ⁇ 2.5 ⁇ m, and said valleys having a rounded bottom, whose radius of curvature is greater than 0.005 microns and preferably between 0.05 microns and 15 microns.
- the devices according to the invention thus obtained have higher yields than existing heterojunction devices.
- Three heterojunction photovoltaic cells are prepared by following steps A, B, A and B, and A, B and C for texturing the crystalline silicon substrate. Steps A and B are carried out in accordance with the publication W.
- step C the substrate is quenched in an aqueous solution comprising 50% hydrogen fluoride (HF), nitric acid (100% fuming) and acetic acid (CH 3 COOH). ) at 100% in a 1: 3: 3 ratio, for about 5 seconds for a freshly prepared solution or about 1 minute in other cases.
- aqueous solution comprising 50% hydrogen fluoride (HF), nitric acid (100% fuming) and acetic acid (CH 3 COOH).
- a photovoltaic cell is produced whose crystalline silicon substrate is formed of small pyramids (base dimensions less than 5 microns) and irregular prepared by the method described in the publication King et al. "Experimental Optimization of an Anisotropic Etching Process for Random Texturization of Silicon Solar Cells",
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Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP09782410A EP2332182A1 (fr) | 2008-09-01 | 2009-08-31 | Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectrique |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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EP08163425A EP2159851A1 (fr) | 2008-09-01 | 2008-09-01 | Procédé pour limiter la croissance épitaxiale dans un dispositif photoélectrique à hétérojonctions et un tel dispositif photoélctrique |
PCT/EP2009/061223 WO2010023318A1 (fr) | 2008-09-01 | 2009-08-31 | Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectrique |
EP09782410A EP2332182A1 (fr) | 2008-09-01 | 2009-08-31 | Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectrique |
Publications (1)
Publication Number | Publication Date |
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EP2332182A1 true EP2332182A1 (fr) | 2011-06-15 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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EP08163425A Withdrawn EP2159851A1 (fr) | 2008-09-01 | 2008-09-01 | Procédé pour limiter la croissance épitaxiale dans un dispositif photoélectrique à hétérojonctions et un tel dispositif photoélctrique |
EP09782410A Withdrawn EP2332182A1 (fr) | 2008-09-01 | 2009-08-31 | Procede pour limiter la croissance epitaxiale dans un dispositif photoelectrique a heterojonctions et un tel dispositif photoelectrique |
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EP08163425A Withdrawn EP2159851A1 (fr) | 2008-09-01 | 2008-09-01 | Procédé pour limiter la croissance épitaxiale dans un dispositif photoélectrique à hétérojonctions et un tel dispositif photoélctrique |
Country Status (4)
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US (1) | US20110174371A1 (fr) |
EP (2) | EP2159851A1 (fr) |
CN (1) | CN102165606A (fr) |
WO (1) | WO2010023318A1 (fr) |
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---|---|---|---|---|
NL2003390C2 (en) | 2009-08-25 | 2011-02-28 | Stichting Energie | Solar cell and method for manufacturing such a solar cell. |
CN102400225A (zh) * | 2010-09-16 | 2012-04-04 | 上海神舟新能源发展有限公司 | 一种单晶硅太阳能电池的制绒液及其制备方法和应用 |
US20120085397A1 (en) * | 2010-10-11 | 2012-04-12 | Choul Kim | Solar cell |
NL2006298C2 (en) * | 2011-02-24 | 2012-08-27 | Energieonderzoek Ct Nederland | Solar cell and method for manufacturing such a solar cell. |
TWI453927B (zh) * | 2011-06-29 | 2014-09-21 | Ind Tech Res Inst | 多重反射結構以及光電元件 |
WO2014148443A1 (fr) * | 2013-03-19 | 2014-09-25 | 長州産業株式会社 | Élément photovoltaïque et procédé de fabrication associé |
WO2014155833A1 (fr) | 2013-03-28 | 2014-10-02 | 三洋電機株式会社 | Batterie solaire |
CN103253626A (zh) * | 2013-05-15 | 2013-08-21 | 西北工业大学 | 一种硅材料锥形结构及其制备方法 |
JP2018026388A (ja) | 2016-08-08 | 2018-02-15 | パナソニックIpマネジメント株式会社 | 太陽電池及び太陽電池の製造方法 |
EP3404724B1 (fr) * | 2017-05-19 | 2022-08-03 | LG Electronics Inc. | Cellule solaire et son procédé de fabrication |
CN116844937B (zh) * | 2023-06-30 | 2024-04-09 | 淮安捷泰新能源科技有限公司 | 硅片的rca清洗方法 |
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US4137123A (en) | 1975-12-31 | 1979-01-30 | Motorola, Inc. | Texture etching of silicon: method |
US6207890B1 (en) | 1997-03-21 | 2001-03-27 | Sanyo Electric Co., Ltd. | Photovoltaic element and method for manufacture thereof |
JP2000022185A (ja) * | 1998-07-03 | 2000-01-21 | Sharp Corp | 太陽電池セル及びその製造方法 |
JP2002359293A (ja) * | 2001-05-31 | 2002-12-13 | Toshiba Corp | 半導体装置 |
-
2008
- 2008-09-01 EP EP08163425A patent/EP2159851A1/fr not_active Withdrawn
-
2009
- 2009-08-31 WO PCT/EP2009/061223 patent/WO2010023318A1/fr active Application Filing
- 2009-08-31 EP EP09782410A patent/EP2332182A1/fr not_active Withdrawn
- 2009-08-31 US US13/061,584 patent/US20110174371A1/en not_active Abandoned
- 2009-08-31 CN CN2009801379031A patent/CN102165606A/zh active Pending
Non-Patent Citations (2)
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See also references of WO2010023318A1 * |
Also Published As
Publication number | Publication date |
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WO2010023318A1 (fr) | 2010-03-04 |
CN102165606A (zh) | 2011-08-24 |
US20110174371A1 (en) | 2011-07-21 |
EP2159851A1 (fr) | 2010-03-03 |
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