CN102158234A - RS (Reed-Solomon) coding performance limit detection method based on field element verification mode - Google Patents

Abstract

The invention discloses a method for detecting whether errors in received code groups of RS (Reed-Solomon) codes outnumber the code error correction performance limit. The method comprises the following steps of: forming an RS code extraneous root check matrix; and verifying the code groups processed by the RS codes by using the extraneous root check matrix, detecting whether the received code groups outnumber the RS code error correction performance limit. The invention has the beneficial technical effects of being capable of completely detecting whether the code groups received by the codes outnumber the code error correction performance limit, providing a reliable data output selection mode for code data output and effectively avoiding increase of data error codes.

Description

RS decoding performance limit detection method based on the field element verification mode

Technical field

The present invention relates to communication channel coding techniques field, relate in particular to a kind of RS sign indicating number and receive the detection method whether number of errors in the code character exceeds the error-correcting performance limit of sign indicating number.

Background technology

Information bit usually can cause the generation of mistake because of random noise or other interference effects in transmission or storing process.The channel decoding technology is the key technology of effectively eliminating transfer of data and storage mistake, guaranteeing the communication system data reliability.From the angle of coding method, existing channel coding technology can be divided into several big classes such as convolutional encoding, RS/BCH coding, algebraic geometry coding, Turbo coding, LDPC coding.Wherein, the RS sign indicating number is as a kind of outstanding burst error sign indicating number that entangles, and is used widely in radio communication and magnetic, light medium memory system.Error correcting capability is the RS sign indicating number of t, and being illustrated in code length is in the code character of n, is no more than t code word arbitrarily and makes a mistake, and all can obtain correcting; When number of errors v＞t, the situation that the error code number increases also might take place in not only correctly error correction, more how to bring difficulty for normal reception of data.For fear of this situation occurring, must effectively detect the reception code character and whether exceed the error-correcting performance limit, thereby can the code character that exceed the error-correcting performance limit not done correction process, directly output is as the input information of next stage Digital Signal Processing.

For the generator polynomial g (x) of GF (q) territory cyclic code, if contain 2t the inferior root of power continuously

Then the cyclic code that is generated by g (x) is called q system BCH code.If root a is primitive element a, this sign indicating number is a primitive BCH code.The RS sign indicating number is m ₀=1 q unit primitive BCH code.RS code parameters form is as follows: code length n=q-1; Information bit is k; Check digit n-k=2t; Minimum range d _Min=2t+1.

If the code polynomial that sends is C (x)=c _N-1x ^N-1+ c _N-2x ^N-2+ ... + c ₁X+c ₀, the mistake multinomial that channel causes is E (x)=e _N-1x ^N-1+ e _N-2x ^N-2+ ... + e ₁X+e ₀, be R (x)=r through receiving code multinomial after the Channel Transmission _N-1x ^N-1+ r _N-2x ^N-2+ ... + r ₁X+r ₀, three's relation is as follows:

R (x)=C (x)+E (x) is r _i=c _i+ e _i(i=0,1 ..., n-1)

For the q RS of unit sign indicating number, r _i, c _i, e _i(i=0,1 ..., n-1) q kind possibility value is arranged all.Therefore, not only bit-error locations to be considered during error correction, also the mistake amplitude will be considered.Suppose to have v error distribution at bit-error locations j ₁, j ₂..., j _vOn the position, and the mistake amplitude is respectively

Then

$E\left(x\right)=e_{j_1}{x}^{{\mathrm{<figure-callout\; id="1"\; label="j"\; filenames="HSA00000485888600012.png"\; state="\{\{state\}\}">j</figure-callout>}}_1}+e_{j_2}{x}^{{\mathrm{<figure-callout\; id="2"\; label="j"\; filenames="HSA00000485888600012.png"\; state="\{\{state\}\}">j</figure-callout>}}_2}+\&CenterDot;\&CenterDot;\&CenterDot;+e_{\mathrm{jv}}{x}^{\mathrm{jv}.}$ (0≤j ₁＜j ₂…＜j _v≤n-1)

When mistake number v≤t, general RS decoding algorithm all can be correct finds bit-error locations and mistake amplitude, finishes error code correction; When mistake number v＞t, not only bit-error locations can not correctly find, even the situation that the error code number increases occurs, thereby more how to bring difficulty for correct reception of data.Can not correctly detect reception code character mistake number and whether exceed RS decoding performance limit, become a weak point of existing decoding technique.

Summary of the invention

The present invention is directed to the prior art above shortcomings, the problem that solve is: before the output of RS decode results, whether the correct mistake number that detects in the decoding reception data exceeds the decoding performance limit; The mistake number does not exceed the RS decoding performance in limited time, and decoding output result is the data behind the error correcting, otherwise the output result is decoding input information data.

The present invention is achieved by the following technical solution for solving the problem that above-mentioned prior art exists:

The check matrix of RS sign indicating number is:

$H=\left[\begin{array}{ccccc}1& \mathrm{\&alpha;}& {\mathrm{\&alpha;}}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ 1& {\mathrm{\&alpha;}}^2& {\left({\mathrm{\&alpha;}}^2\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^2\right)}^{n-1}\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{2t}& {\left({\mathrm{\&alpha;}}^{2t}\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{2t}\right)}^{n-1}\end{array}\right]$ 2t * n matrix

Definition extraneous root check matrix is:

$H_a=\left[\begin{array}{ccccc}1& \mathrm{\&alpha;}& {\mathrm{\&alpha;}}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ 1& {\mathrm{\&alpha;}}^2& {\left({\mathrm{\&alpha;}}^2\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^2\right)}^{n-1}\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{n-1}& {\left({\mathrm{\&alpha;}}^{n-1}\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{n-1}\right)}^{n-1}\end{array}\right]$ (n-1) * the n matrix

To the code character behind the error correction, by syndrome computational methods shown in Figure 1, with the root element in the extraneous root check matrix code character is carried out check value and find the solution, according to the size of the verification value of finding the solution, can correctly judge the code character of carrying out behind the error correction as normal decoding data output.

The present invention compared with prior art, beneficial effect is: performance limit detection method proposed by the invention, whether the code character that can detect the decoding reception fully exceeds the performance of decoding error correction limit, for decoding data output provides reliable data output preference pattern, effectively avoided data error code number to increase the generation of situation.

Description of drawings

Fig. 1 is that syndrome calculates schematic diagram;

Fig. 2 is that check value calculates the realization schematic diagram;

Embodiment

To the code character behind the error correction, press the syndrome computational methods, carry out the field element verification, according to verification output, can correctly judge the code character of carrying out behind the error correction as normal decoding data output.Concrete verification mode is as follows:

Steps A: to the arbitrary coding codeword of RS sign indicating number by syndrome account form shown in Figure 1, in GF (q) territory, except 0 and a continuous 2t root element k-1 element, α ^2t+1, α ^2t+2..., α ^N-1Carry out verification and calculate, obtain R (α ^2t+1), R (α ^2t+2) ..., R (α ^N-1) value, as the memory pre-stored value.The syndrome computing block diagram as shown in Figure 1.Wherein, α ^2t+1, α ^2t+2..., α ^N-1Value can finish α by GF (q) the territory multiplying of primitive element α ¹Multiplication and add operation all can be finished by GF (q) territory multiplying and add operation.

Step B: to decoding output code group c ₀, c ₁..., c _N-1, at first use c ₀To register D set, other code words in the code character move into one by one subsequently.Move into computing in code character and finish, after register D value was upgraded, register memory storage numerical value was R (α ^2t+1), R (α ^2t+2) ..., R (α ^N-1).Consider from time complexity, adopt k-1 parallel computation circuit to finish check value and calculate, realize block diagram as shown in Figure 1.Wherein, α ^2t+1, α ^2t+2..., α ^N-1Multiplication is realized, by the look-up table mode of pre-stored GF (q) field element product value in the register; Add operation is finished by data mould 2 and computing.

Step C: compare R (α ^2t+1), R (α ^2t+2) ..., R (α ^N-1) memory pre-stored value in check value and the steps A, if identical, then index signal indication decoding effectively, otherwise decipher invalid.Decipher when effective the code word output of decoding module after with error correction; Otherwise decoding module is not done decoding to the code word that receives and is handled, and direct output information data is as the input data of next stage Digital Signal Processing.

Claims (2)

1. the RS decoding performance based on the field element verification mode is limit detection method, it is characterized in that: the code word behind the paginal translation code error correcting is carried out verification with the extraneous root check matrix, according to the size of check value, determine whether the number of errors in the decoding reception code character exceeds the error-correcting performance limit of sign indicating number.

2. the RS decoding performance limit detection method based on the field element verification mode according to claim 1, it is characterized in that: for block size is n, and the generator polynomial primitive element is the RS sign indicating number of α, and the composition form of extraneous root check matrix is as follows:

$H_a=\left[\begin{array}{ccccc}1& \mathrm{\&alpha;}& {\mathrm{\&alpha;}}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\mathrm{\&alpha;}}^{n-1}\\ 1& {\mathrm{\&alpha;}}^2& {\left({\mathrm{\&alpha;}}^2\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^2\right)}^{n-1}\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ & & \&CenterDot;& & \&CenterDot;\\ 1& {\mathrm{\&alpha;}}^{n-1}& {\left({\mathrm{\&alpha;}}^{n-1}\right)}^2& \&CenterDot;\&CenterDot;\&CenterDot;& {\left({\mathrm{\&alpha;}}^{n-1}\right)}^{n-1}\end{array}\right]$ (n-1) * the n matrix

The arbitrary coding codeword of RS sign indicating number is carried out verification with the extraneous root check matrix, obtain check value; Decoding after decoding output code word is carried out verification with the extraneous root check matrix, obtain new check value.Relatively if twice check value identical, then deciphered the reception code character and do not exceeded the performance of decoding error correction limit, limits otherwise the reception code character exceeds the decoding error-correcting performance.

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