CN111224741A - BCH code decoding method and decoder for satellite navigation and satellite navigation receiver - Google Patents

BCH code decoding method and decoder for satellite navigation and satellite navigation receiver Download PDF

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CN111224741A
CN111224741A CN201811405200.XA CN201811405200A CN111224741A CN 111224741 A CN111224741 A CN 111224741A CN 201811405200 A CN201811405200 A CN 201811405200A CN 111224741 A CN111224741 A CN 111224741A
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CN111224741B (en
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刘海洋
王云
巴晓辉
原青
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
    • G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables

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Abstract

The invention provides a BCH code decoding method, a decoder and a satellite navigation receiver for satellite navigation, which are used for reducing the decoding complexity of BCH (51,8) codes. In the invention, the hard decision vector is used for calculating the checksum of any bit in the code word, the error value of the bit is estimated according to the checksum, and the estimated error value is used for correcting the hard decision value corresponding to the bit in the hard decision vector, thereby completing the decoding of the bit. And repeating the above processes to finish the decoding results of all bits. In the decoding process, all code words of the BCH code do not need to be stored, and all possible information sequences do not need to be coded to obtain corresponding code words, so that the operation is relatively simple, and the decoding complexity is reduced.

Description

BCH code decoding method and decoder for satellite navigation and satellite navigation receiver
Technical Field
The invention relates to the field of information security, in particular to a BCH code decoding method and decoder for satellite navigation and a satellite navigation receiver.
Background
Bose-Chaudhuri-Hocquenghem (BCH) codes are an important class of error control coding schemes. The codes have cyclic characteristics, so that the coding and decoding can be efficiently realized, and the codes are widely applied to the fields of digital communication, storage and the like. BCH (51,8) codes with the code length of 51 bits and the information bits of 8 bits are adopted in the next generation GPS system L1C signal message data and the next generation Beidou global positioning system B1C signal message data as error control coding schemes and used for correcting errors occurring in the transmission process of navigation messages.
Because the code rate of the BCH (51,8) code is low, the navigation standard file recommends that the BCH (51,8) code is decoded by adopting the following method: and correlating all code words of the BCH code with the received vector, and finding an information sequence corresponding to the code word with the maximum correlation value as a decoding result. It can be seen that the decoding result obtained by adopting the method has optimality. However, this method requires storing all codewords of the BCH (51,8) code. If the code word is not stored, all possible information sequences need to be encoded in the decoding process to obtain corresponding code words, and then the corresponding code words are correlated with the received vector. Furthermore, correlation of the codeword with the received vector requires a multiply-accumulate operation. Therefore, the decoding method has high complexity, and is not suitable for being applied to practical navigation receivers, especially low-cost navigation receivers.
Disclosure of Invention
Accordingly, the present invention provides a BCH code decoding method, decoder and satellite navigation receiver for satellite navigation to reduce the decoding complexity of BCH (51,8) code.
In order to achieve the above object, the present invention provides the following technical solutions:
a BCH code decoding method for satellite navigation comprises the following steps:
acquiring a receiving value corresponding to a code word of the BCH code;
performing hard decision according to the received value to obtain a hard decision vector; the hard decision vector length is the same as the total length of the codeword;
decoding each bit in the code word by using a majority logic decoding principle and the hard decision vector to obtain a decoding vector;
any bit in the code words is represented as the ith bit, i is not less than 1; the decoding each bit in the codeword using a majority logic decoding principle and the hard decision vector to obtain a decoded vector comprises:
(i-1) th cycle left shift result X using the hard decision vectoriCalculating N groups of checksums corresponding to the ith bit; wherein each set of checksums comprises N sum values, each sum value of the N sum values resulting from the addition of at least four hard decision values in the hard decision vector; n is a positive integer;
obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsi(ii) a The decision vector SiThe length is N;
according to the decision vector SiCalculating an error value estimate e for the ith biti；
Using said eiTo the XiAnd correcting the hard decision value of the first bit to obtain a correction value, wherein the correction value is the decoding result of the ith bit.
A decoder, comprising:
a hard decision module: the device is used for acquiring a receiving value corresponding to a code word of the BCH code and performing hard decision according to the receiving value to obtain a hard decision vector; the hard decision vector length is the same as the total length of the codeword;
a decoding module: decoding each bit in the codeword by using a majority logic decoding principle and the hard decision vector to obtain a decoded vector;
wherein,
any bit in the code words is represented as the ith bit, i is not less than 1; the decoding each bit in the codeword using a majority logic decoding principle and the hard decision vector to obtain a decoded vector comprises:
(i-1) th cycle using the hard decision vectorLeft shift result XiCalculating N groups of checksums corresponding to the ith bit; wherein each set of checksums comprises N sum values, each sum value of the N sum values resulting from the addition of at least four hard decision values in the hard decision vector; n is a positive integer;
obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsi(ii) a The decision vector SiThe length is N;
according to the decision vector SiCalculating an error value estimate e for the ith biti；
Using said eiTo the XiAnd correcting the hard decision value of the first bit to obtain a correction value, wherein the correction value is the decoding result of the ith bit.
A satellite navigation receiver comprises the decoder.
It can be seen that, in the embodiment of the present invention, the hard decision vector is used to calculate the checksum of any bit in the codeword, the error value of the bit is estimated according to the checksum, and the estimated error value is used to correct the hard decision value corresponding to the bit in the hard decision vector, thereby completing the decoding of the bit. And repeating the above processes to finish the decoding results of all bits. In the decoding process, all code words of the BCH code do not need to be stored, and all possible information sequences do not need to be coded to obtain corresponding code words, so that the operation is relatively simple, and the decoding complexity is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a satellite navigation receiver according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a decoder according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for decoding BCH codes for satellite navigation according to an embodiment of the present invention;
FIG. 4 is a decoding performance diagram according to an embodiment of the present invention.
Detailed Description
The invention provides a BCH code decoding method and a decoder for satellite navigation and a satellite navigation receiver applying the decoder, so as to reduce the decoding complexity of BCH (51,8) codes.
Referring to fig. 1, the satellite navigation receiver may include an acquirer 101, a tracker 102, a data demodulator 103, a decoder 104, and the like.
The navigation signal sent by the satellite is captured by the satellite navigation receiver, the received value corresponding to the code word of the BCH code is obtained through signal tracking and data demodulation, then the received value is input into a decoder for decoding, and then the message information required by positioning can be obtained according to the decoding result to complete positioning.
Fig. 2 shows an exemplary structure of the decoder described above, including: a hard decision module 201 and a decoding module, wherein the hard decision module 201 is configured to perform hard decision on bits in a codeword of the BCH code to obtain a hard decision vector (the length of the hard decision vector is the same as the total length of the codeword, and in the present invention, the total length is 51); and the decoding module is used for: and decoding each bit in the code word by using a majority logic decoding principle and the hard decision vector to obtain a decoding vector.
Further, the decoding module may include at least: a checksum calculation module 203, a correction module 204 and a decoding output module 207.
In another embodiment of the present invention, still referring to fig. 2, the decoding module may further include a checking module 206 for checking whether the decoding result (decoding vector) is correct. In addition, the decoding module may further include a first buffer memory 202 and a second buffer memory 205 to buffer data.
Next, a decoding method performed by the decoder shown in fig. 1 and 2 will be described.
Fig. 3 shows an exemplary flow of the decoding method, which may include at least the following steps:
s301: and acquiring a received value corresponding to the code word of the BCH code.
The received value may be output from the data demodulator 103 in the satellite navigation receiver to the decoder 104.
More specifically, the received value output by the data demodulator 103 may be received by the hard decision module 201 in fig. 2.
S302: and carrying out hard decision on the received value to obtain a hard decision vector.
The length of the hard decision vector is the same as the total length of the codeword, and in the present invention, is 51. X may be used to represent a hard decision vector.
S302 is performed by the hard decision module 201 in fig. 2.
Specifically, the hard decision module 201 performs hard decision according to each bit in the output codeword of the data demodulator 103 to obtain a hard decision value. The judgment method is to compare each accumulated output value with a set threshold value, if the accumulated output value exceeds the threshold value, the hard judgment value of the corresponding bit is judged to be 1, otherwise, the hard judgment value is judged to be 0.
The above-mentioned decision method is a general hard decision method, which is not described herein again.
In one example, the resulting hard decision values may be stored in the first buffer 202 in sequence to form the hard decision vector x described above.
Any bit in the codeword can be represented as the ith bit, i is not less than 1 and not more than 51. For the ith bit in the code word, performing the following operations to obtain a decoding result:
s303: (i-1) th cycle left shift result X using hard decision vectoriAnd calculating N groups of checksums corresponding to the ith bit.
N is a positive integer. Each of the N sets of checksums includes N sum values, each sum value being obtained by summing at least four hard decision values in the hard decision vector.
In one example, if any group of checksums is represented as a jth group of checksums (j is not less than 1, not more than N), each sum value in the jth group of checksums is represented by X aboveiThe hard decision value of the first bit, the jth bit and other bits in the sequence are added.
Note that, for the BCH (51,8) code, N-16 is the maximum value subjected to greedy search.
The jth group checksum may be expressed as sj,1,sj,2,…,sj,16]If N is 16, the 1 st set of checksums may be represented as s1,1,s1,2,…,s1,16](ii) a The 2 nd set of checksums may be represented as s2,1,s2,2,…,s2,16](ii) a The 3 rd set of checksums may be represented as s3,1,s3,2,…,s3,16]… …, and so on, the 16 th set of checksums may be represented as s16,1,s16,2,…,s16,16]. How to specifically calculate the 16 sets of checksums will be described later herein.
S304: obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsi。
Wherein the decision vector SiLength is also N, where decision vector SiEach bit in (a) may correspond to a set of checksum decisions.
Specifically, if the number of the N sum values of the jth group of checksums, whose value is 1, is greater than N/2, the decision vector S is determinediThe value of the jth bit of (1); otherwise, it is noted as 0.
With N being 16, Si＝[S1,S2,…,S16]For example, after 16 sets of checksums are calculated, S1To S16Can be determined by:
if s1,1,s1,2,…,s1,16In case the number of 1 is greater than 8, S1Is 1, otherwise S1Is 0;
if s2,1,s2,2,…,s2,16In case the number of 1 is greater than 8, S2Is 1, otherwise S2Is 0;
if s3,1,s3,2,…,s3,16In case the number of 1 is greater than 8, S3Is 1, otherwise S3Is 0;
……
if s16,1,s16,2,…,s16,16In case the number of 1 is greater than 8, S16Is 1, otherwise S16Is 0.
Steps S303 and S304 may be performed by the checksum calculation module 203 shown in fig. 2.
S305: according to a decision vector SiCalculating an error value estimate e for the ith biti。
In one exampleIf the decision vector S isiOf the N bits of (1), the number of values of 1 is greater than N/2, the error value is estimated eiThe value of (a) is marked as 1; otherwise, it is noted as 0.
With N being 16, Si＝[S1,S2,…,S16]For example, if S1,S2,…,S16In case the number of 1 is greater than 8, eiIs 1, otherwise eiIs 0.
S306: using eiFor the above XiThe hard decision value of the first bit in the error correction code is corrected to obtain a correction value.
Can convert the above X intoiThe hard decision value of the first bit in (a) is represented as x1Expressing the correction value as yi. The correction value is the decoding result of the ith bit of the code word.
In one example, the formula y may be usedi＝x1+eiCalculating to obtain yi. The "+" in the formula represents a modulo-2 addition operation.
Steps S305 and S306 may be performed by the correction module 204 shown in FIG. 2, correcting the result yiMay be stored in the second cache 205.
It should be noted that i is from 1, and the first bit of the codeword is a hard decision vector used in decoding. After the first bit is decoded, the correction module 204 circularly shifts the hard decision vector stored in the first buffer 202 by 1 bit to the left to obtain X2Returning to S303, repeatedly performing S303-S306 to decode the second bit of the codeword, and then circularly left-shifting the hard decision vector stored in the first cache 202 by 1 bit to obtain X3And returning to S303 to decode the third bit of the code word until 51 bits obtain a decoding result, and forming a decoding vector y ═ y1,y2,…,y51]。
The decoding vector contains an information sequence. In one example, if i is equal to 51, the decoding output module 207 may output the information sequence of the decoding vector stored in the second buffer 205. In another example, if i is equal to 51, the following S307 may be performed.
S307: checking the decoding vector;
in one example, for BCH (51,8) code, the first 8 bits of the 51-bit coded vector are the information sequence. 43 verification results can be calculated according to the information sequence, and the 43 verification results can be expressed as
Figure BDA0001877191490000061
Figure BDA0001877191490000062
If all p is 9,10, …,51, there are
Figure BDA0001877191490000063
The check is successful.
Step S307 may be performed by the verification module 206.
S308: if the check is successful, outputting the information sequence in the decoding vector.
Specifically, if the check is successful, the check module 206 may notify the decoding output module 207 to output the information sequence in the second buffer 206.
Of course, if the check fails, the decoding vector is invalid, and the received navigation message data may be discarded, waiting for the next set or frame of navigation messages to be received.
Fig. 4 shows decoding performance of the decoding method according to the embodiment of the present invention.
Therefore, in the invention, the hard decision vector is used for calculating the checksum of any bit in the code word, the error value of the bit is estimated according to the checksum, and the estimated error value is used for correcting the hard decision value corresponding to the bit in the hard decision vector, so that the decoding of the bit is completed. And repeating the above processes to finish the decoding results of all bits. In the decoding process, all code words of the BCH code do not need to be stored, and all possible information sequences do not need to be coded to obtain corresponding code words, so that the operation is relatively simple, and the decoding complexity is reduced.
In addition, after all bits are decoded, the decoding vector can be checked, if the check is successful, an information sequence in the decoding vector is output, and if the check is failed, the decoding result is invalid.
How to generate 16 sets of checksums and how to generate 43 check results are described below.
Can convert the above X intoiEach hard decision value in (1) is expressed as x1To x51Then, the sum of the 16 checksum sets is calculated using the following formula in table 1:
Figure BDA0001877191490000071
Figure BDA0001877191490000081
Figure BDA0001877191490000091
Figure BDA0001877191490000101
Figure BDA0001877191490000111
Figure BDA0001877191490000121
TABLE 1
And the 43 verification results
Figure BDA0001877191490000122
The following formula in table 2 can be used for calculation:
Figure BDA0001877191490000123
Figure BDA0001877191490000131
TABLE 2
Wherein, the addition sign in all formulas of table 1 and table 2 represents the modulo-2 addition operation.
It can be seen that the operations related to the decoding method provided by the present invention include circular left shift and modulo 2 addition, and these operations are all logical operations, compared with the multiply-accumulate operation in the prior art, the operation is simple, and the decoding complexity of the BCH (51,8) code can be effectively reduced. In addition, the decoding method can detect decoding errors and is a good choice for satellite navigation receivers (especially low-cost satellite navigation receivers) in practice.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is simple, and the description can be referred to the method part.
Those of skill would further appreciate that the various illustrative components and model steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or model described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, WD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A BCH code decoding method for satellite navigation is characterized by comprising the following steps:
acquiring a receiving value corresponding to a code word of the BCH code;
performing hard decision according to the received value to obtain a hard decision vector; the hard decision vector length is the same as the total length of the codeword;
decoding each bit in the code word by using a majority logic decoding principle and the hard decision vector to obtain a decoding vector;
any bit in the code words is represented as the ith bit, i is not less than 1; the decoding each bit in the codeword using a majority logic decoding principle and the hard decision vector to obtain a decoded vector comprises:
(i-1) th cycle left shift result X using the hard decision vectoriCalculating N groups of checksums corresponding to the ith bit; wherein each set of checksums comprises N sum values, each sum value of the N sum values resulting from the addition of at least four hard decision values in the hard decision vector; n is a positive integer;
obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsi(ii) a The decision vector SiThe length is N;
according to the decision vector SiCalculating an error value estimate e for the ith biti；
Using said eiTo the XiAnd correcting the hard decision value of the first bit to obtain a correction value, wherein the correction value is the decoding result of the ith bit.
2. The method of claim 1,
the coding vector comprises an information sequence;
after obtaining the coding vector, the method further comprises:
checking the coding vector; and if the verification is successful, outputting the information sequence in the decoding vector.
3. The method of claim 1,
any one group in the N groups of checksums is expressed as a jth group of checksums; j is not less than 1 and not more than N;
obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsiThe method comprises the following steps:
if the number of the numerical values 1 in the N sum values of the jth group of checksums is greater than N/2, the decision vector S is determinediThe value of the jth bit of (1); otherwise, marking as 0;
according to the decision vector SiCalculating an error value estimate e for the ith bitiThe method comprises the following steps:
if the decision vector SiOf the N bits of (1), the number of values of 1 is greater than N/2, the error value is estimated eiThe value of (a) is marked as 1; otherwise, it is noted as 0.
4. The method of claim 1, wherein X isiThe hard decision value of the first bit in (a) is represented as x1(ii) a Said use of said eiTo the XiCorrecting the hard decision value of the first bit to obtain a correction value, wherein the step of correcting the hard decision value of the first bit comprises the following steps:
using the formula yi＝x1+eiCalculating to obtain a correction value;
wherein, said yiIndicating the correction value, "+" indicates a modulo-2 addition operation.
5. The method of claim 1 or 3,
the total length of the code word is 51 bits; the hard decision vector length is 51 bits; a jth group checksum in the N groups of checksums is represented as [ s ]j,1,sj,2,…,sj,16](ii) a j is not less than 1 and not more than N; said N is 16, said XiEach hard decision value in (1) is expressed as x1To x51；
The sum value of each group of checksums is calculated by the following formula:
Figure FDA0001877191480000021
Figure FDA0001877191480000031
Figure FDA0001877191480000041
Figure FDA0001877191480000051
Figure FDA0001877191480000061
Figure FDA0001877191480000071
wherein the addition sign in all formulas represents a modulo-2 addition operation.
6. The method of claim 2, wherein the total length of the decoded vector is 51 bits, the length of the information sequence is 8 bits, and the information sequence occupies the first 8 bits of the decoded vector; each decoding result in the decoding vector is represented as y1To y51；
The verifying the coding vector comprises:
calculating 43 check results according to the information sequence, wherein the 43 check results are expressed as
Figure FDA0001877191480000072
Figure FDA0001877191480000073
If all p is 9,10, …,51, there are
Figure FDA0001877191480000074
The check is successful.
7. The method of claim 6, wherein the 43 verification results are calculated using the following formula:
Figure FDA0001877191480000075
Figure FDA0001877191480000081
wherein the addition sign in all formulas represents a modulo-2 addition operation.
8. A decoder, comprising:
a hard decision module: the device is used for acquiring a receiving value corresponding to a code word of the BCH code and performing hard decision according to the receiving value to obtain a hard decision vector; the hard decision vector length is the same as the total length of the codeword;
a decoding module: decoding each bit in the codeword by using a majority logic decoding principle and the hard decision vector to obtain a decoded vector;
wherein,
any bit in the code words is represented as the ith bit, i is not less than 1; the decoding each bit in the codeword using a majority logic decoding principle and the hard decision vector to obtain a decoded vector comprises:
(i-1) th cycle left shift result X using the hard decision vectoriCalculating N groups of checksums corresponding to the ith bit; wherein each set of checksums comprises N sum values, each sum value of the N sum values resulting from the addition of at least four hard decision values in the hard decision vector; n is a positive integer;
obtaining a decision vector S corresponding to the ith bit according to the N groups of checksumsi(ii) a The decision vector SiThe length is N;
according to the decision vector SiCalculating an error value estimate e for the ith biti；
Using said eiTo the XiAnd correcting the hard decision value of the first bit to obtain a correction value, wherein the correction value is the decoding result of the ith bit.
9. The decoder of claim 8, wherein the decoded vector includes a sequence of information; the coding module is also to:
checking the coding vector; and if the verification is successful, outputting the information sequence in the decoding vector.
10. A satellite navigation receiver comprising a decoder as claimed in claim 8 or 9.
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