CN102157497A - Multi-layer stacked semiconductor device structure and forming method - Google Patents
Multi-layer stacked semiconductor device structure and forming method Download PDFInfo
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- CN102157497A CN102157497A CN2011100281853A CN201110028185A CN102157497A CN 102157497 A CN102157497 A CN 102157497A CN 2011100281853 A CN2011100281853 A CN 2011100281853A CN 201110028185 A CN201110028185 A CN 201110028185A CN 102157497 A CN102157497 A CN 102157497A
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Abstract
The invention provides a multi-layer stacked semiconductor device structure. The structure comprises a substrate, at least two epitaxial layers and at least three label layers, wherein the substrate is internally provided with identification structures; the epitaxial layers and the three label layers are alternately arranged on the surface of the substrate; and the label layers are made of germanium silicon and cover the epitaxial layers. The structure has the following advantages: a germanium-silicon film layer is added between two adjacent epitaxial layers to serve as a label layer; as the diffusion rate of germanium in silicon is lower, the formed germanium-silicon label layers have clear sections; if the structure is adopted to detect the crystal orientation of the epitaxial layers, the results are more accurate, thus improving the accuracy of photoetching or P implanting positions in the semiconductor process; furthermore, if the method of directly forming the label layers on the surfaces of the epitaxial layers is adopted, the next epitaxial layer can be formed without cleaning the surface of the epitaxial layer; and the forming process of the multi-layer stacked semiconductor device is simple.
Description
Technical field
The present invention relates to semiconductor applications, relate in particular to a kind of structure and formation method of semiconductor device of multilayer storehouse.
Background technology
In order to improve the performance of bipolar device and integrated circuit, usually need be at the one or more epitaxial loayers of silicon base surface deposition.Before the special P body injection process in super knot technology, need on initial epitaxial layer, to put on earlier mark, see through the supreme a plurality of epitaxial loayers of described initial epitaxial layer then and come alignment mark.
And because when making epitaxial loayer, because the monocrystalline silicon in the described epitaxial loayer has epitaxial characteristic, and the crystal orientation of monocrystalline silicon growing is relevant with technology, if technology is correct, monocrystalline silicon will be along correct direction growth so; If technology is incorrect, monocrystalline silicon just can not be along correct crystal orientation growth so.But because the material of each epitaxial loayer is identical, therefore judging whether described epitaxial loayer just has difficulties along correct crystal orientation growth, if and the monocrystalline silicon in the epitaxial loayer is not along correct crystal orientation growth, so for semiconductor device, accurately judge the position of photoetching or judge that accurately the position that the P body injects has difficulties in super knot technology the time with multilayer stack architecture.
Fig. 1 is the position alignment method schematic diagram of the semiconductor device of prior art multilayer storehouse.Please refer to Fig. 1, silicon base 101 is provided, form the initial epitaxial layer 103 that covers described silicon base 101, be formed with marking structure 113 in the described initial epitaxial layer 103, the position alignment when described marking structure 113 is used for photoetching or the injection of P body.Described initial epitaxial layer 103 surfaces are formed with first epitaxial loayer 105, second epitaxial loayer 107, the 3rd epitaxial loayer 109, the 4th epitaxial loayer 111 successively.If described epitaxial loayer 103,105,107,109,111 is not along correct crystal orientation growth, when judging the position of described marking structure 113, will there be error so, please refer to as shown in Figure 1, may occur when judging thinking that described marking structure 113 is positioned at 115 or the situation of other positions.Thereby deviation appears in the position that causes photoetching or P body to inject, and influences the performance of the semiconductor device of described multilayer stack architecture.
Be used to detect the structure of semiconductor device of the multilayer storehouse in crystal orientation in the prior art, usually adopt arsenic doped in each epitaxial loayer, and under certain process conditions, form the method for the mark layer that contains arsenic silicon, judge that whether epitaxial loayer is along correct crystal orientation growth.Yet, because the arsenic in the mark layer spreads easily, being unfavorable for observing the crystal orientation in epitaxial loayer, the position at the actual place of mark is observed in influence, thus the positional precision that causes photoetching or P body to inject is poor.And after arsenic doped forms mark layer, need clean this surface, form next epitaxial loayer again, complex process.
Summary of the invention
The problem that the present invention solves has provided a kind of structure and formation method of semiconductor device of multilayer storehouse, utilizes the semiconductor device of multilayer storehouse of the present invention to detect the crystal orientation, has avoided judging the problem of the accuracy difference of mark position.
For addressing the above problem, the invention provides a kind of structure of semiconductor device of multilayer storehouse, comprising:
Substrate has marking structure in the described substrate;
Be positioned at two-layer at least epitaxial loayer and at least three layers of mark layer of replacing of described substrate surface, and described mark layer is a germanium silicon.
Alternatively, the material of described epitaxial loayer is a silicon.
Alternatively, the content of germanium is 7%～12% in the described mark layer.
The invention provides a kind of formation method of semiconductor device of multilayer storehouse, comprising:
Substrate is provided, is formed with marking structure in the described substrate;
Alternately form two-layer at least epitaxial loayer and at least three layers of mark layer successively at described substrate surface, and described mark layer is a germanium silicon.
Alternatively, the formation technology of described mark layer is that ion injects.
Alternatively, the ion of described ion injection is a germanium ion.
Alternatively, the formation technology of described mark layer is chemical vapour deposition (CVD).
Alternatively, the depositing temperature of described chemical vapor deposition method is 600～800 ℃, and pressure is 2666Pa～5333Pa, and thickness is 40nm～80nm, and the retention time is 40～60s.
Alternatively, the content of germanium is 7%～12% in the described mark layer.
Alternatively, the described formation technology of cutting described semiconductor device open is chemical etching.
Compared with prior art, the present invention has the following advantages:
The invention provides a kind of structure and formation method of semiconductor device of multilayer storehouse, between adjacent two epitaxial loayers, increase one deck germanium-silicon thin membrane layer that serves as a mark, because the diffusion rate of germanium in silicon is less, therefore formed mark layer germanium silicon has cross section clearly, adopt the structure of the semiconductor device of multilayer storehouse of the present invention to detect the crystal orientation of epitaxial loayer, the result is more accurate, has improved the positional precision that photoetching in the semiconductor technology or P body inject.
Further, if the present invention adopts the method that directly forms mark layer in described epi-layer surface, then need not this surface is cleaned, can form next epitaxial loayer, the formation technology of the semiconductor device of described multilayer storehouse is simple.
Description of drawings
Fig. 1 is the position alignment method of the semiconductor device of prior art multilayer storehouse;
Fig. 2 is the cross-sectional view of semiconductor device of the multilayer storehouse of one embodiment of the invention;
Fig. 3 is the schematic flow sheet of formation method of semiconductor device of the multilayer storehouse of one embodiment of the invention;
Fig. 4～Fig. 5 is the cross-sectional view of formation method of the semiconductor device of multilayer storehouse in one embodiment of the invention;
Fig. 6 is the cross-sectional view of the semiconductor device of multilayer storehouse in one embodiment of the invention;
Fig. 7 is the microstructure schematic diagram of the semiconductor device of multilayer storehouse in one embodiment of the invention;
Fig. 8 is the cross-sectional view of the semiconductor device of multilayer storehouse in another embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, the semiconductor device of the multilayer storehouse of prior art is for adopting arsenic doped formation arsenic silicon thin film in described epitaxial loayer layer that serves as a mark, because the diffusion rate of arsenic in silicon is higher, therefore the profile of the mark layer that forms is not clearly, it is not high to adopt the semiconductor device of this kind multilayer storehouse to detect the accuracy in crystal orientation, and complex process, this kind method existing problems.
At the problems referred to above, the present inventor finds after deliberation, the diffusion rate of germanium in silicon is less, can adopt the germanium-silicon thin membrane substitute for arsenic silicon thin film layer that serves as a mark to make the semiconductor device of multilayer storehouse, the clear-cut of described mark layer, it is more accurate to be with described mark layer that the semiconductor device of the multilayer storehouse of germanium-silicon thin membrane detects the crystal orientation, and the formation technology of the semiconductor device of described multilayer storehouse is simple.
The invention provides a kind of structure of semiconductor device of multilayer storehouse, comprising:
Substrate has marking structure in the described substrate;
Be positioned at two-layer at least epitaxial loayer and at least three layers of mark layer of replacing of described substrate surface, it is characterized in that described mark layer is a germanium silicon.
Wherein, the material of described epitaxial loayer is a silicon; The content of germanium is 7%～12% in the described mark layer.
In the specific embodiment of the invention, described epitaxial loayer is preferably three layers, and described mark layer is preferably three layers.
Fig. 2 is the profile of semiconductor device of the multilayer storehouse of the specific embodiment of the invention.Please refer to Fig. 2, the structure of the semiconductor device of the multilayer storehouse of the specific embodiment of the invention comprises:
Be positioned at first epitaxial loayer 203 on described substrate 201 surfaces;
Be positioned at first mark layer 205 on described first epitaxial loayer 203 surfaces;
Be positioned at second epitaxial loayer 207 on described first mark layer 205 surfaces;
Be positioned at second mark layer 209 on described second epitaxial loayer 207 surfaces;
Be positioned at the 3rd epitaxial loayer 211 on described second mark layer 209 surfaces;
Be positioned at the 3rd mark layer 213 on described the 3rd epitaxial loayer 211 surfaces.
Wherein, described substrate 201 comprises substrate 21 and initial epitaxial layer 22, and described mark structure 20 is positioned at initial epitaxial layer 22.
The material of described first mark layer 205, second mark layer 209, the 3rd mark layer 213 is a germanium-silicon thin membrane, and the content of germanium is 7%～12% in the described germanium-silicon thin membrane.
The material of described first epitaxial loayer 203, second epitaxial loayer 207, the 3rd epitaxial loayer 211 is a silicon.
The invention provides a kind of formation method of semiconductor device of layer stack, comprising:
Substrate is provided, is formed with marking structure in the described substrate;
Alternately form two-layer at least epitaxial loayer and at least three layers of mark layer successively at described substrate surface, and described mark layer is a germanium silicon.
Wherein, described substrate comprises substrate and initial epitaxial layer, and described marking structure is formed in the initial epitaxial layer.
The formation technology of described mark layer is that ion injects, and the ion that described ion injects is a germanium ion; Perhaps the formation technology of described mark layer is chemical vapour deposition (CVD), and the depositing temperature of described chemical vapor deposition method is 600～800 ℃, and pressure is 2666Pa～5333Pa, and thickness is 40nm～80nm, and the retention time is 40～60s.
And the most clear for the profile that makes described mark layer, the content of germanium is 7%～12% in the described mark layer.
Fig. 3 is the flow chart of formation method of semiconductor device of the multilayer storehouse of the specific embodiment of the invention.Please refer to Fig. 3, the formation method of the semiconductor device of multilayer storehouse of the present invention comprises:
Step S31 provides substrate, is formed with marking structure in the described substrate;
Step S32 forms first epitaxial loayer that covers described substrate;
Step S33 forms first mark layer that covers described first epitaxial loayer, and described first mark layer is a germanium silicon;
Step S34 forms second epitaxial loayer that covers described first mark layer;
Step S35 forms second mark layer that covers described second epitaxial loayer, and described second mark layer is a germanium silicon;
Step S36 forms the 3rd epitaxial loayer that covers described second mark layer;
Step S37 forms the 3rd mark layer that covers described the 3rd epitaxial loayer, and described the 3rd mark layer is a germanium silicon.
After execution of step S31～S37, the semiconductor device of multilayer storehouse of the present invention completes.
Fig. 4 to Fig. 5 shows the schematic diagram of formation method of the semiconductor device of multilayer storehouse in the specific embodiment of the invention.
Please refer to Fig. 4, execution in step S31 provides substrate 301, is formed with marking structure 30 in the described substrate 301.
In the specific embodiment of the invention, described substrate 301 comprises substrate 31 and initial epitaxial layer 32, and described marking structure 30 is formed in the initial epitaxial layer 32.
The material of described substrate 31 is a monocrystalline silicon.Can doped N-type or p type impurity in the described substrate 31, to satisfy actual industrial requirement.In the specific embodiment of the invention, be doped with N type impurity in the described substrate 31, for example: pentads such as P, As, Sb.
The material of described initial epitaxial layer 32 is a silicon, and the formation method of described initial epitaxial layer 32 is chemical vapour deposition (CVD).Adopt the method for etching to form marking structure 30 in initial epitaxial layer 32, described marking structure 30 is used for the crystal orientation of follow-up semiconductor technology and detects, and perhaps is used for alignment mark is carried out in the position of photoetching or the injection of P body.
Please refer to Fig. 5, execution in step S32～step S37.Specific as follows:
After described substrate was provided, execution in step S32 formed first epitaxial loayer 303 that covers described substrate.
The material of described first epitaxial loayer 303 is a silicon, the formation method of described first epitaxial loayer 303 is chemical vapour deposition (CVD) (chemical vapor deposition, CVD), because it is consistent with existing epitaxial loayer formation technology to form the technology of described first epitaxial loayer 303, give unnecessary details no longer one by one at this.
In the present embodiment, in order to save time, the thickness of described first epitaxial loayer 303 is preferably 4～8 μ m.
Need to prove, after described first epitaxial loayer 303 is carried out, if be placed in the air for a long time, and do not carry out next step technology, silicon in so described first epitaxial loayer 303 will be oxidized, perhaps airborne dust will drop on the surface of described first epitaxial loayer 303, influences its cleaning, and this will exert an adverse impact to next step operation.Therefore, form the time difference of described first epitaxial loayer 303 and formation first mark layer 305 less than two hours.
Afterwards, execution in step S33 forms first mark layer 305 that covers described first epitaxial loayer, and described first mark layer 305 is a germanium silicon.
Described first mark layer 305 is the germanium-silicon thin membrane of 40nm～80nm for thickness, and the formation method of described germanium-silicon thin membrane has two kinds:
A kind of is doped germanium in described first epitaxial loayer 303, and germanium combines with silicon in described first epitaxial loayer 303 and forms germanium silicon, forms described first mark layer 305.Have after first mark layer 305 of germanium silicon if form, need clean, could form second epitaxial loayer 309 described first mark layer 305 surfaces with this kind method doped germanium in described first epitaxial loayer 303.
Another kind is the method that adopts chemical vapor deposition (CVD), forms first mark layer 305 with germanium silicon on described first epitaxial loayer 303 surfaces.This kind method need not first mark layer 305 is cleaned, and can carry out subsequent technique, and it is simple to form technology.
In specific embodiments of the invention, for making first mark layer more clear, and it is simpler to form technology, preferably adopts second method, and promptly the method for chemical vapor deposition (CVD) forms described first mark layer 305.
When forming described first mark layer 305, the concrete parametric optimization of described chemical vapor deposition (CVD) is: depositing temperature is 600～800 ℃, and pressure is 2666Pa～5333Pa, and thickness is 40nm～80nm, and the retention time is 40～60s.
And the most clear for the mark layer that germanium-silicon thin membrane is formed, the content of germanium is preferably 7%～12% in described first mark layer.
Then, execution in step S34 forms second epitaxial loayer 307 that covers described first mark layer 305.
The material of described second epitaxial loayer 307 is a silicon, and the formation method of described second epitaxial loayer 307 is chemical vapour deposition (CVD); The thickness of described second epitaxial loayer 307 is preferably 4～8 μ m; The time difference that forms described second epitaxial loayer 307 and formation second mark layer 309 was less than two hours.Specifically please refer to the formation method of described first epitaxial loayer 303.
Then, execution in step S35 forms second mark layer 309 that covers described second epitaxial loayer 307, and described second mark layer 309 is a germanium silicon.
The formation method of described second mark layer 309 is that ion injects or chemical vapour deposition (CVD); The content of germanium is preferably 7%～12% in described second mark layer 309.The formation method of described second mark layer 309 and parameter please refer to first mark layer 305.
Then, execution in step S36 forms the 3rd epitaxial loayer 311 that covers described second mark layer 309.
The material of described the 3rd epitaxial loayer 311 is a silicon, and the formation method of described the 3rd epitaxial loayer 311 is chemical vapour deposition (CVD); The thickness of described the 3rd epitaxial loayer 311 is preferably 4～8 μ m; The time difference that forms described the 3rd epitaxial loayer 311 and formation second mark layer 309 was less than two hours.Specifically please refer to the formation method of described first epitaxial loayer 303.
At last, execution in step S37 forms the 3rd mark layer 313 that covers described the 3rd epitaxial loayer 311, and described the 3rd mark layer 313 is a germanium silicon.
The formation method of described the 3rd mark layer 313 is that ion injects or chemical vapour deposition (CVD); The content of germanium is preferably 7%～12% in described the 3rd mark layer 313.The formation method of described the 3rd mark layer 313 and parameter please refer to first mark layer 305.After forming first epitaxial loayer 303, second epitaxial loayer 307, the 3rd epitaxial loayer 311 and first mark layer 305, second mark layer 309, second mark layer, the 313 mutual structures that overlap, described semiconductor device with multilayer stack architecture completes.
Adopt the semiconductor device of the multilayer stack architecture of making in the specific embodiment of the invention to detect the crystal orientation, concrete grammar is seen Fig. 6 to Fig. 7.
Please refer to Fig. 6, after the semiconductor device structure with multilayer storehouse of the specific embodiment of the invention completes, along cutting the semiconductor device of described multilayer storehouse open perpendicular to the direction of described semiconductor device substrates, the sub-cross section group 405,409,413 that the cross section 400 of described semiconductor device is had expose in the described semiconductor layer and the cross section 50 of marking structure.
In specific embodiments of the invention, the formation technology of cutting described semiconductor device open is chemical etching.Described chemical etching adopts H
2O
2And HF.H
2O
2Be used for the described semiconductor device of oxidation place to be etched, generate oxide skin(coating) (not shown), HF is used to remove described oxide skin(coating).Be specially: H
2O
2With the described semiconductor device of speed oxidation faster, generate oxide skin(coating), afterwards, described oxide skin(coating) is removed in HF and the reaction of described oxide skin(coating).For making the semiconductor device cross section quality of cutting open good, described H
2O
2Be preferably 1: 50 with the ratio of HF～1: 70.
Described sub-cross section group 405,409,413 is the cross section of multilayer mark layer (not shown).
Because adopt the method for chemical etching to cut described semiconductor device open, HF removes the oxide skin(coating) in the cross section of described semiconductor device, therefore, after described semiconductor device is cut open, can directly observe down in scanning electron microscopy (SEM).Be specially: the cross section 400 of described semiconductor device is amplified to the enlargement ratio that is suitable for observing sub-cross section group 405,409,413, observes the contour shape of described sub-cross section group 405,409,413.
Need to prove that because substrate 501 interior etchings are formed with the cross section 50 of marking structure, therefore when follow-up formation epitaxial loayer and mark layer, the surface of described epitaxial loayer and mark layer is not smooth fully, but has the zone of depression.The zone of this depression is difficult for observing under macroscopic conditions, just can observe when only being amplified to suitable multiplying power under scanning electron microscopy.
Please refer to Fig. 7, Fig. 7 is the schematic diagram of the present invention under scanning electron microscopy (SEM).
Under scanning electron microscopy, there is the zone of caving in observed sub-cross section group with the corresponding position of described mark layer, choose the minimum point in the zone of described depression, and will be positioned at different layers and belong to one group perpendicular to those minimum points of the vicinity of the straight line on substrate 51 surfaces according to mark layer.
Whether more described every group minimum point is positioned on the straight line, and judges on this basis whether the semiconductor device that forms under these process conditions is accurately aimed at when follow-up photoetching or the injection of P body easily.Be specially: if every group minimum point is positioned on the straight line in the group 505,509,513 of described sub-cross section, then represent epitaxial loayer 503,507,511 along identical crystal orientation growth, the semiconductor device that forms under these process conditions is easier to accurate aligning in follow-up photoetching or P body injection time ratio so; If the minimum point of every group of relevant position is not positioned on the straight line in the group 505,509,513 of described sub-cross section, then represent epitaxial loayer 503,507,511 along the growth of different crystal orientation, when follow-up photoetching or P body inject, be not easy accurate aligning at the semiconductor device that forms under these process conditions so.
In the present embodiment, preferred and marking structure 50a and the corresponding two groups of minimum points of marking structure 50b compare in the sub-cross section of described semiconductor device group 505,509,513.
In specific embodiments of the invention, the concrete grammar whether more described minimum point is arranged on the straight line is: two groups of minimum point A1, B1, C1 and the A2, B2, the C2 that choose described sub-cross section group 505,509,513, whether observe minimum point A1, B1, C1 and A2, B2, C2 lays respectively on the straight line 515,517, for ease of observing and understanding, there is shown straight line 515,517.If minimum point A1, B1, C1 and A2, B2, C2 lay respectively on the straight line 515,517, then represent described epitaxial loayer 503,507,511 along identical crystal orientation growth, the semiconductor device that forms under these process conditions is easier to accurate aligning in follow-up photoetching or P body injection time ratio so; If minimum point A1, B1, C1 and A2, B2, C2 all are not positioned on the straight line 515,517, then represent described epitaxial loayer 503,507,511 along the growth of different crystal orientation, when follow-up photoetching or P body inject, be not easy accurate aligning at the semiconductor device that forms under these process conditions so; If minimum point A1, B1, C1 are positioned on the straight line 515, and A2, B2, C2 are not positioned on the straight line 517, and the minimum point that then needs to introduce other groups again compares.
In the present embodiment, the technology under preferred described straight line 515,517 and the substrate 501 vertical conditions is being carried out the positional precision height that photoetching or P body inject in the semiconductor device with multilayer stack architecture that forms under this technology, and technology is simple.
Need to prove that judge that the semiconductor device that forms under these process conditions when follow-up photoetching or the injection of P body than the condition that is easier to accurate aligning is: the selected minimum point of at least two groups is positioned on the straight line.
After said process was carried out and finished, the detection in the crystal orientation of the semiconductor device of multilayer storehouse was finished.
In another embodiment of the present invention, alternately be formed with three layers of mark layer and two-layer epitaxial loayer at substrate surface.As shown in Figure 8, be formed with first mark layer 603, first epitaxial loayer 605, second mark layer 607, second epitaxial loayer 609 and the 3rd mark layer 611 successively on described substrate 601 surfaces.
Wherein said substrate 601 comprises substrate 61 and initial epitaxial layer 62, and described marking structure 60 is formed in the initial epitaxial layer 62.
The material of described first mark layer 603, second mark layer 607, the 3rd mark layer 611 is a germanium silicon, and specifically formation method is that ion injects or chemical vapour deposition (CVD); The content of germanium is preferably 7%～12% in described first, second, third mark layer 603,607,611.
The material of described first epitaxial loayer 605, second epitaxial loayer 609 is a silicon, and specifically formation method is chemical vapour deposition (CVD); The thickness of described first, second epitaxial loayer 605,609 is preferably 4～8 μ m; The time difference of described first epitaxial loayer 605 and formation second mark layer 607, the time difference of described second epitaxial loayer 609 and formation the 3rd mark layer 611 was less than two hours less than two hours.
Adopt the semiconductor device of the multilayer stack architecture of this embodiment to detect the crystal orientation, can judge also whether the semiconductor device that forms under these process conditions is accurately aimed at easily when follow-up photoetching or the injection of P body, concrete grammar please refer to an embodiment, gives unnecessary details no longer one by one at this.
In sum, the invention provides a kind of structure and forming method thereof of semiconductor device of multilayer storehouse, increase one deck germanium-silicon thin membrane layer that serves as a mark between adjacent two epitaxial loayers, because the diffusion rate of germanium in silicon layer is less, so the mark layer among the present invention has interface clearly.Adopt the structure of the semiconductor device of multilayer storehouse of the present invention to detect the crystal orientation of epitaxial loayer, the result is more accurate, has improved the positional precision that photoetching in the semiconductor technology or P body inject.
If the present invention adopts the method that directly forms mark layer in described epi-layer surface, then need not this surface is cleaned, can form next epitaxial loayer, the formation method technology of the semiconductor device of described multilayer storehouse is simple.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the structure of the semiconductor device of a multilayer storehouse comprises:
Substrate has marking structure in the described substrate;
Be positioned at two-layer at least epitaxial loayer and at least three layers of mark layer of replacing of described substrate surface, it is characterized in that described mark layer is a germanium silicon.
2. the structure of the semiconductor device of multilayer storehouse as claimed in claim 1 is characterized in that, the material of described epitaxial loayer is a silicon.
3. the structure of the semiconductor device of multilayer storehouse as claimed in claim 1 is characterized in that, the content of germanium is 7%～12% in the described mark layer.
4. the formation method of the semiconductor device of a multilayer storehouse comprises:
Substrate is provided, is formed with marking structure in the described substrate;
Alternately form two-layer at least epitaxial loayer and at least three layers of mark layer successively at described substrate surface, it is characterized in that described mark layer is a germanium silicon.
5. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 4 is characterized in that, the formation technology of described mark layer is that ion injects.
6. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 5 is characterized in that, the ion that described ion injects is a germanium ion.
7. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 4 is characterized in that, the formation technology of described mark layer is chemical vapour deposition (CVD).
8. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 7, it is characterized in that the depositing temperature of described chemical vapor deposition method is 600～800 ℃, pressure is 2666Pa～5333Pa, thickness is 40nm～80nm, and the retention time is 40～60s.
9. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 4 is characterized in that, the content of germanium is 7%～12% in the described mark layer.
10. the formation method of the semiconductor device of multilayer storehouse as claimed in claim 4 is characterized in that, also comprises cutting described semiconductor device open, and the described technology of cutting described semiconductor device open is chemical etching.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975024A2 (en) * | 1998-07-24 | 2000-01-26 | Fuji Electric Co. Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
| CN1281257A (en) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | Semiconductor device |
| CN1645562A (en) * | 2004-01-21 | 2005-07-27 | 精工爱普生株式会社 | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| JP2007142436A (en) * | 2005-11-22 | 2007-06-07 | Samsung Electronics Co Ltd | Semiconductor device comprising lineup mark film and method of manufacturing same |
| US7508531B1 (en) * | 2004-03-29 | 2009-03-24 | National Semiconductor Corporation | System and method for measuring germanium concentration for manufacturing control of BiCMOS films |
-
2011
- 2011-01-26 CN CN201110028185.3A patent/CN102157497B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0975024A2 (en) * | 1998-07-24 | 2000-01-26 | Fuji Electric Co. Ltd. | Semiconductor device with alternating conductivity type layer and method of manufacturing the same |
| CN1281257A (en) * | 1999-06-28 | 2001-01-24 | 株式会社东芝 | Semiconductor device |
| CN1645562A (en) * | 2004-01-21 | 2005-07-27 | 精工爱普生株式会社 | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| US7508531B1 (en) * | 2004-03-29 | 2009-03-24 | National Semiconductor Corporation | System and method for measuring germanium concentration for manufacturing control of BiCMOS films |
| JP2007142436A (en) * | 2005-11-22 | 2007-06-07 | Samsung Electronics Co Ltd | Semiconductor device comprising lineup mark film and method of manufacturing same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102891135A (en) * | 2012-10-17 | 2013-01-23 | 上海宏力半导体制造有限公司 | Semiconductor device and formation method thereof |
| CN102891135B (en) * | 2012-10-17 | 2017-02-22 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and formation method thereof |
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