CN102148146B

CN102148146B - Formation method for grid structure

Info

Publication number: CN102148146B
Application number: CN201010111195.9A
Authority: CN
Inventors: 任晓辉; 奚裴; 齐龙茵
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2010-02-10
Filing date: 2010-02-10
Publication date: 2015-06-17
Anticipated expiration: 2030-02-10
Also published as: CN102148146A

Abstract

The invention relates to a formation method for a grid structure, which comprises the following steps: providing a substrate on which a grid dielectric layer, a polycrystalline silicon layer, a first metal layer, a metal nitride layer, a second metal layer and a hard masking film layer are formed; sequentially forming a bottom anti-reflection layer and a photoresist pattern on the surface of the hard masking film layer, wherein the photoresist pattern corresponds to the grid structure; taking the photoresist pattern as a masking film to sequentially etch the bottom anti-reflection layer and the hard masking film layer till the second metal layer is exposed; taking the etched hard masking film layer as the masking film, and adopting Cl2, NF3, O2 as etching gas, wherein the volume ratio of Cl2 and NF3 is less than 2, and sequentially etching the second metal layer, the metal nitride layer and the first metal layer till the polycrystalline silicon layer is exposed. No etched pits and impurities are left on the surface of the grid structure formed by the formation method.

Description

Formation method for grid structure

Technical field

The present invention relates to field of semiconductor manufacture, particularly formation method for grid structure.

Background technology

At present, very lagre scale integrated circuit (VLSIC) (VLSI) has developed into every monolithic and has had 100, the integrated level of more than 000 element, to this circuit except the circuit design that will look for novelty, new device architecture and technique etc., also must reduce the physical dimension of device further.

Along with the reduction of set size, be commonly used to occur series of problems as the Al of low-resistance grid and polysilicon, such as Al, the infiltration of Al easily in silicon, thus occur permeating due to Al the short circuit phenomenon caused; For polysilicon, its resistivity is higher by (about 10 ³Ω cm), when live width narrows down to 1 micron, its time constant RC is comparatively large, can affect the speed of circuit.

In order to address this problem, low-resistance grid formation process has become one of key manufacturing technology of recent ultrahigh speed CMOS logic large scale integrated circuit, is to find more relevant informations about grid formation process in the Chinese patent application of CN1937177 at such as publication number.

Existing formation grid structure technique generally includes following steps, described in reference diagram 1:

Step S101, forms gate dielectric layer at substrate surface;

Step S102, forms polysilicon layer, metal silicide layer and hard mask layer successively on described gate dielectric layer surface;

Step S103, forms the photoetching offset plate figure corresponding with grid structure on described hard mask layer surface, with described photoetching offset plate figure for mask, etches hard mask layer, metal silicide layer and polysilicon layer successively, form grid structure.

Above-mentioned etching technics can adopt containing CF usually at etching metal silicide layer ₄, Cl and He plasma etching, plasma etching is crossed and by force can be produced damage to polysilicon layer at etching metal silicide layer and penetrate gate dielectric layer through next step technique and form pit (Pits) on its surface, and the more weak meeting of plasma etching forms some impurity at polysilicon layer finally forms dielectric layer surface impurities left, the grid structure reliability adopting above-mentioned plasma etch process to be formed is low.

Summary of the invention

The problem that the present invention solves is to provide the high etching technics of a kind of reliability and forms grid structure.

For solving the problem, the invention provides a kind of formation method for grid structure, comprising: the substrate being formed with gate dielectric layer, polysilicon layer, the first metal layer, metal nitride layer, the second metal level, hard mask layer is successively provided; Form bottom anti-reflection layer and photoetching offset plate figure successively on described hard mask layer surface, described photoetching offset plate figure is corresponding with grid structure; With described photoetching offset plate figure for mask, etching bottom anti-reflecting layer, hard mask layer successively, until expose the second metal level; With the hard mask layer after etching for mask, adopt and select Cl ₂, NF ₃, O ₂as etching gas, wherein Cl ₂with NF ₃volume ratio be less than 2, etch the second metal level, metal nitride layer and the first metal layer successively, until expose polysilicon layer.

Compared with prior art, the present invention has the following advantages: the grid structure surface that the present invention is formed without pit and gate dielectric layer smooth surface, without obvious plasma pit and impurities left.

Accompanying drawing explanation

By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.Deliberately do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on purport of the present invention is shown.

Fig. 1 is existing formation grid structure schematic flow sheet;

Fig. 2 is the flow chart of formation method for grid structure of the present invention;

Fig. 3 to Fig. 7 is the schematic diagram of formation method for grid structure of the present invention;

Fig. 8 is the SEM picture of the grid structure adopting the present invention to be formed.

Embodiment

The formation process of existing grid structure can etch by using plasma, and plasma etching is crossed and can be formed pit (Pits) to polysilicon layer generation damage is final on gate dielectric layer surface at etching metal silicide layer by force, cause grid structure to lose efficacy; And the more weak meeting of plasma etching forms some impurity at polysilicon layer finally forms dielectric layer surface impurities left and make grid structure hydraulic performance decline.Formation process for above-mentioned grid structure forms defect, and those skilled in the art can be optimized by regulating parameter such as etching power and etch period etc. usually, but owing to containing CF ₄plasma etching to be more difficultly optimized by above-mentioned optimization method, large or the etch period length of etching power can form pit, and etch the little or short impurities left that can be formed of etch period of power, for this reason, the present inventor, through creative work, proposes a kind of formation process of grid structure of improvement.

Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.

Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.

Fig. 2 is the flow chart of formation method for grid structure of the present invention; Fig. 3 to Fig. 7 is the schematic diagram of formation method for grid structure of the present invention, is described in detail to one embodiment of the invention below in conjunction with Fig. 3 to Fig. 7, and it comprises the following steps:

Step S101, provides the substrate being formed with gate dielectric layer, polysilicon layer, the first metal layer, metal nitride layer, the second metal level, hard mask layer successively.

Please refer to Fig. 3, substrate 100 is provided, described substrate 100 is formed with successively gate dielectric layer 110, polysilicon layer 120, the first metal layer 130, metal nitride layer 140, second metal level 150 and hard mask layer 160.

Concrete, described substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described substrate 100 also can be silicon, germanium, GaAs or silicon Germanium compound; This substrate 100 can also have epitaxial loayer or insulating barrier silicon-on; Described substrate 100 can also be other semi-conducting material.

Described gate dielectric layer 110 material is silica, the thickness of described gate dielectric layer 110 is 10 dust to 200 dusts, the formation method of described gate dielectric layer 110 can be grid oxide layer formation method well known in the art, such as: the silicon on dry oxidation substrate 100 surface forms gate dielectric layer 110 or chemical vapor deposition silica forms gate dielectric layer 110.

The thickness of described polysilicon layer 120 is 400 dust to 3000 dusts, the formation method of described polysilicon layer 120 can be chemical vapour deposition technique, described polysilicon layer 120 can have good adhesiveness with gate dielectric layer 110, and the formation process of described polysilicon layer 120 is chemical vapor deposition method.

The first metal layer 130, metal nitride layer 140 and the second metal level 150 form metal silicide layer for follow-up to react with polysilicon 120.

Wherein, the first metal layer 130 material is titanium, thickness is 35 dust to 45 dusts, and described the first metal layer 130 is for improving the second follow-up metal level and the adhesiveness of polysilicon layer 120, and the formation process of described the first metal layer 130 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).

Metal nitride layer 140 material is selected from tungsten nitride, thickness is 20 dust to 30 dusts, described metal nitride layer 140 is for improving the stress of the second metal level and polysilicon layer 120, and the formation process of described metal nitride layer 140 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).

Second metal level 150 material is selected from tungsten, and thickness is 350 dust to 450 dusts, and described second metal level 150 is for subsequent technique metal silicide layer, and the formation process of described second metal level 150 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).

Described hard mask layer 160 thickness is 500 dust to 3000 dusts, and described hard mask layer 140 material is silicon nitride or fire sand, and the formation process of described hard mask layer 160 can be existing chemical vapour deposition (CVD).

Step S102, form bottom anti-reflection layer and photoetching offset plate figure successively on described hard mask layer surface, described photoetching offset plate figure is corresponding with grid structure.

With reference to figure 4, bottom anti-reflection layer 170 and photoetching offset plate figure 180 is formed successively on described hard mask layer surface, described bottom anti-reflection layer 170 material is the compound of carbon containing hydrogen-oxygen, described bottom anti-reflection layer 170 is for improving the precision of photoetching, prevent light by reflecting after photoresist, the technique forming bottom anti-reflection layer 170 can be spin coating proceeding.

The forming step of described photoetching offset plate figure 180 comprises: at the surperficial spin coating photoresist of bottom anti-reflection layer 170, then will mask plate transfer on photoresist with grid structure graph of a correspondence by exposure, then developer solution is utilized to be removed by the photoresist of corresponding site, to form photoetching offset plate figure 180.

Step S103, with described photoetching offset plate figure for mask, etching bottom anti-reflecting layer, hard mask layer successively, until expose the second metal level.

With reference to figure 5, described etching technics can select plasma etch process, it needs to be noted in the technique of etching bottom anti-reflecting layer 170 and hard mask layer 160, described photoetching offset plate figure 180 and bottom anti-reflection layer 170 also can be consumed a part and consume even completely, form the hard mask layer 160 after etching, as the mask of subsequent etching processes, if be not completely consumed, then described photoetching offset plate figure 180 and bottom anti-reflection layer 170 together with the hard mask layer 160 after etching as mask.

Step S104, with the hard mask layer after etching for mask, etches the second metal level, metal nitride layer and the first metal layer, successively until expose polysilicon layer.

With reference to figure 6, inventor finds in great many of experiments, and existing etching technics can produce damage to polysilicon layer at etching first metal layer, or forms some impurities left at polysilicon layer, and this is owing to containing CF ₄plasma etching more difficult by regulating the etching parameter optimization method such as power and etch period to be optimized.

For this reason, when etching second metal level 150, metal nitride layer 140 and the first metal layer 130, the present inventor proposes a kind of etching technics of optimization, selects Cl ₂, NF ₃, O ₂as etching gas, wherein Cl ₂with NF ₃volume ratio be less than 2, and not containing He in described etching technics.

The etching technics of above-mentioned optimization is adopted to etch the second metal level 150, metal nitride layer 140 and the first metal layer 130, because Cl ₂with NF ₃volume ratio be less than 2, can not to polysilicon layer produce damage; And do not avoid forming some impurities left at polysilicon layer containing He in etching technics, therefore above-mentioned optimization etching technics has larger etching technics window.

Do exemplary illustrated with a specific embodiment below, the concrete etching technics etching the second metal level, metal nitride layer and the first metal layer is: etching power is 300 watts, Cl ₂flow is 200SCCM, NF ₃flow is 500SCCM, O ₂flow be 50SCCM, adopt above-mentioned etching condition, etch the second metal level, metal nitride layer and the first metal layer, until expose polysilicon layer.

Step S105, with the hard mask layer after etching for mask, etches polycrystalline silicon layer and gate dielectric layer, until expose substrate.

With reference to figure 7, the etching technics of described etches polycrystalline silicon layer and gate dielectric layer with reference to existing polysilicon layer and gate dielectric layer plasma etch process, here can not repeat.

In order to further illustrate effect of the present invention, adopting and selecting Cl ₂, NF ₃and O ₂as etching gas, wherein Cl ₂with NF ₃volume ratio be less than 2, and the etching condition not containing He in described etching technics performs step S104, and sem analysis is done to the sample after having etched, Fig. 7 is the partial schematic diagram of sample, can find from Fig. 8, adopt the sample gate dielectric layer surface of the present invention's formation without pit and smooth surface, without obvious plasma damage and impurities left.

Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a formation method for grid structure, is characterized in that, comprising:

There is provided the substrate being formed with gate dielectric layer, polysilicon layer, the first metal layer, metal nitride layer, the second metal level, hard mask layer successively, wherein the first metal layer material is titanium, and metal nitride layer material is tungsten nitride, and the second metal layer material is tungsten;

Form bottom anti-reflection layer and photoetching offset plate figure successively on described hard mask layer surface, described photoetching offset plate figure is corresponding with grid structure;

With described photoetching offset plate figure for mask, etching bottom anti-reflecting layer, hard mask layer successively, until expose the second metal level;

With the hard mask layer after etching for mask, etching power is adopted to be 300 watts, Cl ₂flow is 200SCCM, NF ₃flow is 500SCCM, O ₂flow be the etching technics of 50SCCM, etch the second metal level, metal nitride layer and the first metal layer successively, until expose polysilicon layer, with avoid gate dielectric layer surface formed pit.

2. formation method for grid structure as claimed in claim 1, is characterized in that, also comprise: with the hard mask layer after etching for mask, etches polycrystalline silicon layer and gate dielectric layer, until expose substrate.

3. formation method for grid structure as claimed in claim 1, it is characterized in that, described bottom anti-reflection layer is the compound of carbon containing hydrogen-oxygen.

4. formation method for grid structure as claimed in claim 1, it is characterized in that, described the first metal layer thickness is 35 dust to 45 dusts.

5. formation method for grid structure as claimed in claim 1, it is characterized in that, metal nitride layer thickness is 20 dust to 30 dusts.

6. formation method for grid structure as claimed in claim 1, it is characterized in that, the second metal layer thickness is 350 dust to 450 dusts.