CN102142423B - Circuit substrate and package of light emitting diode - Google Patents
Circuit substrate and package of light emitting diode Download PDFInfo
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- CN102142423B CN102142423B CN201110038898.8A CN201110038898A CN102142423B CN 102142423 B CN102142423 B CN 102142423B CN 201110038898 A CN201110038898 A CN 201110038898A CN 102142423 B CN102142423 B CN 102142423B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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Abstract
The invention relates to a package of a light emitting diode, which comprises a carrying device, a chip of the light emitting diode, and packaging colloid, wherein the carrying device comprises a carrying plate, a first electrode, a first pin, a second electrode and a second pin; the first electrode, the first pin, the second electrode and the second pin are all arranged on the carrying plate, and the carrying plate is provided with two counter bores to expose the first electrode and the second electrode respectively; the first pin is connected with the edge of the first electrode; the second pin is connected with the edge of the second electrode; the chip of the light emitting diode is arranged on the first pin, and is electrically connected with the first pin and the second pin; and the packaging colloid is arranged on the carrying plate, and covers the first pin, the second pin and the chip of the light emitting diode, the packaging colloid is provided with two counter bores to expose the first electrode and the second electrode respectively, both the first electrode and the second electrode have two cutting edges which are adjacent to each other and located at corners, and the two cutting edges are not in parallel to each other.
Description
This case is that application number is dividing an application of 200810100702.1 cases.
Technical field
The invention relates to a kind of circuit base plate and LED package, and particularly relevant for the lower circuit base plate of a kind of cost of manufacture and LED package.
Background technology
Compared to conventional bulb, light-emitting diode has that volume is little, life-span length, power saving, without characteristics such as mercury pollutions.Therefore,, along with the luminous efficiency of light-emitting diode constantly promotes, light-emitting diode replaces fluorescent lamp (fluorescent lamp) and white heat bulb (incandescent lamp) gradually in some field.For instance, need at a high speed the scanner light source of reaction, backlight, the light source of fascia (instrument panel) of liquid crystal display (liquid crystal display, LCD), the light source of traffic signal light and some lighting device have all adopted light-emitting diode.
Fig. 1 is the schematic perspective view of known a kind of LED package.Fig. 2 is the schematic diagram of known a kind of circuit base plate, and the circuit base plate of Fig. 2 can be distinguished into the first pin, the first electrode, the second pin, the second electrode of a plurality of Fig. 1.
Please refer to Fig. 1, LED package 100 comprises a support plate D, one first pin 110, one first electrode 120, one second pin 130, one second electrode 140, a light-emitting diode chip for backlight unit (LED chip) 150, one packing colloid (encapsulant) 160.The first pin 110, the first electrode 120, the second pin 130 and the second electrode 140 are disposed on support plate D.
The first pin 110 is connected with the first electrode 120, and the second pin 130 is connected with the second electrode 140.Light-emitting diode chip for backlight unit 150 is disposed on the first pin 110, and is electrically connected with the first pin 110 and the second pin 130 respectively by one first wire 172 and one second wire 174.Packing colloid 160 is disposed at support plate D and goes up and be coated the first pin 110, the second pin 130 and light-emitting diode chip for backlight unit 150.Support plate D has two counterbore D1, and to expose respectively the first electrode 120 and the second electrode 140, and LED package 100 can for example, be electrically connected with other electronic building brick (wiring board) by the first electrode 120 and the second electrode 140.
Please refer to Fig. 2, circuit base plate 200 can be distinguished into along many cutting path A1, A2 the carrier with support plate D, the first pin 110, the first electrode 120, the second pin 130 and the second electrode 140 of a plurality of Fig. 1.Circuit base plate 200 has a plurality of pin units 210.Each pin units 210 all has one first pin 110, one second pin 130 and share terminal 212, and each shared terminal 212 is to be all formed by connecting by first electrode 120 and second electrode 140.The first pin 110 of each pin units 210 is connected with the edge of the second electrode 140 with the first electrode 120 all respectively with the second pin 130.Each pin units 210 all can cut into two conductive structures, and wherein conductive structure is for example the first pin 110 and the first electrode 120 or the second pin 130 and the second electrode 140.
In known technology, be mostly to provide and there is the substrate (not illustrating) of comprehensive covering metal layer and metal level is carried out to patterning to form circuit base plate 200.Yet the arranging density of the pin units 210 of circuit base plate 200 is low, so that the utilance of the substrate of unit are is low, and each pin units 210 only can cut into two conductive structures.The number of the conductive structure that in other words, the base material of unit are can make is less.Therefore, the cost of manufacture of conductive structure is higher.
Summary of the invention
The present invention proposes a kind of circuit base plate, and the arranging density of its pin units is larger, and its each pin units can cut into more conductive structure.
A kind of LED package of the another proposition of the present invention, its cost of manufacture is lower.
The present invention proposes a kind of circuit base plate, and it comprises a basic unit and a plurality of pin units arranged into an array, and basic unit has a plurality of counterbores, and described pin units is disposed in basic unit.Each pin units comprises share terminal and at least three pins.Shared terminal region is divided into a plurality of electrodes connected to one another.Described pin stretches out from sharing the edge of terminal, and each pin stretches out from the edge of one of them electrode respectively.Described counterbore exposes respectively the shared terminal of described pin units.
In one embodiment of this invention, the number of pins in each pin units is four.
In one embodiment of this invention, the pattern of pin units is identical in fact.
In one embodiment of this invention, the pattern of each pin units is essentially some symmetrical patterns, and pin in each pin units comprises 2 first pins and 2 second pins, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin has a chip bearing portion, and each second pin does not have a chip bearing portion.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
In one embodiment of this invention, to take a central point of each shared terminal be symmetrical centre to each point symmetrical pattern.
In one embodiment of this invention, the pattern of each pin units is essentially a line symmetric graph case, and pin in each pin units comprises 2 first pins and 2 second pins, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin has a chip bearing portion, and each second pin does not have a chip bearing portion.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
In one embodiment of this invention, each line symmetric graph case is symmetrical in a symmetry axis, and symmetry axis is parallel to column direction, and by a central point of each shared terminal.
In one embodiment of this invention, the pin units that is arranged in same row comprises a plurality of the first pin units and a plurality of the second pin units, each first pin units has one first pattern, and each second pin units has one second pattern, the first pattern is different from the second pattern, and wherein the first pin units and the second pin units are along column direction alternative arrangement.
In one embodiment of this invention, the pattern of each first pin units and each the second pin units is essentially a line symmetric graph case, pin in each first pin units comprises 2 first pins and 2 second pins, and pin in each second pin units comprises 2 first pins and 2 second pins, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin has a chip bearing portion, and each second pin does not have a chip bearing portion.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
In one embodiment of this invention, each line symmetric graph case is symmetrical in a symmetry axis, and symmetry axis is parallel to line direction, and by a central point of each shared terminal.
In one embodiment of this invention, the pattern of each first pin units can be consistent with the pattern of each the second pin units after Rotate 180 degree.
In one embodiment of this invention, the pattern of each first pin units and each the second pin units is essentially some symmetrical patterns, pin in each first pin units comprises four the first pins, and pin in each second pin units comprises four the second pins, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin has a chip bearing portion, and each second pin does not have a chip bearing portion.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
In one embodiment of this invention, the number of pins in each pin units is three.
In one embodiment of this invention, the pin units that is arranged in same row comprises a plurality of the first pin units and a plurality of the second pin units, each first pin units has one first pattern, and each second pin units has one second pattern, the first pattern is different from the second pattern, and wherein the first pin units and the second pin units are along column direction alternative arrangement.
In one embodiment of this invention, each first pin units comprises one first pin and 2 second pins, and each second pin units comprises 2 first pins and one second pin, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin units comprises 3 first pins, and each second pin units comprises 3 second pins, and the pattern of each first pin is different from the pattern of each the second pin.
In one embodiment of this invention, each first pin has a chip bearing portion, and each second pin does not have a chip bearing portion.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin also has a routing junction surface, and each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
The present invention proposes a kind of LED package, and it comprises a carrier, a light-emitting diode chip for backlight unit and a packing colloid, and wherein carrier comprises a support plate, one first electrode, one first pin, one second electrode and one second pin.The first electrode, the first pin, the second electrode and the second pin are all disposed on support plate, and support plate has two counterbores to expose respectively the first electrode and the second electrode.The first pin is connected with the edge of the first electrode.The second pin is connected with the edge of the second electrode.Light-emitting diode chip for backlight unit is disposed on the first pin and with the first pin and the second pin and is electrically connected.Packing colloid is disposed on support plate and coated the first pin, the second pin and light-emitting diode chip for backlight unit, wherein packing colloid has two counterbores to expose respectively the first electrode and the second electrode, and that the first electrode and the second electrode all have is two adjacent one another are and be positioned at the edge that cuts in corner, and two to cut edge not parallel each other.
In one embodiment of this invention, two angles that cut between edge that the first electrode has are 90 degree, and two angles that cut between edge that the second electrode has are 90 degree.
In one embodiment of this invention, the first electrode have two cut that edge and the second electrode have two cut edge and all trim with the edge of packing colloid.
In one embodiment of this invention, the first pin has a chip bearing portion and a routing junction surface, and light-emitting diode chip for backlight unit is disposed in chip bearing portion and with routing junction surface and is electrically connected.
In one embodiment of this invention, the first pin has at least one adhesive-spill-preventing breach between chip bearing portion and routing junction surface.
In one embodiment of this invention, each first pin has an adhesive-spill-preventing opening between chip bearing portion and routing junction surface.
In one embodiment of this invention, the material of packing colloid comprises a printing opacity colloid.
In sum, pin units arranging density of the present invention is higher, and each pin units can be divided at least three conductive structures.Therefore, the substrate of unit are can make more pin units, and each pin units can be divided into more conductive structure.The number of the conductive structure that in other words, the substrate of unit are can make is more.Therefore, the cost of manufacture of conductive structure of the present invention is lower.
Accompanying drawing explanation
For above and other objects of the present invention, feature and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing, be described in detail below, wherein:
Fig. 1 is a kind of schematic perspective view of known luminescence diode package.
Fig. 2 is a kind of schematic diagram of known line substrate, and the circuit base plate of Fig. 2 can be distinguished into the first pin, the first electrode, the second pin, the second electrode of a plurality of Fig. 1.
The schematic diagram of the circuit base plate that Fig. 3 A and Fig. 3 B are one embodiment of the invention.
Fig. 4～Figure 11 is the schematic diagram of multiple variation kenel of the circuit base plate of Fig. 3 A.
Figure 12 A is the schematic perspective view of the LED package of one embodiment of the invention.
Figure 12 B is by the view in the indicated direction of arrow V in Figure 12 A.
Embodiment
The schematic diagram of the circuit base plate that Fig. 3 A and Fig. 3 B are one embodiment of the invention, Fig. 4～Figure 11 is the schematic diagram of multiple variation kenel of the circuit base plate of Fig. 3 A.
Please refer to Fig. 3 A, the circuit base plate L of the present embodiment comprises a F of basic unit and a plurality of pin units arranged into an array 300, it is upper that wherein pin units 300 is all disposed at the F of basic unit, and the pin units 300 of arrayed refers on the described pin units 300 F of basic unit and is arranged in multiple lines and multiple rows.The F of basic unit has a plurality of counterbore F1.Each pin units 300 comprises share terminal 310 and at least three pins 320, and in the present embodiment, each pin units 300 has four pins 320.Share terminal 310 and divide into a plurality of electrode E connected to one another.Described pin 320 stretches out from sharing the edge of terminal 310, and each pin 320 stretches out from the edge of one of them electrode E respectively.Each counterbore F1 that the F of basic unit has exposes respectively one of them shared terminal 310 of described pin units 300.
In addition, Fig. 3 A schematically illustrates many cutting path A1, A2 with cutting path during line of cut base board L after representative, from Fig. 3 A, each pin units 300 of circuit base plate L can be divided into four conductive structures with a cutting path A2 wherein by cutting path A1 wherein, and each conductive structure is consisted of an electrode E and a connected pin 320.
It should be noted that compared to known technology, pin units 300 arranging densities of the present embodiment are higher, and each pin units 300 can be divided at least three conductive structures.Therefore, the substrate of unit are can make more pin units, and each pin units can be divided into more conductive structure.The number of the conductive structure that in other words, the substrate of unit are can make is more.Therefore, the cost of manufacture of the conductive structure of the present embodiment is lower.
In the present embodiment, the pattern of each pin units 300 is identical in fact.The pattern of each pin units 300 can be in fact some symmetrical patterns, and four pins 320 of each pin units 300 can be divided into 2 first pins 322 and 2 second pins 324, and the pattern of each first pin 322 is different from the pattern of each the second pin 324.For instance, each first pin 322 has a 322a of chip bearing portion, and each second pin 324 does not have a 322a of chip bearing portion.And each point symmetrical pattern is for example that to take a central point C of each shared terminal 310 be symmetrical centre.In the present embodiment, the first pin 322 of each pin units 300 and the second pin 324 are for example to arrange along 312 compartment of terrains, edge of sharing terminal 310.In other words, wherein one first pin 322 can be between 2 second pins 324, and wherein one second pin 324 can be between 2 first pins 322, and so the present invention is not limited with this kind of arrangement mode.
In addition, the first pin 322 also can have a routing junction surface 322b, and routing junction surface 322b is suitable for being engaged by routing with the chip (not illustrating) being disposed at afterwards on the 322a of chip bearing portion.And, for joint chip after avoiding and the colloid overflow of the 322a of chip bearing portion affect the yield of routing processing procedure to routing junction surface 322b, the present embodiment forms at least one adhesive-spill-preventing breach B (Fig. 3 A illustrates two adhesive-spill-preventing breach B as representing) between the 322a of chip bearing portion of the first pin 322 and routing junction surface 322b.Thus, aforementioned colloid can overflow to adhesive-spill-preventing breach B, and can overflow to routing junction surface 322b.In addition, please refer to Fig. 3 B, for preventing colloid overflow, also can between the 322a of chip bearing portion of the first pin 322 and routing junction surface 322b, form an adhesive-spill-preventing opening 0.
With next, the multiple variation kenel of pin units of the circuit base plate of Fig. 3 A will be introduced in detail.
Please refer to Fig. 4, in the present embodiment, the pattern of each pin units 300a is essentially a line symmetric graph case, and pin 320 in each pin units 300a comprises 2 first pins 322 and 2 second pins 324.And in the present embodiment, each line symmetric graph case is symmetrical in a symmetry axis X, and symmetry axis X is parallel to column direction, and by the central point C of each shared terminal 310.In the present embodiment, 2 first pins 322 of each pin units 300a are along sharing the adjacent arrangement in edge 312 of terminal 310 and being all positioned at the left side of sharing terminal 310,2 second pins 324 are along sharing the adjacent arrangement in edge 312 of terminal 310 and being all positioned at the right side of sharing terminal 310, and so the present invention is not limited with this kind of arrangement mode.
It should be noted that, in each embodiment of following Fig. 5～Figure 11, the pin units that is arranged in same row comprises a plurality of the first pin units and a plurality of the second pin units, each first pin units has one first pattern, and each second pin units has one second pattern, and the first pattern is different from the second pattern.Wherein, the first pin units and the second pin units are for example along column direction alternative arrangement.In addition, in the present embodiment, following Fig. 5～Figure 11 illustrates a plurality of the first pin units arranged into an array and the second pin units, and the pin units that is arranged in same a line can be all the first pin units or be all the second pin units.Certainly, in other embodiment, can be also the first pin units and the second pin units along column direction alternative arrangement, and the first pin units and the second pin units are along line direction alternative arrangement.
Please refer to Fig. 5, in the present embodiment, the pattern of each first pin units 300b and each the second pin units 300c is essentially a line symmetric graph case.And each line symmetric graph case is symmetrical in a symmetry axis Y in this way, and symmetry axis Y is parallel to line direction, and by the central point C of each shared terminal 310.In addition,, in the present embodiment, the pattern of each first pin units 300b can be consistent with the pattern of each second pin units 300c after Rotate 180 degree.
Pin in each first pin units 300b comprises 2 first pins 322 and 2 second pins 324, and pin in each second pin units 300c comprises 2 first pins 322 and 2 second pins 324.Particularly, 2 first pins 322 of each first pin units 300b be for example along share terminal 310 the first half the adjacent arrangement of edge 312a and lay respectively at left and right two sides of sharing terminal 310,2 second pins 324 along share terminals 310 Lower Half the adjacent arrangement of edge 312b and lay respectively at left and right two sides of sharing terminal 310.And, 2 first pins 322 of each second pin units 300c be for example along share terminal 310 Lower Half the adjacent arrangement of edge 312b and lay respectively at left and right two sides of sharing terminal 310,2 second pins 324 along share terminals 310 the first half the adjacent arrangement of edge 312a and lay respectively at left and right two sides of sharing terminal 310.It should be noted that aforementioned each first pin units 300b and the first pin 322 of each second pin units 300c and the arrangement mode of the second pin 324 are only for illustrating, not in order to limit the present invention.
Please refer to Fig. 6, in the present embodiment, the pattern of each first pin units 300d and each the second pin units 300e is essentially some symmetrical patterns.Pin in each first pin units 300d for example has four the first pins 322, and pin in each second pin units 300e for example has four the second pins 324.Specifically, four the first pins 322 in each first pin units 300d are connected with edge 312c, 312d, 312e, the 312f of right lower quadrant with upper left quarter, lower left quarter, the upper right quarter of shared terminal 310 respectively.Similarly, four the second pins 324 of each second pin units 300e are connected with edge 312c, 312d, 312e, the 312f of right lower quadrant with upper left quarter, lower left quarter, the upper right quarter of shared terminal 310 respectively.It should be noted that aforementioned each first pin units 300d and the first pin 322 of each second pin units 300e and the arrangement mode of the second pin 324 are only for illustrating, not in order to limit the present invention.
In addition, each first pin units 300d that Fig. 6 illustrates and the pattern of each the second pin units 300e can also be line symmetric graph cases, and aforementioned line symmetric graph case has two symmetry axis X, Y, wherein symmetry axis X is parallel to column direction, and symmetry axis Y is parallel to line direction, and two symmetry axis X, Y are all by the central point C of each shared terminal 310, and so this is only for illustrating, not in order to limit the present invention.
It is worth mentioning that, in each embodiment of following Fig. 7～Figure 10, each pin units can have three pins.And each first pin units comprises one first pin and 2 second pins, each second pin units comprises 2 first pins and one second pin.Each embodiment of Fig. 7～Figure 10 introduces each the first pin units and the first pin of each the second pin units and various arrangement mode of the second pin, and so the present invention is not limited with described arrangement mode, knows this operator when doing various changes and retouching.
Please refer to Fig. 7, in the present embodiment, the first pin 322 of each first pin units 300f can be connected with edge 312c, 312d, the 312e of upper right quarter with upper left quarter, the lower left quarter of shared terminal 310 respectively with 2 second pins 324, and 2 first pins 322 of each second pin units 300g can be connected with edge 312c, 312f, the 312e of upper right quarter with upper left quarter, the right lower quadrant of shared terminal 310 respectively with one second pin 324.
Please refer to Fig. 8, in the present embodiment, the first pin 322 of each first pin units 300h and 2 second pins 324 can be respectively with the right lower quadrant of shared terminal 310, upper right quarter, lower left quarter with edge 312f, 312e, 312d be connected, and respectively 2 first pins 322 of second pin units 300i can be connected with edge 312c, 312f, the 312d of lower left quarter with upper left quarter, the right lower quadrant of shared terminal 310 respectively with one second pin 324.
Please refer to Fig. 9, in the present embodiment, the first pin 322 of each first pin units 300j and 2 second pins 324 can be respectively with the upper left quarter of shared terminal 310, upper right quarter, right lower quadrant with edge 312c, 312e, 312f be connected, and respectively 2 first pins 322 of second pin units 300k can be connected with edge 312c, 312d, the 312e of upper right quarter with upper left quarter, the lower left quarter of shared terminal 310 respectively with one second pin 324.
Please refer to Figure 10, in the present embodiment, the first pin 322 of each first pin units 300m and 2 second pins 324 can be respectively with the upper right quarter of shared terminal 310, upper left quarter, lower left quarter with edge 312e, 312c, 312d be connected, and respectively 2 first pins 322 of second pin units 300n can be connected with edge 312e, 312f, the 312c of upper left quarter with upper right quarter, the right lower quadrant of shared terminal 310 respectively with one second pin 324.
Please refer to Figure 11, in the present embodiment, each pin units can have three pins, and wherein each first pin units 300p comprises 3 first pins 322, and each second pin units 300q comprises 3 second pins 324.For instance, 3 first pins 322 of each first pin units 300p can be respectively with the upper left quarter of shared terminal 310, upper right quarter, right lower quadrant with edge 312c, 312e, 312f is connected, and respectively 3 second pins 324 of second pin units 300q can be connected with edge 312c, 312d, the 312e of upper right quarter with upper left quarter, the lower left quarter of shared terminal 310 respectively.
To introduce in detail with the made LED package of the circuit base plate of Fig. 3 A or Fig. 4～Figure 11 below.
Figure 12 A is the schematic perspective view of the LED package of one embodiment of the invention, and Figure 12 B is by the view in the indicated direction of arrow V in Figure 12 A.
Referring to Figure 12 A and Figure 12 B, the LED package 500 of the present embodiment comprises a light-emitting diode chip for backlight unit 410, a packing colloid 420 and a carrier 430, and wherein carrier 430 comprises a support plate 432, one first electrode E1, one first pin 322, one second electrode E2, one second pin 324.The first electrode E1, the first pin 322, the second electrode E2 and the second pin 324 are all disposed on support plate 432, and support plate 432 has two counterbore 432a to expose respectively the first electrode E1 and the second electrode E2.
The first pin 322 is connected with the edge of the first electrode E1, and the second pin 324 is connected with the edge of the second electrode E2.In the present embodiment, the first pin 322 and the first electrode E1 are for example one-body molded, and in addition, the second pin 324 and the second electrode E2 are for example one-body molded.The first pin 322 can have a 322a of chip bearing portion and a routing junction surface 322b, and the second pin 324 also can have a routing junction surface 324a.Light-emitting diode chip for backlight unit 410 is configurable upper in the 322a of chip bearing portion, and is electrically connected with two routing junction surface 322b, 324a respectively.Packing colloid 420 is disposed on support plate 432 and coated the first pin 322, the second pin 324 and light-emitting diode chip for backlight unit 410.The material of packing colloid 420 can be a printing opacity colloid or other applicable light transmissive material.
In the present embodiment, for avoiding the colloid overflow that engages light-emitting diode chip for backlight unit 410 and the 322a of chip bearing portion to routing junction surface 322b, the first pin 322 can have at least one adhesive-spill-preventing breach B between the 322a of chip bearing portion and routing junction surface 322b.In other embodiment, each first pin 322 can have an adhesive-spill-preventing opening (not illustrating) between the 322a of chip bearing portion and routing junction surface 322b.
The first electrode E1 of it should be noted that the present embodiment divides one of them of four electrode E forming along a cutting path A1 and cutting path A2 with the share terminal 310 of Fig. 3 A.Similarly, the second electrode E2 is divided one of them of four electrode E forming along another cutting path A1 and cutting path A2 as hereinbefore by another share terminal 310.Therefore,, compared to known technology, the first electrode E1 of the present embodiment and the area of the second electrode E2 are less than respectively the first known electrode 120 and the area (please refer to Fig. 1) of the second electrode 140.Thus, the volume of the LED package 500 of the present embodiment can be less than the volume of known LED package 100.
The first electrode E1 and the second electrode E2 all have two adjacent one another are and be positioned at packing colloid 420 corner cut edge R1, R2, and two to cut edge R1, R2 not parallel each other.In the present embodiment, two angles that cut between edge R1, R2 that the first electrode E1 has are for example 90 degree, and two angles that cut between edge R1, R2 that the second electrode E2 has are for example 90 degree.Certainly, in other embodiment, two angles that cut between edge R1, R2 that the first electrode E1 and the second electrode E2 have can be also other angles.
In addition, the first electrode E1 have two cut that edge R1, R2 and the second electrode E2 have two cut edge R1, R2 and all trim with the edge of packing colloid 420.For instance, what the first electrode E1 had two cuts edge R1, R2 and trims with two edges 422,424 of packing colloid 420 respectively, and what the second electrode E2 had two cuts edge R1, R2 and trim with two edges 426,424 of packing colloid 420 respectively.
In sum, pin units arranging density of the present invention is higher, and each pin units can be divided at least three conductive structures.Therefore, the substrate of unit are can make more pin units, and each pin units can be divided into more conductive structure.The number of the conductive structure that in other words, the substrate of unit are can make is more.Therefore, the cost of manufacture of conductive structure of the present invention is lower.In addition, between the chip bearing portion of the first pin of the present invention and routing junction surface, also dispose adhesive-spill-preventing breach or adhesive-spill-preventing opening, to avoid the colloid overflow of joint chip and chip bearing portion to affect the yield of routing processing procedure to routing junction surface.Moreover, because the area of first and second electrode of LED package of the present invention is less, the therefore small volume of LED package of the present invention.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; any person with usual knowledge in their respective areas; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when being as the criterion of defining depending on claim scope of the present invention.
Claims (7)
1. a LED package, is characterized in that, comprising:
One carrier, comprising:
One support plate, has two counterbores;
One first electrode, is disposed on this support plate, and described counterbore one of them expose this first electrode;
One first pin, is disposed on this support plate and with the edge of this first electrode and is connected;
One second electrode, is disposed on this support plate, and wherein another of described counterbore exposes this second electrode;
One second pin, is disposed on this support plate and with the edge of this second electrode and is connected;
Described the first electrode, the second electrode, the first pin, the second pin are all positioned on the same plane of support plate the same side, and the first electrode and the first pin be formed in one, and the second electrode and the second pin are formed in one;
One light-emitting diode chip for backlight unit, is disposed on this first pin and with this first pin and this second pin and is electrically connected; And
One packing colloid, be disposed on this surface of this support plate and coated this first pin, this second pin and this light-emitting diode chip for backlight unit, wherein this first electrode and this second electrode all have two adjacent one another arely and be positioned at the edge that cuts in corner, and two to cut edge not parallel each other
Wherein this carrier is to cut apart acquisition from a circuit base plate, and this circuit base plate comprises:
One basic unit, has a plurality of counterbores, and this basic unit will be cut into a plurality of these support plates;
A plurality of pin units arranged into an array, are disposed in this basic unit, and respectively this pin units comprises:
Share terminal, divides into a plurality of electrodes connected to one another; And
Four pins, stretch out from the edge of this shared terminal, and wherein respectively this pin stretches out from the edge of one of them electrode respectively,
Wherein, the pattern of described pin units is identical, respectively the pattern of this pin units is some symmetrical patterns, wherein respectively this point symmetry pattern to take a respectively central point of this shared terminal be symmetrical centre, and respectively the described pin in this pin units comprises 2 first pins and 2 second pins, and respectively the pattern of this first pin is different from the pattern of this second pin respectively, respectively this first pin is arranged along the marginating compartment of this shared terminal with this second pin respectively, wherein those first pins one of them between those second pins, described the second pin one of them between described the first pin, described counterbore exposes respectively the shared terminal of described pin units, described shared terminal in adjacent two row is in alignment with each other on column direction, wherein respectively this first pin has a chip bearing portion, and respectively this second pin does not have a chip bearing portion, wherein in those pin units of same a line, those pins that are arranged in different lines are spaced from each other.
2. LED package as claimed in claim 1, is characterized in that, two angles that cut between edge that wherein this first electrode has are 90 degree, and two angles that cut between edge that this second electrode has are 90 degree.
3. LED package as claimed in claim 1, is characterized in that, wherein this first electrode have two cut that edge and this second electrode have two cut edge and all trim with the edge of this packing colloid.
4. LED package as claimed in claim 1, is characterized in that, wherein this first pin has a chip bearing portion and a routing junction surface, and this light-emitting diode chip for backlight unit is disposed in this chip bearing portion and be electrically connected with this routing junction surface.
5. LED package as claimed in claim 4, is characterized in that, wherein this first pin has at least one adhesive-spill-preventing breach between this chip bearing portion and this routing junction surface.
6. LED package as claimed in claim 4, is characterized in that, wherein respectively this first pin has an adhesive-spill-preventing opening between this chip bearing portion and this routing junction surface.
7. LED package as claimed in claim 1, is characterized in that, wherein the material of this packing colloid comprises a printing opacity colloid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110038898.8A CN102142423B (en) | 2008-05-16 | 2008-05-16 | Circuit substrate and package of light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110038898.8A CN102142423B (en) | 2008-05-16 | 2008-05-16 | Circuit substrate and package of light emitting diode |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810100702A Division CN101582402B (en) | 2008-05-16 | 2008-05-16 | Circuit base plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102142423A CN102142423A (en) | 2011-08-03 |
| CN102142423B true CN102142423B (en) | 2014-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110038898.8A Active CN102142423B (en) | 2008-05-16 | 2008-05-16 | Circuit substrate and package of light emitting diode |
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| Country | Link |
|---|---|
| CN (1) | CN102142423B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1380702A (en) * | 2001-04-09 | 2002-11-20 | 株式会社东芝 | Luminescent device |
| US6534799B1 (en) * | 2000-10-03 | 2003-03-18 | Harvatek Corp. | Surface mount light emitting diode package |
| TWM328674U (en) * | 2007-08-02 | 2008-03-11 | Everlight Electronics Co Ltd | Light emitting diode |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3507251B2 (en) * | 1995-09-01 | 2004-03-15 | キヤノン株式会社 | Optical sensor IC package and method of assembling the same |
| US7710045B2 (en) * | 2006-03-17 | 2010-05-04 | 3M Innovative Properties Company | Illumination assembly with enhanced thermal conductivity |
| KR100764432B1 (en) * | 2006-04-05 | 2007-10-05 | 삼성전기주식회사 | Led package having anodized isolations and its manufacturing method |
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2008
- 2008-05-16 CN CN201110038898.8A patent/CN102142423B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534799B1 (en) * | 2000-10-03 | 2003-03-18 | Harvatek Corp. | Surface mount light emitting diode package |
| CN1380702A (en) * | 2001-04-09 | 2002-11-20 | 株式会社东芝 | Luminescent device |
| TWM328674U (en) * | 2007-08-02 | 2008-03-11 | Everlight Electronics Co Ltd | Light emitting diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102142423A (en) | 2011-08-03 |
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Address after: China Taiwan New Taipei city forest region of the road 6 No. 8 Applicant after: Everlight Electronics Co.,Ltd. Address before: The central road Tucheng Chinese Taiwan New Taipei City three lane 76 No. 25 Applicant before: Everlight Electronics Co.,Ltd. |
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