CN102142236A - Liquid crystal display driver for high-resolution interlacing scanned video signals - Google Patents
Liquid crystal display driver for high-resolution interlacing scanned video signals Download PDFInfo
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Abstract
The invention discloses a liquid crystal display driver for high-resolution interlacing scanned video signals. The liquid crystal display driver comprises an interlacing video input module, a field programmable gate array (FPGA) module, a synchronous dynamic random access memory (SDRAM), a brightness control module, a line-by-line video output module, a low voltage differential signaling (LVDS) liquid crystal screen logic board interface module, a crystal oscillator and a power supply module, wherein the interlacing video input module samples the interlacing scanned video signals from a video input interface and performs analog/digital conversion; the FPGA module is connected with the interlacing video input module and receives the interlacing scanned video signals converted by the interlacing video input module; the SDRAM is connected with the FPGA module through a bus and stores the interlacing scanned video signals; the brightness control module is connected with the FPGA module; the line-by-line video output module is connected with the FPGA module; the LVDS liquid crystal screen logic board interface module is connected with the FPGA module; the crystal oscillator is connected with the FPGA module; and the power supply module is connected with the FPGA module and the like and provides an analog direct-current power supply and a digital direct-current power supply. The liquid crystal display driver realizes point-to-point display of the high-resolution interlacing scanned video signals on a liquid crystal display.
Description
Technical field
The present invention relates to a kind of lcd technology, particularly relate to a kind of LCD driver at the high resolving power interlaced video signal.
Background technology
Recent years, the technical development of LCD is rapid, traditional C RT (Cathode Ray Tube, cathode-ray tube (CRT)) display is progressively replaced by LCD, becomes main flow with 16: 9 widescreen LCD in home audio-visual, Entertainment, industrial display application field.What LCD required input is the progressive-scan video signal form, and traditional C RT display generally adopts staggered scanning, and input signal is the simulation interlaced video signal.The high resolving power interlaced video signal is as 1024 * 768,1280 * 1024 resolution, be mainly derived from the video format that some industrial CRT display devices and CRT radar peculiar to vessel are adopted, the main character display type of these equipment, form type and change photo type image slowly, the image type image that does not relate to rapid movement mainly requires high to the sharpness that shows.When the kinescope of these equipment damages,, need to seek replacement scheme owing to be difficult to purchase similar accessory.
PAL (Phase Alternating Line, line-by-line inversion) standard is a kind of interlaced scanning video form, current LCD has adopted multiple deinterlacing technique to be implemented to the conversion of progressive video signal, and be presented on the LCD, this kind LCD TV device has been realized single chip, and use very extensively, but this LCD can not discern 1024 * 768 or more high-resolution interlaced video signal.
The development of Digital Television and audio-visual technology at present, produced the i.e. high definition interlaced scan tv signal format of 1920 * 1080 resolution of 1080i, large-screen liquid crystal display television on the market is much all supported the interlaced video signal that 1080i is such, such TV tech is owing to adopt the special chip scheme, the video signal format that can discern only limits to popular computer VGA (Video Graphics Array at present, Video Graphics Array) video and television video are not supported the interlaced video signal of 1024 * 768 or 1280 * 1024 such resolution yet.
A kind of video specialty chip with utilization 1080i interlaced video signal is the scheme of means by limited programming in the chip or configuring technical, and as game video converter, industrial display converter, support sector divides the staggered scanning vision signal.When if this professional chip is used for the high resolving power interlaced video signal and since image that transforms and literal in the demonstration on the LCD far away from clear on former CRT monitor, and can not drop into actual use.
In addition, the available liquid crystal display is mainly controlled display brightness by adjusting liquid crystal display brightness backlight, and the brightness of LCD backlight approximately can only high-high brightness 30%～100% interval in adjust, the brightness setting range is very limited, can not adjust to the luminance level of deceiving entirely.
Summary of the invention
Technical matters to be solved by this invention provides a kind of LCD driver at the high resolving power interlaced video signal, and it has realized carrying out point-to-point demonstration on LCD.
The present invention solves above-mentioned technical matters by following technical proposals: a kind of LCD driver at the high resolving power interlaced video signal is characterized in that it comprises:
The interlaced video load module, it is from a video input interface sampling interlaced video signal and carry out the analog/digital conversion;
The FPGA module, it is connected and receives and handle the interlaced video signal of process interlaced video load module conversion with the interlaced video load module;
The SDRAM storer, it is connected with the FPGA module by bus, and it stores interlaced video signal;
The brilliance control module, it is connected with the FPGA module and voltage is adjusted in the brightness that a potentiometer interface sends carried out sending the FPGA module to after the voltage-frequency conversion;
The progressive output module, it is connected with the FPGA module, and interlaced video signal is gone to be sent to a slave display interface after the interlacing;
LVDS liquid crystal display logic card interface module, it is connected with the FPGA module, and interlaced video data is gone to drive a liquid crystal panel interface after the interlacing point-to-pointly;
Crystal oscillator, it is connected with the FPGA module, and produces the work of three road clocks with synchronous SDRAM storer, progressive output module, LVDS liquid crystal display logic card interface module;
Power module, it is connected with FPGA module, crystal oscillator, SDRAM storer, interlaced video load module, brilliance control module, progressive output module, LVDS liquid crystal display logic card interface module respectively and analog DC power supply and digital DC power supply is provided.
Preferably, described FPGA module comprises clock generator, I
2C controller, time schedule controller, even field detector, input FIFO writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller, progressive scanned video controller, LVDS interface controller, clock generator produces the clock of different frequency by phaselocked loop and is connected with SDRAM-FIFO controller, progressive scanned video controller, LVDS interface controller respectively, time schedule controller respectively with clock generator, I
2C controller, even field detector, SDRAM-FIFO controller, output FIFO Read Controller, LVDS interface controller connect, input FIFO writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller order connect step by step, output FIFO Read Controller is connected I with progressive scanned video controller, LVDS interface controller
2Interlaced video signal in the C controller identification interlaced video load module, time schedule controller notify even field detector to send even field mark signal to input FIFO writing controller, and time schedule controller is according to I
2The situation of C controller configuration interlaced video load module opens or closes the switch of progressive scanned video controller and LVDS interface controller.
Preferably, the work of the synchronous SDRAM-FIFO controller of described clock generator, progressive scanned video controller, LVDS interface controller.
Preferably, described clock generator, I
2C controller, time schedule controller common clock also are connected input FIFO writing controller and I with crystal oscillator
2The C controller is connected with the interlaced video load module with control bus by data bus respectively, the luminance processor module also is connected with the brilliance control module, the SDRAM-FIFO controller also is connected with the SDRAM storer, the progressive scanned video controller also is connected with the progressive output module, and the LVDS interface controller also is connected with LVDS liquid crystal display logic card interface module.
Preferably, described luminance processor comprises RGB/YUV converter, counter, multiplier and YUV/RGB converter, the RGB/YUV converter is connected with multiplier by the Y data bus, the RGB/YUV converter is connected with the YUV/RGB converter with the V data bus by the U data bus, counter is connected with multiplier and exports luminance control data and give multiplier, multiplier is connected with the YUV/RGB converter, and multiplier sends brightness Y data and luminance control data multiplied result high eight-bit data to the YUV/RGB converter.
Preferably, described RGB/YUV converter also is connected with input FIFO writing controller, and counter also is connected with the brilliance control module and receives voltage and the frequency signal that the brilliance control module produces, and the YUV/RGB converter also is connected with the input fifo module.
Preferably, described SDRAM-FIFO controller comprises the SDRAM clock, interlacing SDRAM page or leaf counter, input staggered scanning linage-counter, interlacing SDRAM row address generator, input FIFO Read Controller, sdram controller, output FIFO writing controller, SDRAM row address generator line by line, export the linage-counter of lining by line scan, SDRAM page or leaf counter line by line, sdram controller and SDRAM clock, interlacing SDRAM row address generator, SDRAM row address generator connects line by line, interlacing SDRAM page or leaf counter is connected with input staggered scanning linage-counter, input staggered scanning linage-counter also respectively with interlacing SDRAM row address generator, input FIFO Read Controller connects, SDRAM page or leaf counter and the output linage-counter of lining by line scan is connected line by line, output line by line scan linage-counter respectively with SDRAM row address generator line by line, output FIFO writing controller connects, the SDRAM clock provides synchronous clock, interlacing SDRAM row address generator writes the SDRAM storer with interlaced video signal, and SDRAM row address generator is read interlaced video signal from the SDRAM storer line by line.
Preferably, described input FIFO Read Controller also is connected with the input fifo module, output FIFO writing controller also is connected with the output fifo module, and sdram controller also is connected with the SDRAM storer with time schedule controller respectively, and the SDRAM clock also is connected with clock generator.
Preferably, described sdram controller adopts the mode of burst page or leaf read-write.
Preferably, the brightness that sends of described potentiometer interface is adjusted voltage and also is sent to a liquid crystal panel interface to adjust backlight illumination.
Positive progressive effect of the present invention is:
One, the present invention adopts the direct alternating method of parity field image to go interlacing, view data is undistorted, and only carry out analog/digital conversion one time, it all is digital signal that post-processed and liquid crystal display drive, the signal to noise ratio (S/N ratio) height, realized on LCD, carrying out point-to-point demonstration, display resolution even also better than CRT monitor.
Two, the present invention can adjust the brightness of LCD backlight and the brightness value of video data simultaneously, is a kind of FR brightness adjustment technology, can adjust in the brightest brightness linearity of carrying out to black full interval.
Description of drawings
Fig. 1 is the theory diagram that the present invention is directed to the LCD driver of high resolving power interlaced video signal.
Fig. 2 is the theory diagram of FPGA module among the present invention.
Fig. 3 is the theory diagram of luminance processor among the present invention.
Fig. 4 is the theory diagram of SDRAM-FIFO controller among the present invention.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to describe technical scheme of the present invention in detail.
As shown in Figure 1, the LCD driver that the present invention is directed to the high resolving power interlaced video signal comprises power module, FPGA (Field Programmable Gate Array, field programmable gate array) module, crystal oscillator, SDRAM (Synchronous Dynamic Random Access Memory, synchronous DRAM) storer, the interlaced video load module, the brilliance control module, progressive output module and LVDS (Low Voltage Differential Signal, Low Voltage Differential Signal) liquid crystal display logic card interface module, power module respectively with the FPGA module, crystal oscillator, the SDRAM storer, the interlaced video load module, the brilliance control module, the progressive output module, LVDS liquid crystal display logic card interface module connects, the interlaced video load module is connected from video input interface sampling high resolving power interlaced video signal and with the FPGA module, and crystal oscillator is connected with the FPGA module; The SDRAM storer is connected with the FPGA module by bus; The brightness that the potentiometer interface sends is adjusted voltage one tunnel and is sent to the liquid crystal panel interface to adjust backlight illumination, another road is delivered to the brilliance control module and is carried out sending the FPGA module to after the voltage-frequency conversion, the brilliance control module is connected with the FPGA module, the progressive output module is connected with the FPGA module, and the high resolving power interlaced video signal is gone to be sent to slave display (CRT monitor or LCD) interface after the interlacing; LVDS liquid crystal display logic card interface module is connected with the FPGA module, the high resolving power interlaced video data is gone to drive the liquid crystal panel interface after the interlacing point-to-pointly, at last point-to-point demonstration the on LCD.Wherein, it is the chip of EP1C3T144 that the FPGA module can adopt model, it is the chip of AD9883AKST or pin compatibility that the interlaced video load module adopts model, it is the chip of ADV7123 or pin compatibility that the progressive output module adopts model, it is the chip of LM331 that the brilliance control module adopts model, it is the chip of DS90C385 or pin compatibility that LVDS liquid crystal display logic card interface module adopts model, and it is that 64Mbit, bit wide are 16 SDRAM storage chip that the SDRAM storer adopts a slice capacity.Power module provides analog DC power supply and digital DC power supply for other all modules, and the driving power of liquid crystal panel is provided.Crystal oscillator produces three road configurable clocks in the FPGA inside modules by phaselocked loop as the reference clock of FPGA module, with the work of synchronous SDRAM storer, progressive output module, three modules of LVDS liquid crystal display logic card interface module.The high resolving power that the interlaced video load module inserts video input interface, carry out analog/digital (A/D) as 1024 * 768,1280 * 1024 resolution and the interlaced scanning video simulating signal that satisfies the RS343A video standard and transform, generate R (red primary), G (green primary), each 8 digital video digital signal of B (blue primary).After the FPGA module received and handle the video signal of process interlaced video load module conversion, the FPGA module was passed through I
2The C bus is discerned and is disposed as resolution, dot frequency clock, line frequency, field frequency, row field system chronizing impulse polarity, correctly to catch even field mark signal the video signal format of interlaced video load module conversion processing.Subsequently the FPGA module with the field preface be the idol interlaced video signal press row 0, row 2, row 4 ... row 1022 (is example with 1280 * 1024 resolution) writes the input fifo module in the FPGA module, and presses row address 0, row address 2, row address 4 ... row address 1022 is stored in the SDRAM storer; After idol field mark signal capture finishes, the FPGA module begins to catch strange field mark signal, and be that strange interlaced video signal is pressed row 1, row 3, row 5 with the field preface ... row 1023 writes the input fifo module in the FPGA module, and presses row address 1, row address 3, row address 5 ... row address 1023 is stored in the SDRAM storer.When the voltage of potentiometer interface changes, voltage one tunnel is delivered to the liquid crystal panel interface with the variation backlight of control liquid crystal display, another road is delivered to the brilliance control module and is carried out voltage-frequency and change the module to FPGA, control the brightness value of incoming video signal simultaneously, its method is to adjust to when the brightest when potentiometer, the liquid crystal display high-high brightness that reaches backlight, the brightness value of incoming video signal is not decayed; Adjust to when the darkest when potentiometer, the liquid crystal display minimum brightness that reaches backlight, the brightness value of incoming video signal decay to zero, so just adjust the brightness value of liquid crystal display device backlight lightness and video data synchronously, realize the linear adjustment from blank screen to the brightest gamut; The every 125ms of FPGA module to this frequency counting once, and RGB data that count value entered the input fifo module as luminance control data control; Because the interlaced video signal that is stored in the SDRAM storer has adopted the directly staggered mode of parity field, therefore outputs to the interlaced video signal of progressive output module and LVDS liquid crystal display logic card interface module by row address 0, row address 1, row address 2 ... the order of row address 1022, row address 1023 is read from the SDRAM storer and is got final product.Because SDRAM memory read/write both sides have all adopted fifo module, the clock that reads in video data and output video data like this can be different, so have realized that direct alternating method removes interlacing and frame frequency conversion.LVDS liquid crystal display logic card interface module can drive 16: 9 large-screen lc panel, video with input interlacing 1280 * 1024 resolution is an example, adopt the liquid crystal panel of 1920 * 1080 resolution, 1280 * 1024 image is presented at center Screen, fill with the blank screen data in other zone, this method has realized point-to-point demonstration, and for character type, form type with change photo type image slowly, the clear effect of demonstration is very desirable.
As shown in Figure 2, the FPGA module comprises clock generator, I
2C controller, time schedule controller, even field detector, input FIFO (push-up storage) writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller, progressive scanned video controller, LVDS interface controller.Clock generator produces the clock of different frequency by phaselocked loop and is connected with SDRAM-FIFO controller, progressive scanned video controller, LVDS interface controller respectively, time schedule controller according to logical relation respectively with clock generator, I
2C controller, even field detector, SDRAM-FIFO controller, output FIFO Read Controller, LVDS interface controller connect even field detector and I
2C controller, input FIFO writing controller connect, input FIFO writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller order connect step by step, and output FIFO Read Controller is connected with progressive scanned video controller, LVDS interface controller.Simultaneously, clock generator, I
2C controller, time schedule controller common clock also are connected input FIFO writing controller and I with crystal oscillator
2The C controller is connected with the interlaced video load module with control bus by data bus respectively, the luminance processor module is connected with the brilliance control module, the SDRAM-FIFO controller is connected with the SDRAM storer, the progressive scanned video controller is connected with the progressive output module, and the LVDS interface controller is connected with LVDS liquid crystal display logic card interface module.Crystal oscillator is clock generator, I
2C controller, time schedule controller provide clock; When powering on, time schedule controller at first notifies clock generator, SDRAM-FIFO controller to carry out initialization, and clock generator produces the work of configurable clock synchronization SDRAM-FIFO controller, progressive scanned video controller, three modules of LVDS interface controller; Then, the I2C controller is discerned the video format information in the interlaced video load module, and the interlaced video load module is configured; After finishing configuration, time schedule controller notifies even field detector to send even field mark signal to input FIFO writing controller; Time schedule controller is according to I simultaneously
2C controller configuration interlaced video load module whether case of successful opens or closes the power down switch of progressive scanned video controller and LVDS interface controller; Input FIFO writing controller receive begin behind the even field mark signal with interlacing look load module output and a preface for the interlaced video signal of idol by row 0, row 2, row 4 ... row 1022, and preface be that the interlaced video signal of strange field is pressed row 1, row 3, row 5 ... row 1023 (is example with 1280 * 1024 resolution) writes the input fifo module; The RGB data need to carry out brightness processed through luminance processor during this time; The SDRAM-FIFO controller is pressed row address 0, row address 2, row address 4 from the input fifo module ... row address 1022, row address 1, row address 3, row address 5 ... row address 1023 is stored in the SDRAM storer, presses row address 0, row address 1, row address 2 simultaneously ... the order of row address 1022, row address 1023 from the SDRAM storer read data and write output fifo module; The data that output FIFO Read Controller will be exported fifo module send to respectively in progressive scanned video controller and the LVDS interface controller; The LVDS interface controller provides steering logic and inserts the blank screen data according to the requirement of LVDS liquid crystal display logic card interface module, realizes point-to-point display driver; The progressive scanned video controller provides an output such as clock, horizontal synchronization, vertical synchronization and blanking signal frequently, drives the output module of lining by line scan with the RGB data bus.
As shown in Figure 3, luminance processor comprises RGB/YUV converter, counter, multiplier and YUV/RGB converter.The RGB/YUV converter is connected with multiplier by 8 Y data buss, the RGB/YUV converter is connected with the YUV/RGB converter with 8 V data buss by 8 U data buss, counter can be that timing is the counter of 125ms, counter is connected with multiplier and 8 luminance control datas of 8 output of per second are given multiplier, and multiplier is connected with the YUV/RGB converter and sends Y data and luminance control data multiplied result most-significant byte data to the YUV/RGB converter.The RGB/YUV converter is connected with input FIFO writing controller by 24 RGB data buss, counter is connected with the brilliance control module and receives voltage and the frequency signal that the brilliance control module produces, and the YUV/RGB converter is connected with the input fifo module and exports 24 RGB data bus to importing fifo module.The brilliance control module is according to the frequency signal of potentiometer interface generation 0～16384Hz, and counter with this frequency half point frequently, in the 62.5ms inside counting of 125ms in the cycle, adopts 9 saturated counters earlier, with the value representation luminance factor of most-significant byte; The RGB/YUV converter is 8 brightness Y data and each colourity UV data of 8 with each RGB data conversion of 8, chroma data does not deal with and directly delivers to the YUV/RGB converter, 8 brightness Y data and 8 luminance factor multiply each other with multiplier, the most-significant byte brightness data of output is delivered to the YUV/RGB converter, is reduced into the RGB data of brightness controlled by the YUV/RGB converter.
As shown in Figure 4, the SDRAM-FIFO controller comprises SDRAM clock, interlacing SDRAM page or leaf counter, input staggered scanning linage-counter, interlacing SDRAM row address generator, input FIFO Read Controller, sdram controller, output FIFO writing controller, line by line scan linage-counter, SDRAM page or leaf counter line by line of SDRAM row address generator, output line by line.The SDRAM clock is connected with other all modules in the SDRAM-FIFO controller, for other all modules provide synchronous clock; Sdram controller adopts burst full page read-write mode to read in from the video data of importing the FIFO Read Controller, or video data write output FIFO writing controller, sdram controller is with interlacing SDRAM row address generator, SDRAM row address generator is connected line by line; Interlacing SDRAM page or leaf counter is connected with input staggered scanning linage-counter; Input staggered scanning linage-counter also is connected with interlacing SDRAM row address generator, input FIFO Read Controller respectively; SDRAM page or leaf counter and the output linage-counter of lining by line scan is connected line by line; Output is lined by line scan, and SDRAM row address generator, output FIFO writing controller are connected linage-counter respectively with line by line.Input FIFO Read Controller is connected with the input fifo module, and output FIFO writing controller is connected with the output fifo module, and sdram controller also is connected with the SDRAM storer with time schedule controller respectively, and the SDRAM clock is connected with clock generator.The SDRAM clock is connected with other all modules in the SDRAM-FIFO controller, for other all modules provide synchronous clock; Sdram controller is accepted the notice of time schedule controller and is carried out initialization, enters the automatic refresh cycle after finishing; The mode of sdram controller employing burst full page read-write, each read-write is that 256 words are that unit carries out with one page, and for 1024 * 768 resolution, delegation has 4 pages, and for 1280 * 1024 resolution, delegation has 5 pages; With 1280 * 1024 resolution is example, full 5 pages of the every meter of interlacing SDRAM page or leaf counter, and notice input staggered scanning linage-counter adds 1, and notice input FIFO Read Controller is read data line from the input fifo module; For the field preface is the interlaced video signal of idol field, interlacing SDRAM row address generator is pressed row address 0, row address 2, row address 4 from row address 0 ... the interlaced video signal that row address 1022 will be imported in the fifo module writes the SDRAM storer; For the field preface is the interlaced video signal of strange field, interlacing SDRAM row address generator is pressed row address 1, row address 3, row address 5 from row address 1 ... the interlaced video signal that row address 1023 will be imported in the fifo module writes the SDRAM storer; Sdram controller reads in interlaced video signal from the input fifo module writes during the page or leaf, inserts and reads a page cycle; The every meter of SDRAM page or leaf counter is full 5 pages line by line, and notice is exported the linage-counter of lining by line scan and added 1, and notifies output FIFO writing controller to read data line from the SDRAM storer, writes the output fifo module; Line by line SDRAM row address generator according to output line by line scan linage-counter each the counting by row address 0, row address 1, row address 2 ... the order of row address 1022, row address 1023 is read the RGB data of interlaced video signal from the SDRAM storer.
Though more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, under the prerequisite that does not deviate from principle of the present invention and essence, can make numerous variations or modification to these embodiments.Therefore, protection scope of the present invention is limited by appended claims.
Claims (10)
1. LCD driver at the high resolving power interlaced video signal is characterized in that it comprises:
The interlaced video load module, it is from a video input interface sampling interlaced video signal and carry out the analog/digital conversion;
The FPGA module, it is connected and receives and handle the interlaced video signal of process interlaced video load module conversion with the interlaced video load module;
The SDRAM storer, it is connected with the FPGA module by bus, and it stores interlaced video signal;
The brilliance control module, it is connected with the FPGA module and voltage is adjusted in the brightness that a potentiometer interface sends carried out sending the FPGA module to after the voltage-frequency conversion;
The progressive output module, it is connected with the FPGA module, and interlaced video signal is gone to be sent to a slave display interface after the interlacing;
LVDS liquid crystal display logic card interface module, it is connected with the FPGA module, and interlaced video data is gone to drive a liquid crystal panel interface after the interlacing point-to-pointly;
Crystal oscillator, it is connected with the FPGA module, and produces the work of three road clocks with synchronous SDRAM storer, progressive output module, LVDS liquid crystal display logic card interface module;
Power module, it is connected with FPGA module, crystal oscillator, SDRAM storer, interlaced video load module, brilliance control module, progressive output module, LVDS liquid crystal display logic card interface module respectively and analog DC power supply and digital DC power supply is provided.
2. the LCD driver at the high resolving power interlaced video signal as claimed in claim 1 is characterized in that, described FPGA module comprises clock generator, I
2C controller, time schedule controller, even field detector, input FIFO writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller, progressive scanned video controller, LVDS interface controller, clock generator produces the clock of different frequency by phaselocked loop and is connected with SDRAM-FIFO controller, progressive scanned video controller, LVDS interface controller respectively, time schedule controller respectively with clock generator, I
2C controller, even field detector, SDRAM-FIFO controller, output FIFO Read Controller, LVDS interface controller connect, input FIFO writing controller, luminance processor, input fifo module, SDRAM-FIFO controller, output fifo module, output FIFO Read Controller order connect step by step, output FIFO Read Controller is connected I with progressive scanned video controller, LVDS interface controller
2Interlaced video signal in the C controller identification interlaced video load module, time schedule controller notify even field detector to send even field mark signal to input FIFO writing controller, and time schedule controller is according to I
2The situation of C controller configuration interlaced video load module opens or closes the switch of progressive scanned video controller and LVDS interface controller.
3. the LCD driver at the high resolving power interlaced video signal as claimed in claim 2 is characterized in that, the work of the synchronous SDRAM-FIFO controller of described clock generator, progressive scanned video controller, LVDS interface controller.
4. the LCD driver at the high resolving power interlaced video signal as claimed in claim 2 is characterized in that, described clock generator, I
2C controller, time schedule controller common clock also are connected input FIFO writing controller and I with crystal oscillator
2The C controller is connected with the interlaced video load module with control bus by data bus respectively, the luminance processor module also is connected with the brilliance control module, the SDRAM-FIFO controller also is connected with the SDRAM storer, the progressive scanned video controller also is connected with the progressive output module, and the LVDS interface controller also is connected with LVDS liquid crystal display logic card interface module.
5. the LCD driver at the high resolving power interlaced video signal as claimed in claim 2, it is characterized in that, described luminance processor comprises the RGB/YUV converter, counter, multiplier and YUV/RGB converter, the RGB/YUV converter is connected with multiplier by the Y data bus, the RGB/YUV converter is connected with the YUV/RGB converter with the V data bus by the U data bus, counter is connected with multiplier and exports luminance control data and give multiplier, multiplier is connected with the YUV/RGB converter, and multiplier sends brightness Y data and luminance control data multiplied result high eight-bit data to the YUV/RGB converter.
6. the LCD driver at the high resolving power interlaced video signal as claimed in claim 5, it is characterized in that, described RGB/YUV converter also is connected with input FIFO writing controller, counter also is connected with the brilliance control module and receives voltage and the frequency signal that the brilliance control module produces, and the YUV/RGB converter also is connected with the input fifo module.
7. the LCD driver at the high resolving power interlaced video signal as claimed in claim 2, it is characterized in that, described SDRAM-FIFO controller comprises the SDRAM clock, interlacing SDRAM page or leaf counter, input staggered scanning linage-counter, interlacing SDRAM row address generator, input FIFO Read Controller, sdram controller, output FIFO writing controller, SDRAM row address generator line by line, export the linage-counter of lining by line scan, SDRAM page or leaf counter line by line, sdram controller and SDRAM clock, interlacing SDRAM row address generator, SDRAM row address generator connects line by line, interlacing SDRAM page or leaf counter is connected with input staggered scanning linage-counter, input staggered scanning linage-counter also respectively with interlacing SDRAM row address generator, input FIFO Read Controller connects, SDRAM page or leaf counter and the output linage-counter of lining by line scan is connected line by line, output line by line scan linage-counter respectively with SDRAM row address generator line by line, output FIFO writing controller connects, the SDRAM clock provides synchronous clock, interlacing SDRAM row address generator writes the SDRAM storer with interlaced video signal, and SDRAM row address generator is read interlaced video signal from the SDRAM storer line by line.
8. the LCD driver at the high resolving power interlaced video signal as claimed in claim 7, it is characterized in that, described input FIFO Read Controller also is connected with the input fifo module, output FIFO writing controller also is connected with the output fifo module, sdram controller also is connected with the SDRAM storer with time schedule controller respectively, and the SDRAM clock also is connected with clock generator.
9. the LCD driver at the high resolving power interlaced video signal as claimed in claim 7 is characterized in that, described sdram controller adopts the mode of burst page or leaf read-write.
10. the LCD driver at the high resolving power interlaced video signal as claimed in claim 1 is characterized in that, the brightness that described potentiometer interface sends is adjusted voltage and also is sent to a liquid crystal panel interface to adjust backlight illumination.
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| CN 201010104667 CN102142236B (en) | 2010-02-03 | 2010-02-03 | Liquid crystal display driver for high-resolution interlacing scanned video signals |
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| CN103794189A (en) * | 2014-02-27 | 2014-05-14 | 刘兴宾 | Liquid crystal display panel sequential control module |
| CN104575442A (en) * | 2014-12-23 | 2015-04-29 | 深圳市思乐数据技术有限公司 | Video signal conversion and expansion method and circuit |
| CN106210592A (en) * | 2016-08-17 | 2016-12-07 | 天津市英贝特航天科技有限公司 | A kind of VGA turns the video conversion circuit of LVDS |
| CN107342055A (en) * | 2017-07-21 | 2017-11-10 | 天津大学 | A kind of region backlight quickly regulating method for interlaced scanning video |
| CN108257566A (en) * | 2018-01-23 | 2018-07-06 | 深圳市华星光电技术有限公司 | Source electrode drive circuit and liquid crystal display drive circuit |
| CN109413356A (en) * | 2018-12-10 | 2019-03-01 | 厦门视诚科技有限公司 | A kind of HDMI high image quality synchronization de interlacing system and method |
| CN110704008A (en) * | 2019-09-30 | 2020-01-17 | 联想(北京)有限公司 | Data reading and writing method and device |
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| US6078361A (en) * | 1996-11-18 | 2000-06-20 | Sage, Inc | Video adapter circuit for conversion of an analog video signal to a digital display image |
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| CN107342055B (en) * | 2017-07-21 | 2019-03-22 | 天津大学 | A kind of region backlight quickly regulating method for interlaced scanning video |
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| CN111240582A (en) * | 2018-11-29 | 2020-06-05 | 长鑫存储技术有限公司 | Data reading and writing method, reading and writing device and dynamic random access memory |
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| CN109413356B (en) * | 2018-12-10 | 2023-08-01 | 厦门视诚科技有限公司 | HDMI high-image-quality synchronous de-interlacing system and method |
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| CN113903287A (en) * | 2021-12-09 | 2022-01-07 | 中国电子科技集团公司第十五研究所 | Display driving board |
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