CN100556119C - A kind of video format converter based on FPGA - Google Patents
A kind of video format converter based on FPGA Download PDFInfo
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- CN100556119C CN100556119C CNB2007100437795A CN200710043779A CN100556119C CN 100556119 C CN100556119 C CN 100556119C CN B2007100437795 A CNB2007100437795 A CN B2007100437795A CN 200710043779 A CN200710043779 A CN 200710043779A CN 100556119 C CN100556119 C CN 100556119C
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Abstract
The present invention relates to a kind of video format converter based on FPGA.With FPGA is kernel processor chip, is aided with the outer SDRAM of A/D decoding chip, D/A chip and sheet, realizes Phase Alternation Line system analog video input (50Hz, 720*288, interlacing scan) to the format conversion of the output signal (75Hz, 1024*768 line by line scan) that can show for the VGA display.This transducer is integrated in conversion of frame frequency lifting, interlacing-line by line and resolution enlarging function in a slice FPGA, both realized the real-time conversion of video format, simultaneously because FPGA is able to programme, can customize IP kernel according to real needs, and can carry out system upgrade and expansion easily, realize more function with minimum input.Compare with existing format converter and to have very big flexibility and very high cost performance.
Description
Technical field
The present invention relates to a kind of video format converter, more particularly, relate to and a kind ofly be used to realize interlaced video signal is carried out the transducer that the conversion of frame frequency lifting, interlacing-line by line and resolution are amplified based on FPGA.Belong to electronic information field.
Background technology
Digital video Display Technique fast development is in recent years lined by line scan, large-size screen monitors, high definition show gradually and promote.And traditional interlaced scanning video still is widely used in the middle of daily life, work.Therefore, interlaced video signal is converted to the video format that novel display unit is supported, the very big market space is arranged.Conversion method of a lot of interlacing-line by line and device arise at the historic moment.
Investigate through coordinate indexing, traditional interlacing-conversion all is to realize with special chip line by line, and just inevitably there is the shortcoming that autgmentability is poor, upgrading is difficult, the construction cycle is long, cost is high in this.On the other hand, the field programmable device (FPGA) that occur the nineties in 20th century, its design is convenient, flexible, construction cycle is short, can customize IP kernel as required, be easy to upgrading, expansion, continuous lifting along with performance, become possibility based on FPGA design embedded system, programmable system on chip (S0PC) notion proposes thereupon, meanwhile, power consumption, the price of FPGA descend year by year, have seized the market share of traditional microprocessing unit (MCU) and standard digital logical circuit (ASSP) gradually.
Summary of the invention
The objective of the invention is to defective, a kind of video format converter based on FPGA is provided at the prior art existence.With FPGA is kernel processor chip, and video processing technique is combined with the FPGA technology, both can realize the real-time conversion of video format, can customize different IP kernels again, satisfies more functional requirements more specifically, has improved cost performance.While can also be realized more complicated processing procedure along with the FPGA performance improves constantly, and makes converter function more perfect.
For achieving the above object, the present invention adopts following technical proposals:
A kind of video format converter based on FPGA is by active crystal oscillator, the power conversion module, FPGA, DLL (dynamic link library) and local control interface, FLASH, the outer SDRAM group of sheet (3), video input module and video output module are formed, its interconnected relationship is: the power conversion module respectively with active crystal oscillator, FPGA, FLASH, the outer SDRAM group of sheet, DLL (dynamic link library), video input module, the video output module is connected, FPGA links to each other with FLASH, link to each other with three SDRAM in the outer SDRAM group of sheet respectively by the SDRAM bus, video input module links to each other with FPGA, the video output module links to each other with FPGA, active crystal oscillator links to each other with FPGA, and DLL (dynamic link library) links to each other with FPGA with local control interface.
Above-mentioned FPGA comprises synchronizing signal controller, read-write state controller, i
2C controller, sdram controller, RAM controller, ram in slice group, YUV/RGB transducer.Its inner interconnected relationship is: described read-write state controller by Internal Control Bus IBC respectively with synchronizing signal controller, sdram controller, RAM controller, YUV/RGB transducer, i
2The c controller links to each other; Described RAM controller links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with the YUV/RGB transducer with sdram controller respectively by internal data bus, links to each other with the ram in slice group by internal data bus, address bus and control bus.
The external annexation of inner each module of above-mentioned FPGA is: external video input module of described synchronizing signal controller and active crystal oscillator; The external video input module of described sdram controller, three SDRAM during the outer SDRAM of outer contact pin organizes respectively by the SDRAM bus simultaneously; Described i
2The c controller passes through i
2External video input module of c bus and video output module; Described YUV/RGB transducer is by the external video output module of system data bus.
Above-mentioned RAM controller comprise multichannel selection control a, multichannel selection control b, multichannel selection control c, field interpolation device, between interpolation and motion detector, vertically amplify interpolation device.
Above-mentioned ram in slice group comprises RAM1, RAM2, RAM3, RAM4, RAM5, wherein RAM1, RAM2, RAM3, RAM4 are the input and output separating controlling, capacity is the ram in slice of 16X720Bits, and RAM5 is the input and output separating controlling, and capacity is the ram in slice of 17X720Bits.
Above-mentioned RAM controller, its inner interconnected relationship is: described field interpolation device is by receiving data from multichannel selection control a through later 8 the brightness data bus Yin ' of a line delay with through 8 later chroma data bus Cin ' of a line delay, with the data input port of transfer of data, receive data by 8 brightness data bus Ys and 8 chroma data bus Cs from multichannel selection control c by 8 brightness data bus Yin when the pre-treatment field to multichannel selection control b; Described vertical amplification interpolation device is by receiving data from multichannel selection control a through later 8 the brightness data bus Yin ' of a line delay with through 8 later chroma data bus Cin ' of a line delay, receives data from multichannel selection control b by 8 bit data bus Yso and 8 bit data bus Cso; Described multichannel selection control c by when 8 chroma data bus Cin of pre-treatment field, when 8 brightness data bus Yin of pre-treatment field with the data input port of transfer of data to multichannel selection control a, by when 8 brightness data bus Yin of pre-treatment field with the data input port of transfer of data to the field interpolation device.
Above-mentioned RAM controller, the external annexation of its inner each module is: described multichannel selection control a links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with RAM2 with RAM1 respectively by internal RAM data, address, control bus; Described multichannel selection control b links to each other with the read-write state controller by Internal Control Bus IBC, link to each other with RAM4 with RAM3 respectively by internal RAM data, address, control bus, receive data by 8 bit data bus Yo ', 8 bit data bus Co ', 1 bit data bus Flag ', by reading address bus, reading control bus and be connected with RAM5 from RAM5 read data mouth; Described multichannel selection control c links to each other with the read-write state controller by Internal Control Bus IBC, by 8 bit data bus YinH, 8 bit data bus CinH, 8 bit data bus YinL and the 8 bit data bus CinL reception data from sdram controller; Interpolation and motion detector are by 8 bit data bus YinH, 8 bit data bus CinH, 8 bit data bus YinL and the 8 bit data bus CinL reception data from sdram controller between described, by 8 bit data bus Yo, 8 bit data bus Co, 1 bit data bus Flag data are delivered to the write data inlet of RAM5, by the write address bus, write control bus and be connected with RAM5; Described vertical amplification interpolation device links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with the YUV/RGB transducer by 16 bit data bus.
Above-mentioned field interpolation device comprises input as 8 brightness data bus Yin of pre-treatment field, through the Yin ' input of 8 later brightness data buses of a line delay, through the input of 8 later chroma data bus Cin ' of a line delay and the output of 8 brightness data bus Ys, the output of 8 brightness data bus Cs.When 8 brightness data bus Yin of pre-treatment field with input to one 9 adders through 8 later brightness data bus Yin ' of a line delay, its output exports 8 brightness data bus Ys to through the 1 back least-significant byte that moves to left; 8 the chroma data bus Cins ' later through a line delay directly export 8 chroma data bus Cs to.
Interpolation and motion detector comprise the input of 8 bit data bus YinH, the input of 8 bit data bus CinH, the input of 8 bit data bus YinL, the input of 8 bit data bus CinL and the output of 8 bit data bus Yo, the output of 8 bit data bus Co, the output of 1 bit data bus Flag between above-mentioned.8 bit data bus CinH and 8 bit data bus CinL input to one 9 adders, and least-significant byte exports 8 bit data bus Co to after 1 through moving to left in its output; 8 bit data bus YinH and 8 bit data bus YinL input to one 9 adders, and least-significant byte exports 8 bit data bus Yo to after 1 through moving to left in its output; 8 bit data bus YinH and 8 bit data bus YinL input to one 9 the symbol subtracter, and its output is passed through to take absolute value and exported 1 bit data bus Flag to the relatively back result of decision threshold again, and motion detection result is represented in the output of 1 bit data bus Flag.
Above-mentioned vertical amplification interpolation device comprises read-write state controller input Sync, through the input of 8 later brightness data bus Yin ' of a line delay, through a line delay later 8 chroma data bus Cin ' inputs, the input of 8 bit data bus Yso, the input of 8 bit data bus Cso and the outputs of 8 bit data bus Yout, output and 1 MUX M of 8 bit data bus Cout; 8 the brightness data bus Yins ' later through a line delay input to one 9 adders with 8 bit data bus Yso, and its output exports the data input pin of MUX M to through the least-significant byte after 1 of moving to left; Input to one 10 adders through later 8 brightness data bus Yin ' of a line delay and 1 the result of moving to right through 8 later brightness data bus Yin ' of a line delay, together import one 11 adders with 8 bit data bus Yso again, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Move to right 1 result of 8 bit data bus Yso and 8 bit data bus Yso inputs to one 10 adders, together import one 11 adders again with through 8 later brightness data bus Yin ' of a line delay, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Directly export the data input pin of MUX M to through 8 later brightness data bus Yin ' of a line delay; 8 bit data bus Yso directly export the data input pin of MUX M to; 8 the chroma data bus Cins ' later through a line delay input to one 9 adders with 8 bit data bus Cso, and its output exports the data input pin of MUX M to through the least-significant byte after 1 of moving to left; Input to one 10 adders through later 8 chroma data bus Cin ' of a line delay and 1 the result of moving to right through 8 later chroma data bus Cin ' of a line delay, together import one 11 adders with 8 bit data bus Cso again, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Move to right 1 result of 8 bit data bus Cso and 8 bit data bus Cso inputs to one 10 adders, together import one 11 adders again with through 8 later chroma data bus Cin ' of a line delay, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Directly export the data input pin of MUX M to through 8 later chroma data bus Cin ' of a line delay; 8 bit data bus Cso directly export the data input pin of MUX M to; The control end of MUX M receives the input Sync of read-write state controller, and output is connected to 8 bit data bus Yout and 8 bit data bus Cout.
It is kernel processor chip that above-mentioned FPGA adopts large-scale F PGA chip EP1C12F324C8.
Above-mentioned FLASH adopts the EPCS4 chip.
Above-mentioned video input module adopts the SAA7114 video decoding chip.
Above-mentioned video output module adopts ADV7197 video analog-digital chip.
Above-mentioned outer SDRAM group (3) adopts 3 capacity to be 64MBits, and bit wide is 32 SDRAM storage chip.
Above-mentioned its frequency of oscillation of active crystal oscillator is 50MHz.
The present invention compares with existing correlation technique, has following advantage:
1. realize comprising the real-time conversion of the video format that conversion of frame frequency lifting, interlacing-line by line and resolution are amplified at lower cost, had high cost performance.2. can customize different IP kernels according to concrete functional requirement, but design achievement flexmux.3.FPGA programmability make system possess sizable extensibility.4. the design portable of preserving with the hardware description language form is in different fpga chips, and along with improving constantly of FPGA performance, system can also realize more complicated processing procedure, thereby makes converter function more perfect.
Description of drawings
Fig. 1 system configuration schematic diagram.
Fig. 2 FPGA internal structure block diagram.
Fig. 3 RAM controller internal structure schematic diagram.
Fig. 4 field interpolation device internal structure schematic diagram.
Interpolation and motion detector internal structure schematic diagram between Fig. 5 field.
Fig. 6 vertically amplifies interpolation device internal structure schematic diagram.
Embodiment
Below in conjunction with accompanying drawing a preferred embodiment of the present invention is described in detail.
This mainly comprises the fpga core process chip, video input module, video output module and three outer SDRAM groups of sheet that SDRAM constitutes based on the system configuration of the video format converter of FPGA as shown in Figure 1.FPGA adopts the EP1C12F324C8 chip in the present embodiment, and video input module adopts the SAA7114H video decoding chip, and the video output module adopts ADV7197 video analog-digital chip, and three SDRAM all adopt the SDRAM storage chip of 64MBits32 position.Video input module is with the Phase Alternation Line system of video input interface input, 50Hz, 720X288, interleaved analog video signal carries out synchronizing signal to be separated, and luminance chrominance signal separates, and is 16 YUV4:2:2 with analog signal conversion, 50Hz, 720X288, interleaved digital signal is delivered to FPGA simultaneously with isolated field sync signal, line synchronizing signal, 27MHz dot frequency signal, parity field marking signal; FPGA passes through i as kernel processor chip
2The c bus initialization is also adjusted video input module and the concrete parameter of video output module, reception is from 16 the YUV4:2:2 signals and the synchronizing signal of video input module, outer SDRAM organizes as a buffer memory with sheet, and with the ram in slice group as row cache, interlacing scan digital video signal to input carries out frame frequency lifting, interlacing-conversion line by line, three kinds of processing of resolution amplification, and be converted to 24 RGB4:4:4 forms, together deliver to the video output module with inner, the field sync signal synchronous that produces of FPGA then for the row that shows usefulness; The video output module receives the RGB4:4:4 digital video after format conversion, carries out delivering to video output interface confession VGA display with 75Hz after the digital to analog conversion, and 1024*768, progressive-scan format shows.
The outer SDRAM group of sheet is as (frame) buffer memory, and rationally the be arranged in conversion of frame frequency lifting, interlacing-line by line and the resolution of its read-write blocked operation all play crucial effects in amplifying.FPGA receives 16 YUV4:2:2 from video input module, the digital video signal of 50Hz, by capable field synchronization of 50Hz and 27MHz Dot Clock that video input module provided it is write the outer SDRAM of three sheets in turn, with the 75Hz display synchronization of synchronizing signal controller generation and the 50MHz Dot Clock of crystal oscillator deposited vision signal is read in turn simultaneously, for further processing, write field is 50Hz synchronously, reading field synchronization is 75Hz, become 2: 3 ratios, therefore adopt first to read twice, second reads through, Xun Huan reading method according to this, reach the effect of 2: 3 frame frequency liftings, interlacing-adopt adaptively selected interior still mode of interpolation between the field of motion detection in the transfer process line by line, to need when the front court interpolation previous field and after one data, therefore every SDRAM deposits continuous four video datas, three in turn, when the SDRAM of anter deposit the 4th with the SDRAM of following a slice deposit first identical, circulation according to this, for every SDRAM, there are low 16 of strange row in the strange field data that arrives earlier, there are low 16 of idol row in the even field data that arrives earlier, there be the high 16 of strange row in the strange field data that the back arrives, there be the high 16 of idol row in the even field data that the back arrives, and when computing, 32 bit data are read simultaneously, can be that the interpolation computing provides great convenience between the field.
Referring to Fig. 2, fpga core process chip inside is by synchronizing signal controller, read-write state controller, i
2C controller, sdram controller, RAM controller, ram in slice group, YUV/RGB transducer are formed.Row, field sync signal, 27MHz Dot Clock and the parity field marking signal of synchronizing signal controller receiver, video input module, and, offer the read-write state controller after handling from the 50MHz inter-process reference clock signal of external crystal-controlled oscillation; The read-write state controller generates the required read-write control clock signal of each module according to the specific requirement of transfer algorithm, totally controls the read-write operation sequential of each module in the FPGA; i
2The c controller passes through i
2The c bus makes its parameter compliance with system requirement to video input module and the transfer control instruction of video output module; Sdram controller receives the 50Hz interlaced digital video data from video input module, receive the read-write state control command of read-write state controller simultaneously, respectively the outer SDRAM of three sheets is carried out read-write operation according to read-write state, realize the frame frequency lifting of video data 50Hz, and provide 32 interpolation data for the conversion of interlacing-line by line and resolution amplification to 75Hz; 32 interpolation data that the RAM controller receives that sdram controller transmits are also carried out interpolation arithmetic to it, realize interlacing-conversion and resolution amplification line by line, with 16 interpolated data deliver to the YUV/RGB transducer; Row cache during the ram in slice group is amplified as the conversion of interlacing-line by line and resolution is accepted the full powers of RAM controller and is controlled; The YUV/RGB transducer with 16 interpolated data be converted to 24 RGB4:4:4 forms and deliver to the video output module and be for further processing.
RAM controller in the FPGA and ram in slice group are as shown in Figure 3, the RAM controller comprise multichannel selection control a, multichannel selection control b, multichannel selection control c, field interpolation device, between interpolation and motion detector and vertically amplify interpolation device, the ram in slice group comprises RAM1, RAM2, RAM3, RAM4, RAM5, wherein RAM1, RAM2, RAM3, RAM4's is the input and output separating controlling, capacity is the ram in slice of 16X720Bits, RAM5 is the input and output separating controlling, and capacity is the ram in slice of 17X720Bits.The interpolation arithmetic process mainly is divided into the conversion of interlacing-line by line and resolution is amplified conversion two parts.The conversion of interlacing-line by line adopt field interpolation and between the interpolation two-way carry out simultaneously, the result according to motion detection between the field determines to adopt any interpolation result again.Resolution is amplified because the horizontal Dot Clock that only needs to change reading of data that amplifies gets final product simple realization, so only interpolation is carried out in vertical amplification, every 288 line data is through interlacing-the conversion interpolation is 576 row line by line, and output needs 768 row, abbreviation was 3: 4 in 576: 768, and the method interpolation that only needs proportionally adjacent lines in the data of 576 row to be carried out the weights addition can draw 768 row.Specifying of interior each module of RAM controller: it (is that RAM1 RAM2 when reading is writing that multichannel selection control a control RAM1 and RAM2 read and write by turns, RAM2 RAM1 when reading is writing, the conflict that produces to avoid read-write operation to take place simultaneously in the same address with a slice RAM); Multichannel selection control b control RAM3 and RAM4 read and write by turns; Multichannel selection control c sends high 16 (comprising 8 bit data bus YinH and 8 bit data bus CinH) still low 16 (comprising 8 bit data bus YinL and 8 bit data bus CinL) according to the field sequence decision when pre-treatment of read-write clock; Inside in the interpolation device, when 8 brightness data Yin of pre-treatment field with carry out the field interpolation computing through 8 later brightness data Yin ' of a line delay, colourity then directly adopts 8 chroma data Cin ' behind the line delay, after the interpolation, the data input pin that 8 brightness data Ys and 8 chroma data Cs deliver to multichannel selection control b is treated gating; On the other hand, interpolation is carried out interpolation and motion detection between the field with motion detector to 32 bit data (comprising two two point data that middle position is identical) of input between, gained 16 bit data (comprising 8 bit data bus Yo and eight bit data bus Co) and motion detection result Flag make buffering in RAM5 after, 8 bit data bus Yo ', 8 bit data bus Co ' deliver to the data input pin of multichannel selection control b and treat gating, and Flag ' delivers to the defeated decision of the control gating result of multichannel selection control b; 8 bit data bus Yso, 8 bit data bus Cso after the interpolation of interlacing-line by line and the initial data before the interpolation (8 brightness data Yin ' and 8 later chroma data Cin ' of a line delay that a line delay is later) together are sent to vertical amplification interpolation device, capable ordinal number according to current interpolation row is selected different interpolation weights, and interpolation result is delivered to the YUV/RGB transducer.
The structure of field interpolation device is asked on average (addition removes 2) with the brightness of going in the front and back two of input as shown in Figure 4, and colourity is straight-through.Interpolation and motion detector are as shown in Figure 5 between, the output of brightness and colourity is the corresponding data of two position identical points and asks average, motion detection then is that absolute value and the decision threshold of getting above-mentioned luminance difference at 2 are made comparisons, difference then is judged to motion greater than thresholding, give court verdict Flag with 1 tax, otherwise compose to court verdict Flag 0.Vertically the structure of amplification interpolation device is made same treatment to brightness and colourity of input at 2 as shown in Figure 6.Input value is 8 later brightness data bus Yin ' of a line delay, 8 bit data bus Yso, 8 chroma data bus Cin ' that a line delay is later, 8 bit data bus Cso; Output valve is 8 bit data bus Yout and 8 bit data bus Cout.Then have respectively
Yout＝Yin’/2+Yso/2，Cout＝Cin’/2+Cso/2；
Yout＝Yin’*3/4+Yso*1/4，Cout＝Cin’*3/4+Cso*1/4；
Yout＝Yin’*1/4+Yso*3/4，Cout＝Cin’*1/4+Cso*3/4；
Yout＝Yin’，Cout＝Cin’；
Yout＝Yso，Cout＝Cso
Which kind of mode five kinds of weights average modes specifically adopt then select according to the capable preface of current interpolation row.
Claims (4)
1. video format converter based on FPGA, it is characterized in that: by active crystal oscillator, the power conversion module, FPGA, DLL (dynamic link library) and local control interface, FLASH, 3 outer SDRAM groups of sheet, video input module and video output module are formed, its interconnected relationship is: the power conversion module respectively with active crystal oscillator, FPGA, FLASH, the outer SDRAM group of sheet, DLL (dynamic link library), video input module, the video output module is connected, FPGA links to each other with FLASH, link to each other with three SDRAM in the outer SDRAM group of sheet respectively by the SDRAM bus, video input module links to each other with FPGA, the video output module links to each other with FPGA, active crystal oscillator links to each other with FPGA, and DLL (dynamic link library) links to each other with FPGA with local control interface; Described FPGA comprises synchronizing signal controller, read-write state controller, i
2C controller, sdram controller, RAM controller, ram in slice group and YUV/RGB transducer; Its inner interconnected relationship is: described read-write state controller by Internal Control Bus IBC respectively with synchronizing signal controller, sdram controller, RAM controller, YUV/RGB transducer, i
2The c controller links to each other; Described RAM controller links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with the YUV/RGB transducer with sdram controller respectively by internal data bus, links to each other with the ram in slice group by internal data bus, address bus and control bus; The external annexation of inner each module of described FPGA is: external video input module of described synchronizing signal controller and active crystal oscillator; The external video input module of described sdram controller, three SDRAM during the outer SDRAM of outer contact pin organizes respectively by the SDRAM bus simultaneously; Described i
2The c controller passes through i
2External video input module of c bus and video output module; Described YUV/RGB transducer is by the external video output module of system data bus; Described RAM controller comprise multichannel selection control a, multichannel selection control b, multichannel selection control c, field interpolation device, between interpolation and motion detector, vertically amplify interpolation device; Described ram in slice group comprises RAM1, RAM2, RAM3, RAM4, RAM5, wherein RAM1, RAM2, RAM3, RAM4's is characterized as the input and output separating controlling, capacity is the ram in slice of 16 * 720Bits, RAM5 is characterized as the input and output separating controlling, and capacity is the ram in slice of 17 * 720Bits; The inside interconnected relationship of described RAM controller is: described field interpolation device is by receiving data from multichannel selection control a through later 8 the brightness data bus Yin ' of a line delay with through 8 later chroma data bus Cin ' of a line delay, with the data input port of transfer of data, receive data by 8 brightness data bus Ys and 8 chroma data bus Cs from multichannel selection control c by 8 brightness data bus Yin when the pre-treatment field to multichannel selection control b; Described vertical amplification interpolation device is by receiving data from multichannel selection control a through later 8 the brightness data bus Yin ' of a line delay with through 8 later chroma data bus Cin ' of a line delay, receives data from multichannel selection control b by 8 bit data bus Yso and 8 bit data bus Cso; Described multichannel selection control c by when 8 chroma data bus Cin of pre-treatment field, when 8 brightness data bus Yin of pre-treatment field with the data input port of transfer of data to multichannel selection control a, by when 8 brightness data bus Yin of pre-treatment field with the data input port of transfer of data to the field interpolation device; The inside of the described RAM controller external annexation of each module is: described multichannel selection control a links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with RAM2 with RAM1 respectively by internal RAM data, address, control bus; Described multichannel selection control b links to each other with the read-write state controller by Internal Control Bus IBC, link to each other with RAM4 with RAM3 respectively by internal RAM data, address, control bus, receive data by 8 bit data bus Yo ', 8 bit data bus Co ', 1 bit data bus Flag ', by reading address bus, reading control bus and be connected with RAM5 from RAM5 read data mouth; Described multichannel selection control c links to each other with the read-write state controller by Internal Control Bus IBC, by 8 bit data bus YinH, 8 bit data bus CinH, 8 bit data bus YinL and the 8 bit data bus CinL reception data from sdram controller; Interpolation and motion detector are by 8 bit data bus YinH, 8 bit data bus CinH, 8 bit data bus YinL and the 8 bit data bus CinL reception data from sdram controller between described, by 8 bit data bus Yo, 8 bit data bus Co, 1 bit data bus Flag data are delivered to the write data inlet of RAM5, by the write address bus, write control bus and be connected with RAM5; Described vertical amplification interpolation device links to each other with the read-write state controller by Internal Control Bus IBC, links to each other with the YUV/RGB transducer by 16 bit data bus.
2. the video format converter based on FPGA according to claim 1, it is characterized in that described field interpolation device comprise input as 8 brightness data bus Yin of pre-treatment field, through the input of 8 later brightness data bus Yin ' of a line delay, through the input of 8 later chroma data bus Cin ' of a line delay and the output of 8 brightness data bus Ys, the output of 8 chroma data bus Cs; When 8 brightness data bus Yin of pre-treatment field with input to one 9 adders through 8 later brightness data bus Yin ' of a line delay, its output exports 8 brightness data bus Ys to through the 1 back least-significant byte that moves to left; 8 the chroma data bus Cins ' later through a line delay directly export 8 chroma data bus Cs to.
3. the video format converter based on FPGA according to claim 2, it is characterized in that described between interpolation and motion detector comprise the input of 8 bit data bus YinH, the input of 8 bit data bus CinH, the input of 8 bit data bus YinL, the input of 8 bit data bus CinL and the output of 8 bit data bus Yo, the output of 8 bit data bus Co, the output of 1 bit data bus Flag; 8 bit data bus CinH and 8 bit data bus CinL input to one 9 adders, and least-significant byte exports 8 bit data bus Co to after 1 through moving to left in its output; 8 bit data bus YinH and 8 bit data bus YinL input to one 9 adders, and least-significant byte exports 8 bit data bus Yo to after 1 through moving to left in its output; 8 bit data bus YinH and 8 bit data bus YinL input to one 9 the symbol subtracter, and its output is passed through to take absolute value and exported 1 bit data bus Flag to the relatively back result of decision threshold again; Motion detection result is represented in the output of 1 bit data bus Flag.
4. the video format converter based on FPGA according to claim 2, it is characterized in that described vertical amplification interpolation device comprise read-write state controller input Sync, through the input of 8 later brightness data bus Yin ' of a line delay, through a line delay later 8 chroma data bus Cin ' inputs, the input of 8 bit data bus Yso, the input of 8 bit data bus Cso and the outputs of 8 bit data bus Yout, output and 1 MUX M of 8 bit data bus Cout; 8 the brightness data bus Yins ' later through a line delay input to one 9 adders with 8 bit data bus Yso, and its output exports the data input pin of MUX M to through the least-significant byte after 1 of moving to left; Input to one 10 adders through later 8 brightness data bus Yin ' of a line delay and 1 the result of moving to right through 8 later brightness data bus Yin ' of a line delay, together import one 11 adders with 8 bit data bus Yso again, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Move to right 1 result of 8 bit data bus Yso and 8 bit data bus Yso inputs to one 10 adders, together import one 11 adders again with through 8 later brightness data bus Yin ' of a line delay, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Directly export the data input pin of MUX M to through 8 later brightness data bus Yin ' of a line delay; 8 bit data bus Yso directly export the data input pin of MUX M to; 8 the chroma data bus Cins ' later through a line delay input to one 9 adders with 8 bit data bus Cso, and its output exports the data input pin of MUX M to through the least-significant byte after 1 of moving to left; Input to one 10 adders through later 8 chroma data bus Cin ' of a line delay and 1 the result of moving to right through 8 later chroma data bus Cin ' of a line delay, together import one 11 adders with 8 bit data bus Cso again, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Move to right 1 result of 8 bit data bus Cso and 8 bit data bus Cso inputs to one 10 adders, together import one 11 adders again with through 8 later chroma data bus Cin ' of a line delay, its output exports the data input pin of MUX M to through the least-significant byte after 2 of moving to left; Directly export the data input pin of MUX M to through 8 later chroma data bus Cin ' of a line delay; 8 bit data bus Cso directly export the data input pin of MUX M to; The control end of MUX M receives the input Sync of read-write state controller, and output is connected to 8 bit data bus Yout and 8 bit data bus Cout.
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Assignee: Jiaxing Ouma Health Technology Co., Ltd. Assignor: Shanghai University|Shanghai top Audio Visual Engineering Research Center Co Ltd Contract record no.: 2010310000066 Denomination of invention: FPGA based video format converter Granted publication date: 20091028 License type: Exclusive License Open date: 20080102 Record date: 20100518 |
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