CN102136430A - Semiconductor encapsulating structure and manufacturing method thereof - Google Patents
Semiconductor encapsulating structure and manufacturing method thereof Download PDFInfo
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- CN102136430A CN102136430A CN 201010118978 CN201010118978A CN102136430A CN 102136430 A CN102136430 A CN 102136430A CN 201010118978 CN201010118978 CN 201010118978 CN 201010118978 A CN201010118978 A CN 201010118978A CN 102136430 A CN102136430 A CN 102136430A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to a semiconductor encapsulating structure and a manufacturing method thereof. The semiconductor encapsulating structure comprises a substrate, a fist metal layer, a first dielectric layer, a first upper electrode and a first protective layer, wherein the first metal layer is positioned on a first surface of the substrate and comprises a first inductor and a first lower electrode; the first dielectric layer is positioned on the first lower electrode; the first upper electrode is positioned on the first dielectric layer; the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and the first protective layer covers the first inductor and the first capacitor. By adopting the method, the first inductor and the first lower electrode of the first capacitor are positioned on the same layer, so that the thickness of a product can be reduced.
Description
Technical field
The present invention in detail, is semiconductor package and a manufacture method thereof of integrating passive component about a kind of about a kind of semiconductor package and manufacture method thereof.
Background technology
With reference to figure 1, show the generalized section of known semiconductor encapsulating structure.This known semiconductor encapsulating structure 1 comprises a substrate 11, an encapsulation unit 12 and an adhesive body 13.This encapsulation unit 12 comprises several passive component (not shown).This encapsulation unit 12 is positioned on this substrate 11, and is electrically connected to this substrate 11.This adhesive body 13 coats this encapsulation unit 12.
The shortcoming of this known semiconductor encapsulating structure 1 is as follows.These passive components earlier via the semiconductor process integration in this encapsulation unit 12, then, this encapsulation unit 12 is again in the routing mode, or cover the crystal type (not shown), be electrically connected to this substrate 11, cause technology that these passive components are integrated in this semiconductor package 1 complicated, and raise the cost.
Therefore, be necessary to provide a kind of semiconductor package and manufacture method thereof, to address the above problem.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor package, it may further comprise the steps: a base material (a) is provided; (b) form a first metal layer on this base material, this first metal layer comprises one first inductance and one first bottom electrode; (c) form one first dielectric layer and one first top electrode on this first bottom electrode, wherein this first dielectric layer is between this first top electrode and this first bottom electrode, and this first top electrode, this first dielectric layer and this first bottom electrode form one first electric capacity; Reach and (d) form one first protective layer, to coat this first inductance and this first electric capacity.
By this, first bottom electrode of this first inductance and first electric capacity forms simultaneously, and is positioned at same one deck, and reaches the effect of integrating several passive components, and promotes process efficiency.
The present invention provides a kind of semiconductor package in addition, and it comprises a base material, a first metal layer, one first dielectric layer, one first top electrode and one first protective layer.This base material has a first surface and a second surface.This first metal layer is positioned at the first surface of this base material, and comprises one first inductance and one first bottom electrode.This first dielectric layer is positioned on this first bottom electrode.This first top electrode is positioned on this first dielectric layer, and this first top electrode, this first dielectric layer and this first bottom electrode form one first electric capacity.This first protective layer coats this first inductance and this first electric capacity.
The present invention more provides a kind of semiconductor package, and it comprises a base material, a first metal layer, one first dielectric layer, one first top electrode and one first protective layer.This base material has a first surface, a second surface, at least one groove and at least one perforating holes structure, and this groove runs through this first surface and this second surface, and this perforating holes structure is positioned at this groove, and is revealed in this first surface and this second surface.This first metal layer is positioned at the first surface of this base material, and comprises one first inductance and one first bottom electrode, and this first metal layer directly contacts this perforating holes structure.This first dielectric layer is positioned on this first bottom electrode.This first top electrode is positioned on this first dielectric layer, and this first top electrode, this first dielectric layer and this first bottom electrode form one first electric capacity.This first protective layer coats this first inductance and this first electric capacity.
By this, first bottom electrode of this first inductance and this first electric capacity is positioned at on one deck, and can reduce product thickness.
Description of drawings
Fig. 1 shows the generalized section of known semiconductor encapsulating structure;
Fig. 2 to Figure 18 shows the schematic diagram of first embodiment of the manufacture method of semiconductor package of the present invention;
Figure 19 shows the generalized section of second embodiment of semiconductor package of the present invention;
Figure 20 to Figure 26 shows the schematic diagram of second embodiment of the manufacture method of semiconductor package of the present invention; And
Figure 27 to Figure 29 shows the schematic diagram of the 3rd embodiment of the manufacture method of semiconductor package of the present invention.
Embodiment
Referring to figs. 2 to Figure 19, the schematic diagram of first embodiment of the manufacture method of demonstration semiconductor package of the present invention.With reference to figure 2, provide a base material 21.In the present embodiment, this base material 21 comprises a first surface 211, a lower surface 212, at least one groove 213 and at least one conductive hole structure 217.This groove 213 is opened on the first surface 211 of this base material 21.This conductive hole structure 217 is positioned at this groove 213, and is revealed in the first surface 211 of this base material 21.
In the present embodiment, the material of this base material 21 is a non-insulating material, for example silicon or silica.This conductive hole structure 217 comprises an external insulation layer 2141, a conductor 2142 and an inner insulating layer 2143.This external insulation layer 2141 is positioned at the sidewall of this groove 213, defines one second central channel 2144, and this conductor 2142 is positioned at the sidewall of this second central channel 2144, defines one first central channel 2145, and this inner insulating layer 2143 fills up this first central channel 2145.Because the material of this base material 21 is a non-insulating material, so this external insulation layer 2141 is avoided branching to this base material 21 by the electric current of this conductive hole structure 217, and reduced the electrical effect of this conductive hole structure 217 in order to isolated this base material 21 and this conductor 2142.
Yet, in other is used, as shown in Figure 3, this conductive hole structure 217 can only comprise an external insulation layer 2141 and a conductor 2142, and do not comprise this inner insulating layer 2143 (Fig. 2), this external insulation layer 2141 is positioned at the sidewall of this groove 213, defines one second central channel 2144, and this conductor 2142 fills up this second central channel 2144.Moreover the material of this base material 21 can be insulating material, glass for example, and then this conductive hole structure 217 can not comprise this external insulation layer 2141 (Fig. 2).Therefore, as shown in Figure 4, this conductive hole structure 217 can only comprise a conductor 2142 and an inner insulating layer 2143, and this conductor 2142 is positioned at the sidewall and the bottom of this groove 213, define one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145.Perhaps, as shown in Figure 5, this conductive hole structure 217 only comprises a conductor 2142, and this conductor 2142 fills up this groove 213.With reference to figure 6, form one first insulating bottom layer 22 on this base material 21.In the present embodiment, this first insulating bottom layer 22 is positioned at the first surface 211 of this base material 21, and has one first perforation 221, and this first perforation 221 appears this conductive hole structure 217.
Then, form a first metal layer 23 (Fig. 9) on this base material 21, this first metal layer 23 comprises one first inductance 231 and one first bottom electrode 232.In the present embodiment, this first metal layer 23 is positioned on this first insulating bottom layer 22, and directly contacts this conductive hole structure 217.In the present embodiment, it is as described below to form the step of this first metal layer 23.With reference to figure 7, form one first crystal seed layer 233 on this base material 21.With reference to figure 8, form one first photoresistance 234 on this first crystal seed layer 233, with this first crystal seed layer 233 of cover part, and appear this first crystal seed layer 233 of part, and form one first electrodeposited coating 235 on quilt this first crystal seed layer 233 of part that appears.With reference to figure 9, this first crystal seed layer 233 of part that removes this first photoresistance 234 (Fig. 8) and be capped, this first crystal seed layer 233 of this first electrodeposited coating 235 and part forms this first metal layer 23.
Then, form one first dielectric layer 24 (Figure 11) and one first top electrode 25 (Figure 11) on this first bottom electrode 232.This first dielectric layer 24 is between this first top electrode 25 and this first bottom electrode 232, and this first top electrode 25, this first dielectric layer 24 and this first bottom electrode 232 form one first electric capacity 26 (Figure 11).In the present embodiment, it is as described below to form the step of this first dielectric layer 24.With reference to Figure 10, at first, form (for example sputter) one second metal level on this first bottom electrode 232, and this second metal level is carried out anodic oxidation, to form one first oxide layer 241.The material of this second metal level is that (Tantalum, Ta), the material of this first oxide layer 241 is tantalum pentoxide (Tantalum Pentoxide, Ta to tantalum
2O
5).Then, form (for example sputter) one the 3rd metal level 251 on this first oxide layer 241, the material of the 3rd metal level 251 is aluminum bronze (AlCu).At last, form one second photoresistance 261 on the 3rd metal level 251.With reference to Figure 11, remove this first oxide layer 241 (Figure 10) of part and part the 3rd metal level 251 (Figure 10), to form this first dielectric layer 24 and this first top electrode 25 respectively, form this first electric capacity 26 simultaneously, and remove this second photoresistance 261 (Figure 10).With reference to Figure 12, form one first protective layer 27, to coat this first inductance 231 and this first electric capacity 26.This first protective layer 27 comprises at least one first opening 271, and this first opening 271 appears this first metal layer 23 of part or this first top electrode 25 of part.
Then, form at least one first projection 28 (Figure 15) in first opening 271 of this first protective layer 27.In the present embodiment, it is as described below to form the step of this first projection 28.With reference to Figure 13, form one second crystal seed layer 281 on this first protective layer 27.With reference to Figure 14, form one the 3rd photoresistance 282 earlier on this second crystal seed layer 281, with this second crystal seed layer 281 of cover part, and appear this second crystal seed layer 281 of part, form one second electrodeposited coating 283 again on quilt this second crystal seed layer 281 of part that appears.With reference to Figure 15, this second crystal seed layer 281 of part that removes the 3rd photoresistance 282 and be capped is to form this first projection 28.
With reference to Figure 16, this base material 21 is set on a carrier 29, wherein the first surface 211 of this base material 21 is in the face of this carrier 29, and remove this base material 21 of part from the lower surface 212 (Figure 15) of this base material 21, to form a second surface 215, and the conductor 2142 that appears this conductive hole structure 217 (Figure 15) is in this second surface 215, to form a perforating holes structure 214.Yet, in other is used, can remove this base material 21 of more parts again, make the inner insulating layer 2143 of this conductive hole structure 217 (Figure 15) also be revealed in this second surface 215, be revealed in this second surface 215 to guarantee this conductor 2142.
With reference to Figure 17, form the second surface 215 of at least one electrical assembly in this base material 21.In the present embodiment, this electrical assembly is one second projection 31, and the manufacture method of this second projection 31 is with the manufacture method of this first projection 28, so repeat no more.With reference to Figure 18, remove this carrier 29, form first embodiment of semiconductor package 2 of the present invention.Yet this electrical assembly can be one second inductance 32 and one second electric capacity 33, as shown in figure 19.The manufacture method of this second inductance 32 and this second electric capacity 33, manufacture method with this first inductance 231 and this first electric capacity 26, that is the technology that the technology of being carried out in the second surface 215 of this base material 21 can be carried out with the first surface 211 in this base material 21 is identical, so repeat no more.
By this, first bottom electrode 232 of this first inductance 231 and this first electric capacity 26 forms simultaneously, and is positioned at same one deck, and reaches the effect of integrating several passive components, and promotes process efficiency.
With reference to Figure 18, show the generalized section of first embodiment of semiconductor package of the present invention again.This semiconductor package 2 comprises a base material 21, one first insulating bottom layer 22, one second insulating bottom layer 34, a first metal layer 23, one first dielectric layer 24, one first top electrode 25, one first protective layer 27, at least one first projection 28 and at least one electrical assembly.
This base material 21 has a first surface 211, a second surface 215, at least one groove 213 and at least one perforating holes structure 214.This groove 213 runs through this first surface 211 and this second surface 215, and this perforating holes structure 214 is positioned at this groove 213, and is revealed in this first surface 211 and this second surface 215.Yet in other was used, this base material 21 can not comprise this groove 213 and this perforating holes structure 214.
In the present embodiment, the material of this base material 21 is a non-insulating material, for example silicon or silica.This perforating holes structure 214 comprises an external insulation layer 2141, a conductor 2142 and an inner insulating layer 2143, this external insulation layer 2141 is positioned at the sidewall of this groove 213, define one second central channel 2144, this conductor 2142 is positioned at the sidewall of this second central channel 2144, define one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145.Because the material of this base material 21 is a non-insulating material, so this external insulation layer 2141 is avoided branching to this base material 21 by the electric current of this perforating holes structure 214, and reduced the electrical effect of this perforating holes structure 214 in order to isolated this base material 21 and this conductor 2142.
Yet, in other is used, this perforating holes structure 214 can only comprise an external insulation layer 2141 and a conductor 2142, and do not comprise this inner insulating layer 2143, this external insulation layer 2141 is positioned at the sidewall of this groove 213, define one second central channel 2144, this conductor 2142 fills up this second central channel 2144.Moreover, the material of this base material 21 can be insulating material, glass for example, and then this perforating holes structure 214 can not comprise this external insulation layer 2141, therefore, this perforating holes structure 214 can only comprise a conductor 2142 and an inner insulating layer 2143, and this conductor 2142 is positioned at the sidewall of this groove 213, defines one first central channel 2145, this inner insulating layer 2143 fills up this first central channel 2145, perhaps, this perforating holes structure 214 only comprises a conductor 2142, and this conductor 2142 fills up this groove 213.
This first insulating bottom layer 22 is positioned at the first surface 211 of this base material 21, and has one first perforation 221, and this first perforation 221 appears this perforating holes structure 214.This second insulating bottom layer 34 is positioned at the second surface 215 of this base material 21, and has one second perforation 341, and this second perforation 341 appears this perforating holes structure 214.This first metal layer 23 is positioned at the first surface 211 of this base material 21, preferably, is positioned on this first insulating bottom layer 22, and comprises one first inductance 231 and one first bottom electrode 232, and this first metal layer 23 directly contacts this perforating holes structure 214.This first dielectric layer 24 is positioned on this first bottom electrode 232.In the present embodiment, the material of this first dielectric layer 24 is tantalum pentoxide (Tantalum Pentoxide, Ta
2O
5).This first top electrode 25 is positioned on this first dielectric layer 24, and this first top electrode 25, this first dielectric layer 24 and this first bottom electrode 232 form one first electric capacity 26.In the present embodiment, the material of this first top electrode 25 is aluminum bronze (AlCu).
This first protective layer 27 coats this first inductance 231 and this first electric capacity 26.In the present embodiment, this first protective layer 27 comprises at least one first opening 271, and this first opening 271 appears this first metal layer 23 of part or this first top electrode 25 of part.This first projection 28 is positioned at first opening 271 of this first protective layer 27.This electrical assembly is positioned at the second surface 215 of this base material 21.This electrical assembly is one second projection 31.
By this, first bottom electrode 232 of this first inductance 231 and this first electric capacity 26 is positioned at on one deck, and can reduce product thickness.
With reference to Figure 19, show the generalized section of second embodiment of semiconductor package of the present invention.The semiconductor package 2 (Figure 18) of the semiconductor package 3 of present embodiment and first embodiment is roughly the same, and wherein identical assembly is given identical numbering.Present embodiment and first embodiment different be in, in the present embodiment, the second surface 215 of this semiconductor package 3 comprises several electrical assemblies (for example one second inductance 32, one second electric capacity 33 and one second projection 31).
Referring to figures 20 through Figure 26, the schematic diagram of second embodiment of the manufacture method of demonstration semiconductor package of the present invention.With reference to Figure 20, provide a base material 21.In the present embodiment, this base material 21 has a upper surface 216 and a second surface 215, and this groove 213 is opened on the second surface 215 of this base material 21, and this conductive hole structure 217 is revealed in the second surface 215 of this base material 21.With reference to Figure 21, form one second insulating bottom layer 34 on this base material 21.In the present embodiment, this second insulating bottom layer 34 is positioned at the second surface 215 of this base material 21, and has one second perforation 341, and this second perforation 341 appears this conductive hole structure 217.Then, form the second surface 215 of at least one electrical assembly in this base material 21, preferably, be positioned on this second insulating bottom layer 34, in the present embodiment, this electrical assembly is one second projection 31.With reference to Figure 22, this base material 21 is set on a carrier 29, wherein the second surface 215 of this base material 21 is in the face of this carrier 29, and remove this base material 21 of part from the upper surface 216 (Figure 21) of this base material 21, to form a first surface 211, and appear this conductive hole structure 217 (Figure 21) in this first surface 211, to form a perforating holes structure 214.
With reference to Figure 23, form a first metal layer 23 on this base material 21, preferably, be positioned at the first surface 211 of this base material 21.One first electrodeposited coating 235 and one first crystal seed layer 233 form this first metal layer 23.This first metal layer 23 comprises one first inductance 231 and one first bottom electrode 232.With reference to Figure 24, form one first dielectric layer 24 and one first top electrode 25 on this first bottom electrode 232, wherein this first dielectric layer 24 is between this first top electrode 25 and this first bottom electrode 232, and this first top electrode 25, this first dielectric layer 24 and this first bottom electrode 232 form one first electric capacity 26.With reference to Figure 25, form one first protective layer 27, to coat this first inductance 231 and this first electric capacity 26.This first protective layer 27 comprises at least one first opening 271, and this first opening 271 appears this first metal layer 23 of part or this first top electrode 25 of part.With reference to Figure 26, form at least one first projection 28 in first opening 271 of this first protective layer 27, and remove this carrier 29, form first embodiment of semiconductor package 2 of the present invention.
With reference to Figure 27 to Figure 29, the schematic diagram of the 3rd embodiment of the manufacture method of demonstration semiconductor package of the present invention.The manufacture method (Fig. 2 to Figure 19) of the semiconductor package of the manufacture method of the semiconductor package of present embodiment and first embodiment is roughly the same, and wherein identical assembly is given identical numbering.Present embodiment is different with first embodiment be in, with reference to Figure 27, when a base material 21 is provided, this base material 21 has a first surface 211, a second surface 215, at least one groove 213 and at least one conductive hole structure, this groove 213 runs through this first surface 211 and this second surface 215, this conductive hole structure is positioned at this groove 213, and is revealed in this first surface 211 and this second surface 215, and forms a perforating holes structure 214.Then, with reference to Figure 28, prior to first surface 211 formation one first inductance 231 and one first electric capacity 26 of this base material 21.With reference to Figure 29, the second surface 215 in this base material 21 forms at least one electrical assembly again, and forms first embodiment of semiconductor package of the present invention simultaneously.Yet in other was used, when a base material 21 was provided, this base material 21 can have a first surface 211 and a second surface 215, and does not comprise this groove 213 (Figure 27) and this perforating holes structure 214 (Figure 27).Moreover, also can form this electrical assembly prior to the second surface 215 of this base material 21, the first surface 211 in this base material 21 forms this first inductance 231 and this first electric capacity 26 again.
Only the foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in the personage of this technology.Interest field of the present invention should be listed as claims.
Claims (19)
1. the manufacture method of a semiconductor package comprises:
(a) provide a base material;
(b) form a first metal layer on this base material, this first metal layer comprises one first inductance and one first bottom electrode;
(c) form one first dielectric layer and one first top electrode on this first bottom electrode, wherein this first dielectric layer is between this first top electrode and this first bottom electrode, and this first top electrode, this first dielectric layer and this first bottom electrode form one first electric capacity; And
(d) form one first protective layer, to coat this first inductance and this first electric capacity.
2. method as claimed in claim 1, wherein in this step (a), this base material comprises at least one groove and at least one conductive hole structure, this conductive hole structure is positioned at this groove.
3. method as claimed in claim 2, wherein in this step (a), this base material has a first surface and a second surface, this groove runs through this first surface and this second surface, and this conductive hole structure is revealed in this first surface and this second surface, and forms a perforating holes structure, in this step (b), this the first metal layer is positioned at the first surface of this base material, and directly contacts with this perforating holes structure.
4. method as claimed in claim 2, wherein in this step (a), this base material has a first surface and a lower surface, this groove opening is in the first surface of this base material, and this conductive hole structure is revealed in the first surface of this base material, in this step (b), this first metal layer is positioned at the first surface of this base material, and directly contacts with this conductive hole structure.
5. method as claimed in claim 4, wherein this step (d) more comprises afterwards:
(e) this base material is set on a carrier, wherein the first surface of this base material is in the face of this carrier;
(f) remove this base material of part from the lower surface of this base material, forming a second surface, and appear this conductive hole structure, to form a perforating holes structure in this second surface;
(g) form at least one electrical assembly in the second surface of this base material; And
(h) remove this carrier.
6. method as claimed in claim 2, wherein in this step (a), this base material has a upper surface and a second surface, and this groove opening is in the second surface of this base material, and this conductive hole structure is revealed in the second surface of this base material.
7. method as claimed in claim 6, wherein this step (a) more comprises afterwards:
(a1) form at least one electrical assembly in the second surface of this base material;
(a2) this base material is set on a carrier, wherein the second surface of this base material is in the face of this carrier; And
(a3) remove this base material of part from the upper surface of this base material, forming a first surface, and appear this conductive hole structure, to form a perforating holes structure in this first surface.
8. method as claimed in claim 7, wherein in this step (b), this first metal layer is positioned at the first surface of this base material, and directly contacts with this perforating holes structure.
9. method as claimed in claim 7, wherein this step (d) comprises that more one removes the step of this carrier afterwards.
10. method as claimed in claim 1, wherein this step (b) comprising:
(b1) form one first crystal seed layer on this base material;
(b2) form one first photoresistance on this first crystal seed layer,, and appear this first crystal seed layer of part with this first crystal seed layer of cover part;
(b3) form one first electrodeposited coating on quilt this first crystal seed layer of part that appears; And
(b4) this first crystal seed layer of part that removes this first photoresistance and be capped, this first electrodeposited coating and this first crystal seed layer of part form this first metal layer.
11. method as claimed in claim 1, wherein this step (c) comprising:
(c1) form one second metal level on this first bottom electrode, and this second metal level is carried out anodic oxidation, to form one first oxide layer;
(c2) form one the 3rd metal level on this first oxide layer;
(c3) form one second photoresistance on the 3rd metal level;
(c4) remove this first oxide layer of part and part the 3rd metal level,, form this first electric capacity simultaneously to form this first dielectric layer and this first top electrode respectively; And
(c5) remove this second photoresistance.
12. a semiconductor package comprises:
One base material has a first surface and a second surface;
One the first metal layer is positioned at the first surface of this base material, and comprises one first inductance and one first bottom electrode;
One first dielectric layer is positioned on this first bottom electrode;
One first top electrode is positioned on this first dielectric layer, and this first top electrode, this first dielectric layer and this first bottom electrode form one first electric capacity; And
One first protective layer coats this first inductance and this first electric capacity.
13. as the encapsulating structure of claim 12, wherein the material of this base material is a glass.
14. as the encapsulating structure of claim 12, wherein the material of this base material is silicon or silica.
15. encapsulating structure as claim 14, more comprise one first insulating bottom layer and one second insulating bottom layer, this first insulating bottom layer is positioned at the first surface of this base material, and this second insulating bottom layer is positioned at the second surface of this base material, and this first metal layer is positioned on this first insulating bottom layer.
16. encapsulating structure as claim 12, wherein this base material comprises at least one groove and at least one perforating holes structure, this groove runs through the first surface and the second surface of this base material, this perforating holes structure is positioned at this groove, and be revealed in the first surface and the second surface of this base material, this first metal layer directly contacts this perforating holes structure.
17. as the encapsulating structure of claim 12, wherein this first protective layer comprises at least one first opening, this first opening appears this first metal layer of part or this first top electrode of part.
18. as the encapsulating structure of claim 17, more comprise at least one first projection, be positioned at first opening of this first protective layer.
19., more comprise at least one electrical assembly as the encapsulating structure of claim 12, be positioned at the second surface of this base material, wherein this electrical assembly is one second inductance, one second electric capacity or one second projection.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102496616A (en) * | 2011-11-28 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor element with integrated passive element and manufacture method of semiconductor element |
| US8853819B2 (en) | 2011-01-07 | 2014-10-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure with passive element network and manufacturing method thereof |
| CN105742251A (en) * | 2014-12-09 | 2016-07-06 | 联华电子股份有限公司 | Structure with inductor and metal-insulating layer-metal capacitor |
| CN105789199A (en) * | 2011-11-28 | 2016-07-20 | 日月光半导体制造股份有限公司 | Semiconductor element having integrated passive element, and manufacturing method thereof |
| CN105977203A (en) * | 2012-02-15 | 2016-09-28 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| WO2022222131A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Substrate integrated with passive device, and preparation method therefor |
| WO2022222133A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100338757C (en) * | 2005-12-21 | 2007-09-19 | 广辉电子股份有限公司 | Method for preparing copper conductor for plane display substrate |
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| US8853819B2 (en) | 2011-01-07 | 2014-10-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor structure with passive element network and manufacturing method thereof |
| CN102496616A (en) * | 2011-11-28 | 2012-06-13 | 日月光半导体制造股份有限公司 | Semiconductor element with integrated passive element and manufacture method of semiconductor element |
| CN102496616B (en) * | 2011-11-28 | 2016-04-27 | 日月光半导体制造股份有限公司 | There is semiconductor element and the manufacture method thereof of integrated passive element |
| CN105789199A (en) * | 2011-11-28 | 2016-07-20 | 日月光半导体制造股份有限公司 | Semiconductor element having integrated passive element, and manufacturing method thereof |
| CN105789199B (en) * | 2011-11-28 | 2019-05-21 | 日月光半导体制造股份有限公司 | Semiconductor element and its manufacturing method with integrated passive element |
| CN105977203A (en) * | 2012-02-15 | 2016-09-28 | 日月光半导体制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN105977203B (en) * | 2012-02-15 | 2019-06-11 | 日月光半导体制造股份有限公司 | Semiconductor element and its manufacturing method |
| CN105742251A (en) * | 2014-12-09 | 2016-07-06 | 联华电子股份有限公司 | Structure with inductor and metal-insulating layer-metal capacitor |
| CN105742251B (en) * | 2014-12-09 | 2019-10-18 | 联华电子股份有限公司 | Structure with inductance and metal-insulating layer-metal capacitor |
| WO2022222131A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Substrate integrated with passive device, and preparation method therefor |
| WO2022222133A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method therefor |
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