CN102131092B - Embedded video transmission method - Google Patents

Abstract

The invention discloses an embedded video transmission method. In the method, an FPGA (field programmable gate array) is provided with a MicroBalze soft core CPU (central processing unit), an EMC (external memory controller), a GPIO (general purpose input output) and an I2C (inter-integrated circuit), wherein in the video transmission process, the CPU module interacts with an external video decoding unit, an external video compression unit and a channel coding unit via the I2C, EMC and GPIO, thus realizing the transmission of video data from the video coding unit to the video compression unit and then to the channel coding unit. According to the invention, data compression and channel coding based on a single chip can be realized, and the speed mismatching under a low code rate can be effectively coordinated by virtue of the control capability of the MicroBalze soft core CPU, thus realizing an application during the speed mismatching between video acquisition and channel coding.

Description

A kind of embedded video transmission method

Technical field

The present invention relates to a kind of embedded video transmission method, be specially adapted to input video stream and outputting video streams when not matching video transmission, belong to field of embedded technology.

Background technology

Xilinx company is the maximum FPGA production firm in the whole world, and Xilinx company has released the EDK developing instrument to PowerPC and MicroBlaze.Be used for the foundation and the generation of application software system of hardware system in the FPGA sheet, the exploitation of promptly whole SOPC system all is EDK (embedded development tool set) completion down at Xilinx.The embedded development kit EDK that Xilinx company provides provides the IDE XPS (Xilinx Platform Studio) of SOPC engineering management interface in this environment, to comprise required all instruments and the interface of each link in the SOPC designs such as hardware platform architecture, software development, placement-and-routing's realization, emulation and debugging.If the user need add oneself logic module and constraint, then need in ISE, accomplish.

Using to the video image under the low bit rate rate is the focus that people study always, the miniaturization of Video transmission system, design reconfigurability, significant for the structure of Video transmission system.The equipment that this method makes up is accomplished the shooting of special scenes, through Radio Link with transmission of video images to receiving equipment, realized the purpose of real-time monitored.The input source of this method is that data volume is 165Mbps (Phase Alternation Line system coloured image) original image, channel transmission rate 25Kbps.Contradiction to original data volume and transmission rate; This method utilizes the inner soft nucleus CPU of FPGA to realize that video decode and compression chip dispose and overall system data flow con-trol, channel coding module are transferred to the logical design unit; Replaced in the past in the system that needs are special to add the complicated controlled function that Controlled CPU just can realize; By a kind of handshake mechanism that soft nucleus CPU is set up, realized that the video transmission under a kind of low bit rate rate is used.

Existing Video Applications mainly concentrates on through certain chip and realizes.In case and constructed in hardware finishes then do not possess reconfigurability, realizes having very big flexibility based on the system hardware of soft nucleus CPU.Be different from common logical design and transfer to the scheme that different chips are realized with controlling Design; System based on soft nucleus CPU effectively organizes logical design and controlling Design; The function integrated monolithic that script needs multifunction chip to realize is realized; Saved system's area effectively, and exploitation of the hardware logic in the FPGA and software development have been isolated when the system development, effectively promoted the speed of system development based on the system of soft nucleus CPU.

Summary of the invention

The objective of the invention is to: a kind of embedded video transmission method is provided; The present invention utilizes the flexible configurability of the embedded MicroBalze soft nucleus CPU in the FPGA; Data compression and chnnel coding have been realized based on single chip; And the control ability that relies on the MicroBalze soft nucleus CPU coordinated the not matching property of speed under the low code check effectively, realized the application when video acquisition and chnnel coding speed do not match.

Technical solution of the present invention is:

A kind of embedded video transmission method, realize through following steps:

Step 1: in FPGA, realize MicroBalze soft nucleus CPU, external memory controller EMC, general input/output port GPIO, I2C; Said CPU is used for EMC, GPIO, I2C are dispatched; Said EMC and external video compression unit carry out alternately; Said GPIO and foreign channels coding unit carry out alternately; The on-chip memory that said I2C and external video decoding unit and being used to stored external video compression unit firmware carries out alternately;

Step 2: power up the back to CPU, EMC, GPIO, I2C, on-chip memory module with carry out initialization;

Step 3:CPU module is passed through I2C configuring external video decoding unit: Phase Alternation Line system is adopted in the video input, and the BT.656 pattern is adopted in video output;

Step 4: after the external video decoding unit detected the vision signal input, the CPU module was being opened the threshold value interrupt mode through EMC configuring external video compression cell operation, and changes step 5 over to;

Step 5: vision signal outputs in the external video compression unit after video decoding unit is handled, and utilizes fifo buffer to store after the data compression of external video compression unit with input; Change step 6 over to;

Step 6: if the fifo buffer of external video compression unit reaches the storage threshold of setting, then start threshold value and interrupt, make the interrupt signal IRQ of video compression unit effective, CPU module responds IRQ gets into interruption, and changes step 7 over to;

Step 7:CPU module utilizes EMC to read the packed data in the fifo buffer of video compression unit, and utilizes GPIO that packed data is outputed to the foreign channels coding unit; By the chnnel coding unit packed data of input is handled back output;

Step 8: when the chnnel coding cell operation, the CPU module judges whether chnnel coding unit end mark signal FLAG is effective, if FLAG is effective, then the chnnel coding cell operation finishes, and returns step 6; If FLAG is invalid, and IRQ is effective, then closes the video input of video decoding unit; After waiting for that IRQ is invalid, open the input of video decoding unit video, and return step 6.

The packed data of exporting through the dual port RAM transmission between said GPIO and foreign channels coding unit.

The present invention compared with prior art has following advantage:

(1) the present invention adopts the method for designing of software-hardware synergism, has made up SOC(system on a chip).The present invention is different from the scheme that the different chips of common employing are realized logical design and controlling Design; And be based on soft nucleus CPU logical design and controlling Design are effectively organized; The function that needs a plurality of functional chips to realize script realizes through integrated monolithic, has saved system's area effectively.

(2) the present invention adopts the C language to realize I2C, EMC and GPIO.And adopt I2C configuring external video decoding unit ADV7180, utilize GPIO to realize the output of packed data; Utilize EMC control external video compression unit ADV212, the design of having omitted configuration ADV212 sequential; Then adopt logical design for chnnel coding, realize that software and hardware carries out simultaneously in the design process, improved the process of design greatly.

(3) the present invention adopts dual port RAM to realize mutual with based on the chnnel coding unit of VHDL language based on the GPIO of C language.Because C language design can not accurately controlling clock, when realizing, adopts dual port RAM that the packed data of GPIO output is received earlier, through dual port RAM packed data is outputed to the chnnel coding unit again, has solved the stationary problem of C language and VHDL language.

Description of drawings

Fig. 1 is a principle of the invention composition frame chart;

Fig. 2 is the dual port RAM allocation plan;

Fig. 3 is a flow chart of the present invention.

Embodiment

Just combine accompanying drawing that the specific embodiment of the invention is done further introduction below.

Adopt the present invention to utilize monolithic FPGA to realize the function that a plurality of functional chips could be realized, dwindled Video transmission system, improved the reconfigurability of Video transmission system design.

As shown in Figure 1, be the Design of Video Transmission System figure that adopts the present invention to realize.When concrete design, adopted the software-hardware synergism scheme of designing, the inner realization of FPGA is divided into two parts: based on the embedded system and the logical design (chnnel coding unit) of MicroBalze soft nucleus CPU, the peripheral hardware of outfit is following:

1, I2C module: general-purpose interface, in order to configuration Video Decoder ADV7180 with from on-chip memory, read the firmware of external video compression unit (video compression chip ADV212);

2, external memory controller EMC:, be used to dispose ADV212 with the ADV212 interface;

3, general I/O port GPIO: the packed data that produces reset signal, transmission ADV212 is to logical design;

5, on-chip memory: the carrier of C programmer operation, realize by the ram in slice of FPGA, store the 32kB firmware of ADV212 simultaneously.

After system powers on, utilize the MicroBalze soft nucleus CPU to call each interface ADV7180 and ADV212 are configured.

The peripheral signal that connects of ADV212 comprises 4 address wires (16 direct registers of corresponding A DV212 respectively), 32 data lines (bidirectional interface related with the HDATA mouth is used to export compressed code flow), read/write and chip selection signal.To said characteristic, it is memory device that CPU looks ADV212, and utilizing its EMC peripheral hardware (external memory controller) is may command ADV212, has omitted the design of configuration ADV212 sequential, thereby has accelerated design schedule.

ADV7180 is the high-performance Video Decoder of ADI company; With the interface shape of peripheral components be the I2C bus; Do not have I2C IP in the EDK system of Xilinx, but provide integrated user from designing the function of peripheral hardware, so designed the I2C peripheral hardware in the native system voluntarily in order to configuration ADV7180.

In system work process,, therefore exist with the logical design of chnnel coding and carry out mutual problem because GPIO adopts the C language to realize.

Program based on the C language is (time of implementation of each bar statement cannot accurately be controlled) of arranging according to the time of implementation of instruction clock when carrying out; But the logical design part can accurately be controlled the operation of each clock cycle; So based on the design of C language and logical design the time, carry out the mutual time, just need can not accurately controlling clock the design of C language be transformed into can the logical design of accurately controlling clock operation in.The present invention adopts dual port RAM to solve in order to address this problem.Utilize the ChipScope test to find that the GPIO mouth sends data and taken 22 clk1 cycles, so utilize the data of dual port RAM and the many-one property of address, well with the multicycle data, conversion monocycle data have satisfied follow-up logical design demand.Concrete design is as shown in Figure 2.

After the introduction of accomplishing above-mentioned configuration, workflow of the present invention is done further introduction.The input source of this method is that data volume is 165Mbps (Phase Alternation Line system coloured image) original image, channel transmission rate 25Kbps.Contradiction to original data volume and transmission rate; This method utilizes the inner MicroBalze soft nucleus CPU of FPGA to realize that video decode and compression chip dispose and overall system data flow con-trol, chnnel coding unit are transferred to the logical design unit; Replaced in the past in the system that needs are special to add the complicated controlled function that Controlled CPU just can realize; By a kind of handshake mechanism that soft nucleus CPU is set up, realized that the video transmission under a kind of low bit rate rate is used.

As shown in Figure 3, be flow chart of the present invention.Its concrete workflow is:

1, power up after, CPU, EMC, GPIO, I2C, on-chip memory module and timer module are carried out initialization;

2, the CPU module disposes ADV7180 through I2C: Phase Alternation Line system is adopted in the video input, and the BT.656 pattern is adopted in video output;

3, when ADV7180 has detected the vision signal input; CPU begins to utilize EMC that ADV212 is configured: make ADV212 be operated in 32bit normal pattern, enable the FIFO threshold value interrupt function of ADV212; Be that data satisfy when setting threshold value among the FIFO, irq signal effectively (low level) promptly takes place to interrupt making in ADV212;

4, the vision signal of input is directly imported ADV212 into behind ADV7180, and ADV212 is stored into the packed data that generates in the fifo buffer of ADV212;

5, if after the data of fifo buffer stored reach preset threshold, get into and interrupt, irq signal (effectively) is a low level, CPU responds IRQ;

6, CPU utilizes EMC to read the packed data among the FIFO of ADV212, and sends to the logical design of chnnel coding through GPIO, and behind the data read sky among the FIFO, irq signal is invalid, again opens interrupters; In the process of sending, at first data are sent to dual port RAM through GPIO, read the dual port RAM data again to chnnel coding, thereby realized the synchronous of C language and logical design;

7, when the chnnel coding cell operation, the CPU module judges whether chnnel coding unit end mark signal FLAG is effective, if FLAG is effective, representes that then the chnnel coding cell operation finishes, and returns 5, responds the interruption of ADV212 again; If FLAG is invalid, and IRQ is effective, representes that then still there are data in the fifo buffer among the ADV212, then closes the video input of video decoding unit, after wait IRQ is invalid, opens the input of video decoding unit video again, returns step 5 then.

Step 7 through above-mentioned has realized the control of shaking hands to video signal collective, compression, coding, has coordinated the high and low contradiction of transmission speed of compressed bit stream speed.

The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.

Claims (2)

1. embedded video transmission method is characterized in that realizing through following steps:

Step 1: in FPGA, realize MicroBalze soft nucleus CPU, external memory controller EMC, general input/output port GPIO, I2C; Said CPU is used for EMC, GPIO, I2C are dispatched; Said EMC and external video compression unit carry out alternately; Said GPIO and foreign channels coding unit carry out alternately; The on-chip memory that said I2C and external video decoding unit and being used to stored external video compression unit firmware carries out alternately;

Step 2: power up the back CPU, EMC, GPIO, I2C, on-chip memory module are carried out initialization;

Step 3:CPU module is passed through I2C configuring external video decoding unit: Phase Alternation Line system is adopted in the video input, and the BT.656 pattern is adopted in video output;

Step 4: after the external video decoding unit detected the vision signal input, the CPU module was being opened the threshold value interrupt mode through EMC configuring external video compression cell operation, and changes step 5 over to;

Step 5: vision signal outputs in the external video compression unit after video decoding unit is handled, and utilizes fifo buffer to store after the data compression of external video compression unit with input; Change step 6 over to;

Step 6: if the fifo buffer of external video compression unit reaches the storage threshold of setting, then start threshold value and interrupt, make the interrupt signal IRQ of video compression unit effective, CPU module responds IRQ gets into interruption, and changes step 7 over to;

Step 7:CPU module utilizes EMC to read the packed data in the fifo buffer of video compression unit, and utilizes GPIO that packed data is outputed to the foreign channels coding unit; By the chnnel coding unit packed data of input is handled back output;

Step 8: when the chnnel coding cell operation, the CPU module judges whether chnnel coding unit end mark signal FLAG is effective, if FLAG is effective, then the chnnel coding cell operation finishes, and returns step 6; If FLAG is invalid, and IRQ is effective, then closes the video input of video decoding unit; After waiting for that IRQ is invalid, open the input of video decoding unit video, and return step 6.

2. a kind of embedded video transmission method according to claim 1 is characterized in that: the packed data of exporting through the dual port RAM transmission between said GPIO and foreign channels coding unit.

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