CN102130136B - Pixel structure and bigrid pixel structure - Google Patents
Pixel structure and bigrid pixel structure Download PDFInfo
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- CN102130136B CN102130136B CN 201010559062 CN201010559062A CN102130136B CN 102130136 B CN102130136 B CN 102130136B CN 201010559062 CN201010559062 CN 201010559062 CN 201010559062 A CN201010559062 A CN 201010559062A CN 102130136 B CN102130136 B CN 102130136B
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Abstract
The invention discloses a pixel structure and a bigrid pixel structure. The pixel structure comprises a substrate, a first metal layer, a grid insulation layer, a semiconductor layer, a second metal layer, a protecting layer, a hole and a pixel electrode. The first metal layer is arranged on the substrate. The first metal layer comprises a scanning line, a grid and a shared electrode. The shared electrode is provided with a preset nick. The grid insulation layer covers the first metal layer. The semiconductor layer is arranged on the grid insulation layer. The second metal layer is arranged on the semiconductor layer and the semiconductor layer is arranged below the second metal layer. The protecting layer covers the second metal layer. The hole is formed in the preset nick and penetrates through the protecting layer, and the second metal layer is exposed. The pixel electrode is arranged on the protecting layer and filled into the hole. The pixel electrode is electrically connected with the second metal layer by passing through the hole. The invention also provides a bigrid pixel structure.
Description
Technical field
The invention relates to a kind of dot structure, and particularly relevant for a kind of dot structure of flat-panel screens.
Background technology
In flat-panel screens industry with keen competition, manufacturer is except being devoted to research and develop the more superior flat-panel screens of performance, and the reduction manufacturing cost of also constantly making great efforts is to improve the flat-panel screens of enterprise's profit and the supply more economical material benefit in consumption market.
The Thin Film Transistor-LCD of popularizing the most in the flat-panel screens is as example, and the method that reduces its manufacturing cost has many kinds.Wherein, it is reduce to make the light shield quantity of the required use of dot structure that a kind of method is arranged, and saving expending of manpower and processing procedure time in the relevant processing procedure, and then reaches the purpose that reduces manufacturing cost.
Generally speaking, the mode that reduces the light shield quantity of making the required use of dot structure is with existing five road optical cover process, is kept to four road optical cover process.Figure 1A to Fig. 1 H is the manufacturing process generalized section of known dot structure with four road light shield manufactures.Please sequentially with reference to Figure 1A to Fig. 1 H, in the processing procedure that uses four road light shields, at first, form the first metal layers 102 at substrate 100, and with the first mask patternization it.Then, sequentially form gate insulation layer 104, semiconductor layer 106 and the second metal level 108 on substrate 100 comprehensively, be coated with again afterwards a photoresist layer 110 on the second metal level 108, shown in Figure 1A.
Then, utilize half mode (half tone) or grey mode (gray tone) light shield, namely the second light shield 200, with photoresist layer 110 patternings of coating on the second metal level 108, as shown in Figure 1B.Then, carry out the wet etching processing procedure first time behind the patterning photoresist layer 110, with the second metal level 108 patternings, afterwards, carry out again the dry ecthing procedure first time, with semiconductor layer 106 patternings, respectively shown in Fig. 1 C and Fig. 1 D.
Yet, the situation of uneven thickness often can occur during light blockage coating, the thinner situation in part zone is for example arranged in the right side of the photoresist layer 110 of Figure 1A.This thinner photoresist layer passes through above-mentioned photoresist layer patterning process, wet etching processing procedure, dry ecthing procedure and ensuing ashing (O sequentially
2Ashing) behind the processing procedure, this thinner photoresist layer might be completely removed, and so that part the second metal level 108 under it be exposed, shown in Fig. 1 E.
So, carry out the second time take photoresist layer 110 as cover curtain during the wet etching processing procedure, the second metal level 108 that is exposed will be etched, and so that the part semiconductor layer 106 under it be exposed, shown in Fig. 1 F.Then, carry out the second time take photoresist layer 110 as cover curtain during dry ecthing procedure, the part semiconductor layer 106 that is exposed can be thinned, shown in Fig. 1 G again.
Then, remove remaining photoresist layer 110 after, form a protective layer 112 on substrate 100, shown in Fig. 1 G.Then, in protective layer 112, form a plurality of contact hole h1, h2 by the 3rd road light shield, shown in Fig. 1 H.What need special instruction is, when forming contact hole h1, h2, the other parts of dot structure (not illustrating) need be done the jumper connection of 108 of the first metal layer 102 and the second metal levels, therefore the part semiconductor layer 106 corresponding with contact hole h2, part gate insulation layer 104 can be consumed totally, and the first metal layer 102 that originally should not expose out is exposed, shown in Fig. 1 H.So, the pixel electrode 114 that forms in the 4th road processing procedure will contact with the first metal layer 102 that is exposed out and form short circuit, and then it is unusual to cause pixel to show.Hold above-mentionedly, in four road optical cover process, how to avoid uneven because of light blockage coating and then cause pixel to show unusual phenomenon, one of real problem that faces for the developer of exploitation four road optical cover process.
Summary of the invention
The invention provides a kind of dot structure, can improve pixel and show unusual phenomenon.
The invention provides a kind of bigrid dot structure, also can improve pixel and show unusual phenomenon.
The invention provides a kind of dot structure, it comprises substrate, the first metal layer, gate insulation layer, semiconductor layer, the second metal level, protective layer, hole and pixel electrode.The first metal layer is disposed on the substrate.Grid and shared electrode that the first metal layer comprises scan line, is electrically connected with scan line.Shared electrode is separated with scan line and is had a default breach, and wherein default breach is positioned on the edge of shared electrode.Gate insulation layer is disposed on the substrate and covers the first metal layer.Semiconductor layer is disposed on the gate insulation layer.The second metal level is disposed on the semiconductor layer, and all there is semiconductor layer the second metal level below.The second metal level comprises data wire, source electrode, drain electrode and storage electrode.Data wire and scan line are staggered.Source electrode is electrically connected data wire.Storage electrode is positioned at the top of default breach.Protective layer is disposed on the substrate and covers the second metal level, and has an opening to expose drain electrode.Hole is positioned at default breach and runs through protective layer and expose the second metal level.Pixel electrode is disposed on the protective layer and inserts in the hole.Pixel electrode sees through opening and is electrically connected with drain electrode, and is electrically connected through hole and the second metal level.
The invention provides a kind of bigrid dot structure, it comprises substrate, the first metal layer, gate insulation layer, semiconductor layer, the second metal level, protective layer, hole and pixel electrode.The first metal layer is disposed on the substrate.The first metal layer comprises two scan lines, shares electrode with two grids and of scan line electric connection.Shared electrode is separated with scan line and is had a default breach, and wherein default breach is positioned on the edge of shared electrode.Gate insulation layer is disposed on the substrate and covers the first metal layer.Semiconductor layer is disposed on the gate insulation layer.The second metal level is disposed on the semiconductor layer, and all there is semiconductor layer the second metal level below.The second metal level comprises a data wire, two source electrodes, two drain electrode and two storage electrodes.Data wire and scan line are staggered.Source electrode is electrically connected with data wire separately.Storage electrode is positioned at the top of default breach.Protective layer is disposed on the substrate and covers the second metal level, and has two openings to expose two drain electrodes.Hole is positioned at default breach and runs through protective layer and expose the second metal level.Pixel electrode is disposed on the protective layer and inserts in the hole.Pixel electrode sees through opening and is electrically connected with drain electrode, and is electrically connected through hole and the second metal level.
In one embodiment of this invention, the aforesaid hole that runs through protective layer and be positioned at default breach does not run through the second metal level, semiconductor layer and an insulating barrier.
In one embodiment of this invention; the aforesaid hole that runs through protective layer and be positioned at default breach more runs through the second metal level, semiconductor layer and an insulating barrier, and exposes the sidewall of the second metal level, the sidewall of semiconductor layer, the sidewall of gate insulation layer and the surface of substrate.
In one embodiment of this invention, aforesaid shared electrode is positioned at the peripheral of pixel electrode and overlaps with its part.
In one embodiment of this invention, the part of aforesaid shared electrode and pixel electrode overlapping consists of a storage capacitors.
In one embodiment of this invention, the part of aforesaid shared electrode and storage electrode overlapping consists of a storage capacitors.
In one embodiment of this invention, aforesaid shared electrode has at least one bending place, and default breach and bending place keep a distance at least.
In one embodiment of this invention, the edge of aforesaid default breach and storage electrode keeps a distance at least.
In one embodiment of this invention, the size of aforesaid hole is in fact less than the size of presetting breach.
The invention provides dot structure and a kind of bigrid dot structure, it is by reserving breach in shared electrode design one, can avoid causing because light blockage coating is uneven part second metal level, semiconductor layer of hole below with etched with the door insulating barrier, and then cause the problem of shared electrode and pixel electrode formation short circuit.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Figure 1A to Fig. 1 H is known pixel structure manufacturing process generalized section.
Fig. 2 looks schematic diagram on the dot structure of first embodiment of the invention.
Fig. 3 A to Fig. 3 H is the making flow process cut-away view of the dot structure that illustrates along the I-I ' line of Fig. 2.
Fig. 4 looks schematic diagram on the dot structure of second embodiment of the invention.
Embodiment
[the first embodiment]
Fig. 2 looks schematic diagram on the dot structure of first embodiment of the invention.Fig. 3 A to Fig. 3 H is the making flow process cut-away view of the dot structure that illustrates along the I-I ' line of Fig. 2.Below, Fig. 2 and Fig. 3 A to Fig. 3 H dot structure and the manufacture method thereof to the present embodiment is described in detail with arranging in pairs or groups.
The dot structure of the present embodiment, its formation method for example are the following stated: please refer to Fig. 3 A, substrate 300 at first is provided.Then on substrate 300, form the first metal layer 302, and by first optical cover process patterning it.In the present embodiment, the first metal layer 302 after the patterning has comprised scan line SL and the shared electrode CL that separates with scan line SL, and wherein, the grid use is used as in the subregion of scan line SL, as shown in Fig. 2 and Fig. 3 A.
What be worth paying special attention to is that the shared electrode CL of the present embodiment has at least one bending place and default breach O.Wherein, default breach O is positioned on the edge of shared electrode CL, and this default breach O and bending place keep a suitable distance.In the present embodiment, the material of substrate 300 for example is glass, quartz, organic polymer, light tight/reflecting material (such as electric conducting material, wafer, pottery or other material applicatory) or other material applicatory, and the material of the first metal layer 302 for example is alloy, metal or other suitable material.
Then, sequentially on substrate 300, form all sidedly gate insulation layer 304, semiconductor layer 306 and the second metal level 308 to cover scan line SL and shared electrode CL.In the present embodiment, the material of gate insulation layer 304 for example is the combination of Inorganic Dielectric Material (such as the stack layer of silica, silicon nitride, silicon oxynitride or above-mentioned at least two kinds of materials), organic dielectric materials or above-mentioned organic and Inorganic Dielectric Material.In the present embodiment, the material of semiconductor layer 306 for example is amorphous silicon layer or other semi-conducting material that is fit to.In the present embodiment, the material of the second metal level 308 for example is alloy, metal or other suitable material.
After forming above-mentioned gate insulation layer 304, semiconductor layer 306 and the second metal level 308, then on the second metal level 308, be coated with a photoresist layer 310.In the present embodiment, the material of photoresist layer 310 can be positive photoresist or negative photoresist, and the present invention is not particularly limited.Yet, in the light blockage coating processing procedure, often the situation that coating thickness differs can occur, the situation of its thinner thickness for example appears for the photoresist layer 310 of default breach O top, as shown in Fig. 3 A.
Then, by second light shield 400 (for example half mode (half tone) light shield) patterning photoresist layer 310, as shown in Fig. 3 B.Behind the patterning photoresist layer 310, carry out the wet etching processing procedure first time, with the second metal level 308 patternings, as shown in Fig. 3 C.Then, carry out again the dry ecthing procedure first time behind the photoresist layer patterning, with semiconductor layer 306 patternings, as shown in Fig. 3 D.
After finishing above-mentioned steps, in order to remove surface organic matter, can carry out an ashing (O
2Ashing) processing procedure.Carrying out ashing (O
2Ashing) during processing procedure, the portions of light resistance layer 310 that is positioned at scan line SL top can be removed, and exposes part the second metal level 308.Simultaneously, be positioned at default breach O top and the quite thin part photoresist layer 310 of thickness and also can be removed, and expose part metal level 308 below it, as shown in Fig. 3 E.
Behind the patterning photoresist layer 310, carry out the wet etching processing procedure second time, part the second metal level 308 that scan line SL top is exposed etches away, so that source S and drain D be shaped and expose part semiconductor layer 306, as shown in Fig. 3 F.The same time, part the second metal level 308 that default breach O top is exposed out also can be etched and be exposed the part semiconductor layer 306 of its below, as shown in Fig. 3 F.
Behind the patterning photoresist layer 310, carry out the dry ecthing procedure second time.At this moment, the part semiconductor layer 306 etched sub-fractions that scan line SL top is exposed out are as shown in Fig. 3 G.The same time, the part semiconductor layer 306 that is positioned at default breach O top also can etched sub-fraction, as shown in Fig. 3 G.Arrive this, just finished all second optical cover process.
In above-mentioned second optical cover process, main purpose is with the second metal level 308 and semiconductor layer 306 patternings.In the present embodiment, the second metal level 308 after the patterning has comprised data wire DL, source S, drain D and storage electrode CE, as shown in Fig. 2 and Fig. 3 G.As can be seen from Figure 2, data wire DL and scan line SL are staggered, and source S and drain D system are electrically insulated each other, and are covered on the semiconductor layer 306 and gate insulation layer 304 partly of part.
What be worth paying special attention to is, because the dot structure of the present embodiment adopts four road optical cover process to make, that is to say, after sequentially forming gate insulation layer 304, semiconductor layer 306 and the second metal level 308 comprehensively, again with same light shield with its patterning, therefore after finishing above-mentioned steps, semiconductor layer 306 is arranged all just under the data wire DL of the present embodiment, source S, drain D and the storage electrode CE.Wherein, the storage electrode CE of the present embodiment is positioned on the default breach O, and overlaps with shared electrode CL part zone, so the part of shared electrode CL and storage electrode CE overlapping just can consist of storage capacitors.In addition, an edge CE-a of the storage electrode of the present embodiment and an edge O-a of default breach keep one at least apart from d, and an edge CE-a of storage electrode and an edge CL-a of common electrode keep one at least apart from d '.In the present embodiment, above-mentioned apart from d and d ' greater than 0, preferably apart from d and d ' all greater than the maximum admissible error on the contraposition processing procedure (for example 3um).Thus, when the error in the generation allowable range in the contraposition processing procedure, the area that is overlapped by common electrode CL and storage electrode CE can not change because of the error on the contraposition processing procedure, and then the storage capacitors value that causes common electrode CL and storage electrode CE to consist of changes.So, just can avoid changing the relevant electrical problem that causes because of the storage capacitors value.
After finishing all second optical cover process, then remove remaining photoresist layer 310, then on substrate 300, form protective layer 312, and cover the second metal level 308, as shown in Fig. 3 G.Then, in protective layer 312, form opening W and hole H by the 3rd road optical cover process, as shown in Fig. 3 H.
What need special instruction is; when forming opening W, hole H; the part semiconductor layer 306 corresponding with hole H, part gate insulation layer 304 can be consumed totally; run through the second metal level 308, semiconductor layer 306 and a door insulating barrier 304 and make this run through protective layer 312 and be positioned at the hole H that presets breach O; and expose the sidewall of the second metal level 308, the sidewall of semiconductor layer 306, the sidewall of gate insulation layer 304 and the surface of substrate 300, as shown in Fig. 3 H.
Then, on substrate 300, form pixel electrode PE by the 3rd road optical cover process.This pixel electrode PE is connected with the storage capacitors CE of the second metal level and the substrate 300 that is exposed out via hole H via opening W and drain D electric connection, and the situation with the described pixel electrode PE of prior art and the first metal layer 302 short circuits can not occur.
In other words, reserve breach O because the shared electrode CL of the present embodiment has designed one in hole H below, and the actual size of this default breach O is greater than the size of hole.At this moment, if when situation as the described light blockage coating inequality of prior art occured, storage electrode CE and substrate 300 that pixel electrode PE only can see through hole H and the second metal level contacted, and can't contact with shared electrode CL and form short circuit.In other words, uneven and then cause pixel to show that unusual problem can achieve a solution by above-mentioned mode because of light blockage coating described in the prior art, thus promote display quality and the electrical performance of the dot structure of the present embodiment.
What need supplementary notes is; if photoresist layer 310 coating no exceptions; that is to say, photoresist layer 310 coating thicknesss are talked about uniformly, run through protective layer 312 and be positioned at the hole H that presets breach O then not run through the second metal level 308, semiconductor layer 306 and a door insulating barrier 304.In other words, hole H only exposes the second metal level 308 to the open air, and does not run through the second metal level 308 and expose to the open air or run through semiconductor layer 306 and a door insulating barrier 304.
Based on above-mentioned; the present embodiment also can propose a kind of dot structure, and it comprises aforesaid base plate 300, aforementioned the first metal layer 302, aforementioned gate insulation layer 304, aforesaid semiconductor layer 306, second metal layers 308, aforementioned protective layer 312, aforementioned hole H and aforementioned pixel electrode PE.The first metal layer 302 is disposed on the substrate 300, and grid and shared electrode CL that the first metal layer 302 comprises scan line SL, is electrically connected with scan line, wherein shared electrode CL separates with scan line SL and has a default breach O, and default breach O is positioned on the edge of shared electrode CL, shown in Fig. 2 and Fig. 3 H.In addition, gate insulation layer 304 is disposed on the substrate 300 and covers the first metal layer 302, and semiconductor layer 306 is disposed on the gate insulation layer 304.
In the dot structure of the present embodiment, the second metal level 308 is disposed on the semiconductor layer 306, and all there is semiconductor layer 306 the second metal level 308 belows, and wherein the second metal level 308 comprises data wire DL, source S, drain D and storage electrode CE.Data wire DL and scan line SL are staggered, and source electrode D is electrically connected data wire DL, and storage electrode CE is positioned at the top of default breach O.In addition, protective layer 312 is disposed on the substrate and covers the second metal level 308, and has an opening W to expose drain D.In the present embodiment; hole H is positioned at default breach O and runs through protective layer 312 and expose the second metal level 308; and pixel electrode PE is disposed on the protective layer 312 and inserts in the hole H; wherein pixel electrode PE sees through opening O and drain D electric connection, and sees through hole H and 308 electric connections of the second metal level.
In the present embodiment, because the shared electrode CL of dot structure has designed one and has reserved breach O below hole H when design, and the actual size of this default breach O is greater than the size of hole, so that when situation with the described light blockage coating inequality of prior art occurs, storage electrode CE and substrate 300 that pixel electrode PE only can see through hole H and the second metal level contact, thereby can promote the electrical performance of dot structure, and can have better display quality when being applied to display unit.
[the second embodiment]
The concept of reserving breach in the design in shared electrode CL one described in the first embodiment also can be applicable in the bigrid dot structure of second embodiment of the invention, so that the situation that the bigrid dot structure of the present embodiment also can avoid pixel electrode and shared electrode to be short-circuited.
Its generation type of bigrid dot structure of the present embodiment is identical with the dot structure of the spendable material of each rete and the first embodiment, just repeats no more in this.Below, only be described in detail for difference on the dot structure design of the bigrid dot structure of the present embodiment and the first embodiment.
Fig. 4 be second embodiment of the invention the bigrid dot structure on look schematic diagram, the generalized section that ' and III-III ' paints along Fig. 4 hatching line II-II is with Fig. 3 H.
Please refer to Fig. 4 and Fig. 3 H, the bigrid dot structure of the present embodiment can be comprised of the pixel that is positioned at the data wire DL left and right sides.In the present embodiment, the pixel on data wire DL right side in the bigrid dot structure, its structure is identical with the dot structure (as shown in Figure 2) of the first embodiment.If the pixel on this right side is done for the first time mirror to scan line SL bearing of trend first, again data wire DL bearing of trend is done for the second time mirror, the pixel that then consists of with the method is the pixel in left side in the bigrid dot structure unit of the present embodiment.It should be noted that, the pixel of left and right sides is to share a data wire DL in the bigrid dot structure unit of the present embodiment, and the shared electrode CL of the pixel of the data wire DL left and right sides is electrically connected by the connecting portion CL-1 of same rete is mutual, as shown in Figure 4.
Because the bigrid dot structure of the present embodiment, the pixel of its data wire DL left and right sides is to share a data wire DL, therefore can reduce data wire DL number required in the dot structure, and then make required drive integrated circult assembly (the Integrated Circuit of display floater that comprises this bigrid dot structure, IC) decreased number, and then reach the effect that reduces manufacturing cost.
Yet, the bigrid dot structure of the present embodiment is easily because of the skew in the contraposition between the first metal layer 302 (shared electrode CL) and the second metal level 308 (storage electrode CE), cause the storage capacitors of the data wire DL left and right sides not of uniform size, and its display quality of display floater with this dot structure is seriously influenced.
In order to improve the problems referred to above, in the bigrid dot structure of the present embodiment, the storage electrode CE of the data wire DL left and right sides, its edge C E-a and each self-corresponding default gap edge O-a separately keeps one at least apart from d.The storage electrode CE of the data wire DL left and right sides, its edge C E-a and each self-corresponding common electrode edge C L-a separately keeps one at least apart from d '.In the present embodiment, above-mentioned apart from d and d ' greater than 0, preferably apart from d and d ' all greater than the maximum admissible error on the contraposition processing procedure (for example 3um).Thus, when the contraposition of 308 of the first metal layer 302 and the second metal levels had error, the storage capacitors value of the pixel of the data wire DL left and right sides was difficult for being affected.Therefore, and problem that the display quality that cause descend not of uniform size by the storage capacitors of the data line DL left and right sides is such as luminance nonuniformity and cross-talk (cross talk) etc., just can be improved.
Comprehensive the above, the present invention is by the design of reserving breach on the shared electrode, can avoid causing because light blockage coating is uneven part second metal level, semiconductor layer of hole below with etched with the door insulating barrier, and then cause the problem of shared electrode and pixel electrode formation short circuit.
In addition, via the suitable position that must arrange to reserve breach, can improve further the caused display quality decline of the bit errors problem because of the first metal layer and the second metal interlevel.
Although the present invention with embodiment openly as above; so it is not to limit the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when looking aforesaid the claim person of defining.
Claims (16)
1. a dot structure is characterized in that, comprising:
One substrate;
One the first metal layer is disposed on this substrate, and wherein this first metal layer comprises:
The one scan line;
One grid is electrically connected this scan line;
One shares electrode, separates with this scan line and has one and preset breach, wherein should be positioned on the edge of this shared electrode by default breach;
One gate insulation layer is disposed on this substrate and covers this first metal layer;
Semi-conductor layer is disposed on this gate insulation layer;
One second metal level is disposed on this semiconductor layer, and below this second metal level this semiconductor layer is arranged all, and wherein this second metal level comprises:
One data wire, staggered with this scan line;
One source pole is electrically connected this data wire;
One drain electrode;
One storage electrode is positioned at the top of this default breach;
One protective layer is disposed on this substrate and covers this second metal level, and this protective layer has an opening to expose this drain electrode;
One hole is positioned at this default breach and runs through this protective layer and expose this second metal level, and the size of this hole is less than the size of this default breach; And
One pixel electrode is disposed on this protective layer and inserts in this hole, and wherein this pixel electrode sees through this opening and is electrically connected with this drain electrode, and sees through this hole and the electric connection of this second metal level.
2. dot structure as claimed in claim 1 is characterized in that, this hole that runs through this protective layer and be positioned at this default breach does not run through this second metal level, this semiconductor layer and this gate insulation layer.
3. dot structure as claimed in claim 1; it is characterized in that; this hole that runs through this protective layer and be positioned at this default breach more runs through this second metal level, this semiconductor layer and this gate insulation layer, and exposes the sidewall of this second metal level, the sidewall of this semiconductor layer, the sidewall of this gate insulation layer and the surface of this substrate.
4. dot structure as claimed in claim 1 is characterized in that, this shared electrode is positioned at the peripheral of this pixel electrode and overlaps with its part.
5. dot structure as claimed in claim 4 is characterized in that, the part that this shared electrode and this pixel electrode overlap consists of a storage capacitors.
6. dot structure as claimed in claim 1 is characterized in that, the part that this shared electrode and this storage electrode overlap consists of a storage capacitors.
7. dot structure as claimed in claim 1 is characterized in that, this shared electrode has at least one bending place, and this presets breach and this bending place keeps a distance at least.
8. dot structure as claimed in claim 1 is characterized in that, the edge of this default breach and this storage electrode keeps a distance at least.
9. a bigrid dot structure is characterized in that, comprising:
One substrate;
One the first metal layer is disposed on this substrate, and wherein this first metal layer comprises:
Two scan lines;
Two grids are electrically connected respectively those scan lines;
One shares electrode, separate with those scan lines, and this shared electrode has one and is positioned at the default breach in two on this shared electrode edge;
One gate insulation layer is disposed on this substrate and covers this first metal layer;
Semi-conductor layer is disposed on this gate insulation layer;
One second metal level is disposed on this semiconductor layer, and below this second metal level this semiconductor layer is arranged all, and wherein this second metal level comprises:
One data wire, staggered with those scan lines;
Two source electrodes are electrically connected with this data wire separately;
Two drain electrodes;
Two storage electrodes lay respectively at the corresponding top that should preset breach;
One protective layer is disposed on this substrate and covers this second metal level, and this protective layer has two openings to expose those drain electrodes;
Two holes lay respectively in those default breach and run through this protective layer and expose this second metal level, and the size of those holes is less than the size of those default breach; And
Two pixel electrodes are disposed on this protective layer and also insert respectively in those holes, and wherein those pixel electrodes see through respectively those openings and those drain electrode electric connections, and see through those holes and the electric connection of those the second metal levels.
10. dot structure as claimed in claim 9 is characterized in that, this hole that runs through this protective layer and be positioned at this default breach does not run through this second metal level, this semiconductor layer and this gate insulation layer.
11. dot structure as claimed in claim 9; it is characterized in that; this hole that runs through this protective layer and be positioned at this default breach more runs through this second metal level, this semiconductor layer and this gate insulation layer, and exposes the sidewall of this second metal level, the sidewall of this semiconductor layer, the sidewall of this gate insulation layer and the surface of this substrate.
12. bigrid dot structure as claimed in claim 9 is characterized in that this shared electrode lays respectively at the periphery of those pixel electrodes, and overlaps with pixel electrode part respectively.
13. bigrid dot structure as claimed in claim 12 is characterized in that, this shared electrode consists of a storage capacitors with the part that those pixel electrodes overlap respectively.
14. bigrid dot structure as claimed in claim 9 is characterized in that, this shared electrode consists of a storage capacitors with the part that those storage electrodes overlap respectively.
15. bigrid dot structure as claimed in claim 9 is characterized in that this shared electrode respectively has at least one bending place, and this presets breach and this bending place keeps a distance at least.
16. bigrid dot structure as claimed in claim 9 is characterized in that, those default breach keep a distance at least with the edge of corresponding those storage electrodes respectively.
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| CN103176320B (en) * | 2011-12-22 | 2015-12-09 | 上海中航光电子有限公司 | Transversely arranged dot structure, liquid crystal indicator and preparation method thereof |
| CN105974690B (en) * | 2016-07-22 | 2019-04-26 | 京东方科技集团股份有限公司 | A kind of mask plate, array substrate, display panel and display device |
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| CN102130136A (en) | 2011-07-20 |
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