CN102130001A - Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device - Google Patents
Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device Download PDFInfo
- Publication number
- CN102130001A CN102130001A CN2010100273138A CN201010027313A CN102130001A CN 102130001 A CN102130001 A CN 102130001A CN 2010100273138 A CN2010100273138 A CN 2010100273138A CN 201010027313 A CN201010027313 A CN 201010027313A CN 102130001 A CN102130001 A CN 102130001A
- Authority
- CN
- China
- Prior art keywords
- preparation
- ion
- layer
- double
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 6
- -1 nitrogen ion Chemical class 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 210000000746 body region Anatomy 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a preparation method of a trench double gate power MOS (Metal Oxide Semiconductor) device. The preparation method comprises the following steps of: carrying out vertical ion implantation to form a first well region below a trench after trench etching is formed, wherein the conduction type of the first well region is same as that of a body region in an MOS transistor; and preparing an oxide layer between double gates by adopting a thermal oxidization process. The preparation method disclosed by the invention ensures that the parasitic capacitance between a gate electrode and a drain electrode is smaller, and therefore, the MOS device has quicker switching speed and less switching loss.
Description
Technical field
The present invention relates to a kind of groove type double-layer grid power MOS preparation of devices method.
Background technology
Groove type MOS transistor is a kind of MOS transistor type of grid preparation in groove, and is breakdown voltage resistant more than 20V usually.Existing more advanced groove type MOS transistor is the groove type double-layer grid power MOS device.Figure 1 shows that the transistorized structural representation of a kind of existing groove type double-layer grid power MOS, the structure of this MOS transistor, bucking electrode separates switch electrode (being grid) and drain region (i.e. shielding), effectively reduce gate leakage capacitance (that is the miller capacitance in the circuit), thereby reduce the switching time and the switching loss of device.
Summary of the invention
Technical problem to be solved by this invention provides a kind of groove type double-layer grid power MOS preparation of devices method, and it can improve the withstand voltage of device under the situation identical with the traditional structure on state resistance.
For solving the problems of the technologies described above, groove type double-layer grid power MOS preparation of devices method of the present invention, after etching groove forms, carrying out vertical ion is infused in described beneath trenches and forms first well region, the conductivity type opposite in tagma in the conduction type of described first well region and the described MOS transistor; Adopt the oxide layer between the two-layer grid of hot oxygen prepared simultaneously.
Preparation method of the present invention, channel bottom at the groove type double-layer grid power MOS device forms well structure, charge carrier in this structure first well region and the epitaxial loayer exhausts mutually, makes that the parasitic capacitance between grid and the drain electrode is littler, therefore has switching speed and switching loss still less faster.Above-mentioned carrier depletion make the MOS device by the time have higher withstand voltage.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the structural representation of existing groove type double-layer grid power MOS device;
Fig. 2 is the structural representation of the groove type power double-layer grid power MOS device of employing method preparation of the present invention;
Fig. 3 is for implementing the structural representation behind the etching groove among the preparation method of the present invention;
Fig. 4 is for implementing the structural representation after beneath trenches among the preparation method of the present invention forms first well region;
Fig. 5 is the structural representation after lower-layer gate forms among the enforcement preparation method of the present invention;
Fig. 6 is the structural representation after implementing preparation method of the present invention grid forming at the middle and upper levels;
Fig. 7 is for implementing the schematic diagram that the source region ion injects among the preparation method of the present invention;
Fig. 8 is for implementing the structural representation behind the contact hole etching among the preparation method of the present invention;
Fig. 9 is for implementing the structural representation behind the ohmic contact regions of contact hole bottom among the preparation method of the present invention.
Embodiment
Groove type double-layer grid power MOS preparation of devices method of the present invention, for after etching groove forms, carrying out vertical ion is infused in beneath trenches and forms first well region, the conductivity type opposite in tagma in the conduction type of first well region and the MOS transistor, adopt the oxide layer between the two-layer grid of hot oxygen prepared simultaneously, the final mos transistor structure that forms as shown in Figure 2.Method of the present invention is integrated among the transistorized preparation technology of traditional groove type double-layer grid power MOS, is specially:
(1) under the protection that hard barrier layer is arranged, etched substrate forms groove, then beneath trenches is carried out ion and injects, and the conduction type of the ion that is injected is identical with the tagma, forms the first well region (see figure 4) in beneath trenches.Preferably carry out annealing in process after injecting again to advance the degree of depth of trap.The ion dose scope of injecting is: 10
12～10
14Atom/cm
2, the injection energy is 10-2000KeV.The temperature of annealing in process is 350-1200 ℃, and the processing time is 10 seconds-10 hours.
2) then being the oxide layer growth of trench wall, is the deposit and time quarter of ground floor polysilicon afterwards, forms lower-layer gate (be the bucking electrode layer of this device, see Fig. 5).Before the oxide layer growth of trench wall, also can carry out the growth of sacrificial oxide layer and remove technology.And the ion implantation technology of beneath trenches also can be carried out after the sacrificial oxidation layer growth, and ion is removed this sacrificial oxide layer after injecting again.
3) then be the oxide layer that adopts on the hot oxygen technology growth lower-layer gate, the oxide layer of trenched side-wall also forms in the lump.A kind of concrete way is injected into trenched side-wall surface (being the flute surfaces that is not covered by lower-layer gate) for adopting ion implantation technology earlier with the nitrogen ion, and the lower-layer gate surface under not being injected into; Then carry out hot oxide growth, make the silicon of trenched side-wall and the polysilicon oxidation on lower-layer gate surface generate oxide layer, slower because of the oxidation rate that the trenched side-wall that the nitrogen ion exists is arranged than the oxidation rate of polysilicon, therefore can form the oxide layer of enough thick and even compact on the lower-layer gate surface.In the nitrogen ion implantation technology, the nitrogen ion dose that is injected is: 10
11～10
16Atom/cm
2, the angle of nitrogen ion beam and substrate vertical axis is: 1～85 degree, the injection energy is: 10～200KeV.And another kind of way is injected into the surface of lower-layer gate for adopting earlier ion implantation technology with fluorine ion, and trenched side-wall does not inject fluorine ion; Carry out hot oxide growth afterwards, make the silicon of trenched side-wall and the polysilicon oxidation on lower-layer gate surface generate oxide layer, also can on lower-layer gate, form the oxide layer of enough thick and even compact.In the fluorine ion injection technology, the implantation dosage of fluorine ion is: 10
11～10
16Atom/cm
2, the injection energy is: 10～200KeV.
4) then be the deposit of second layer polysilicon, form upper strata grid (see figure 6) (being also referred to as switch electrode) after the etching.
5) then be that the ion that adopts common process to carry out the tagma injects and the ion in source region injects (see figure 7) equally, and at film, then film formation contact hole between etch layer between illuvium on the substrate that has formed said structure.
6) (see figure 8) after contact hole etching forms is carried out ion and is injected below contact hole, form ohmic contact regions, with contact hole in the tungsten metal carry out the ohmic contact (see figure 9).
The double-deck grate MOS device processing procedure of follow-up other technology and traditional groove is in full accord, the final device architecture that forms as shown in Figure 2.
Claims (10)
1. groove type double-layer grid power MOS preparation of devices method, it is characterized in that: after etching groove forms, carry out vertical ion and be infused in described beneath trenches and form first well region, the conduction type of described first well region is identical with the conduction type in tagma in the described MOS device; Adopt the oxide layer between the double-deck grid of hot oxygen prepared simultaneously.
2. preparation method according to claim 1 is characterized in that: described ion implantation step forms afterwards at groove, the sacrificial oxidation layer growth advances row.
3. preparation method according to claim 1 is characterized in that: described ion implantation step is behind the sacrificial oxidation layer growth, and described sacrificial oxide layer carries out before removing.
4. according to the described preparation method of each claim in the claim 1 to 3, it is characterized in that: described ion injects, and the ion dose that is injected is 10
12～10
14Atom/cm
2, the injection energy is 10-2000KeV.
5. according to the described preparation method of each claim in the claim 1 to 3, it is characterized in that: described carrying out also carries out annealing in process, to advance formed first well region after ion injects.
6. preparation method according to claim 5 is characterized in that: the temperature of described annealing in process is: 350-1200 ℃, the time is: 10 seconds-10 hours.
7. according to the described preparation method of each claim among the claim 1-3, it is characterized in that: after the lower-layer gate preparation forms in the described double-deck grid, carry out before the growth of oxide layer on the described lower-layer gate, increase the step that fluorine ion is injected into described lower-layer gate surface.
8. according to the described preparation method of claim 7, it is characterized in that: the implantation dosage of described fluorine ion is 10
11～10
16Atom/cm
2, the injection energy is 10～200KeV.
9. according to the described preparation method of each claim among the claim 1-3, it is characterized in that: after the lower-layer gate preparation forms in the described double-deck grid, carry out before the growth of oxide layer on the described lower-layer gate, increase the step that the nitrogen ion is injected into the trenched side-wall surface.
10. according to the described preparation method of claim 9, it is characterized in that: the implantation dosage of described nitrogen ion is 10
11～10
16Atom/cm
2, the injection energy is 10～200KeV, implant angle is the 1-85 degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010027313A CN102130001B (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010027313A CN102130001B (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102130001A true CN102130001A (en) | 2011-07-20 |
| CN102130001B CN102130001B (en) | 2012-10-03 |
Family
ID=44268029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010027313A Active CN102130001B (en) | 2010-01-20 | 2010-01-20 | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102130001B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594348A (en) * | 2012-08-17 | 2014-02-19 | 茂达电子股份有限公司 | Method for manufacturing semiconductor element with low miller capacitance |
| CN104332401A (en) * | 2014-09-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Manufacture method for thermal oxidation dielectric layer among polycrystalline silicon of groove type double-layer grid MOS |
| CN109216175A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The gate structure and its manufacturing method of semiconductor devices |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342709B1 (en) * | 1997-12-10 | 2002-01-29 | The Kansai Electric Power Co., Inc. | Insulated gate semiconductor device |
| JP2001284584A (en) * | 2000-03-30 | 2001-10-12 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| TWI400757B (en) * | 2005-06-29 | 2013-07-01 | Fairchild Semiconductor | Methods for forming shielded gate field effect transistors |
-
2010
- 2010-01-20 CN CN201010027313A patent/CN102130001B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103594348A (en) * | 2012-08-17 | 2014-02-19 | 茂达电子股份有限公司 | Method for manufacturing semiconductor element with low miller capacitance |
| CN104332401A (en) * | 2014-09-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Manufacture method for thermal oxidation dielectric layer among polycrystalline silicon of groove type double-layer grid MOS |
| CN104332401B (en) * | 2014-09-23 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The manufacture method of the hot oxygen medium layer of groove type double-layer grid MOS inter polysilicons |
| CN109216175A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The gate structure and its manufacturing method of semiconductor devices |
| CN109216175B (en) * | 2017-07-03 | 2021-01-08 | 无锡华润上华科技有限公司 | Gate structure of semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102130001B (en) | 2012-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5323359B2 (en) | Power MOS device | |
| US20160190283A1 (en) | Fabrication of mosfet device with reduced breakdown voltage | |
| CN102130000B (en) | Method for preparing channel-type double-gate MOS device | |
| CN102569411B (en) | Semiconductor device and method for manufacturing the same | |
| JP2008103683A (en) | Semiconductor device having space-saving edge structure | |
| CN108172563B (en) | A kind of ditch flute profile device and its manufacturing method with self-aligned contact hole | |
| CN103151376A (en) | Trench-gate RESURF semiconductor device and manufacturing method | |
| CN103035521A (en) | Process method for achieving minor carrier storage layer groove-type insulated gate bipolar translator (IGBT) | |
| CN102130169B (en) | Power MOS (Metal Oxide Semiconductor) device structure with shielding grid and manufacturing method thereof | |
| CN102130006B (en) | Method for preparing groove-type double-layer gate power metal oxide semiconductor (MOS) transistor | |
| CN102104068A (en) | Structure of power MOS (Metal Oxide Semiconductor) transistor and preparation method thereof | |
| CN102130001B (en) | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device | |
| CN104681438B (en) | A kind of forming method of semiconductor devices | |
| CN102130007B (en) | Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) transistor | |
| CN102103997B (en) | Structure of groove type power MOS (Metal Oxide Semiconductor) device and preparation method thereof | |
| CN109427881A (en) | Trench gate mosfet and manufacturing method with shield grid | |
| CN102956487B (en) | Manufacture method of isolation type power transistor | |
| CN102104001B (en) | Method for improving breakdown voltage of trench type power MOS device | |
| CN102130004A (en) | Preparation method of trench type MOS (metal oxide semiconductor) device | |
| CN105720089A (en) | Super junction and manufacturing method therefor | |
| CN102130003A (en) | Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device | |
| CN102103998B (en) | Structure and preparation method of trench metal oxide semiconductor (MOS) transistor | |
| CN103811548A (en) | MOSFET device with low miller capacitance and method of making the same | |
| CN102130055A (en) | Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device | |
| CN104835736A (en) | Method of manufacturing depletion type double-diffused metal oxide semiconductor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |