CN102103998B - Structure and preparation method of trench metal oxide semiconductor (MOS) transistor - Google Patents
Structure and preparation method of trench metal oxide semiconductor (MOS) transistor Download PDFInfo
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- CN102103998B CN102103998B CN 200910201959 CN200910201959A CN102103998B CN 102103998 B CN102103998 B CN 102103998B CN 200910201959 CN200910201959 CN 200910201959 CN 200910201959 A CN200910201959 A CN 200910201959A CN 102103998 B CN102103998 B CN 102103998B
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Abstract
The invention discloses a preparation method of a trench metal oxide semiconductor (MOS) transistor. The method comprises the following steps: forming a trench of the trench MOS transistor; injecting ions into the trench to form a well with the same conductive type and body region at the bottom of the trench; and forming an injection layer with the same conductive type and body region on the inner wall surface and silicon surface of partial trench, wherein the injection layer is used for electrically connecting the well at the bottom of the trench and a source by utilizing a structure of the contact hole which is formed subsequently. The invention also discloses a trench MOS transistor structure, wherein the well with the same conductive type and body region is formed at the bottom of the trench gate of the trench MOS transistor; and the well is electrically connected with the source. By utilizing the preparation method provided by the invention, the breakdown voltage of the prepared device is improved.
Description
Technical field
The present invention relates to a kind of preparation method of trenched mos transistor.The invention still further relates to a kind of trenched mos transistor structure.
Background technology
Groove type MOS transistor is grid and is prepared in a kind of MOS transistor type in the groove, and is breakdown voltage resistant more than 20V usually.Shown in Figure 1 is a kind of structural representation of traditional groove type MOS transistor, and in this kind groove type MOS transistor, the maximum place of field intensity is trenched side-wall and the corner that the tagma forms, and therefore should locate the key point of the withstand voltage raising of limiting device.
Summary of the invention
Technical problem to be solved by this invention provides a kind of preparation method of trenched mos transistor, and it can improve the withstand voltage of device under the situation identical with the traditional structure on state resistance.
For solving the problems of the technologies described above; The preparation method of trenched mos transistor of the present invention; For after the groove at trenched mos transistor forms; Comprise to said groove carry out that ion is infused in that channel bottom forms the step of the conduction type trap identical with the tagma and on part trench wall surface the step of the implanted layer identical with the tagma with silicon face formation conduction type, the contact hole that said implanted layer is used to utilize follow-up formation is electrically connected the trap of said channel bottom with source electrode.
Trenched mos transistor structure of the present invention, the conduction type trap identical with the tagma arranged at the trench gate bottom of this trenched mos transistor, and this trap is electrically connected with source electrode.
Preparation method of the present invention; By forming deep trap in the trench-gate bottom; And, the channel bottom deep trap is connected back and source end short circuit by contact hole, thereby the epitaxial loayer depletion widths improves greatly below when device ends, making the tagma in part trench wall and bottom formation low resistance; And then the weak turning of shield trenches sidewall, the breakdown voltage of device is improved.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the structural representation of traditional trenched mos transistor;
Fig. 2 is the domain vertical view instance of the trenched mos transistor of employing method preparation of the present invention;
Fig. 3 is the cross section structure sketch map of Fig. 2;
Fig. 4 is the structural representation behind the etching groove among the preparation method of embodiment of the present invention;
Fig. 5 is the structural representation after channel bottom injects among the preparation method of embodiment of the present invention;
Fig. 6 is the structural representation after trenched side-wall surface and the silicon face injection among the preparation method of embodiment of the present invention;
Fig. 7 is the structural representation after grid forms among the preparation method of embodiment of the present invention;
Fig. 8 is the sketch map that the tagma ion injects among the preparation method of embodiment of the present invention;
Fig. 9 is the sketch map that the source region ion injects among the preparation method of embodiment of the present invention;
Figure 10 is the structural representation behind the contact hole etching among the preparation method of embodiment of the present invention;
Figure 11 is the sketch map behind the injection region, contact hole bottom among the preparation method of embodiment of the present invention;
Figure 12 is for adopting the structural representation of the prepared trenched mos transistor of preparation method of the present invention;
Among the above-mentioned figure, a is along AA ' face structural representation among Fig. 2, and b is along BB ' face structural representation among Fig. 2.
Embodiment
The preparation method of trenched mos transistor of the present invention finally forms trenched mos transistor structure as shown in Figure 3.Fig. 2 prepares the domain vertical view of groove nmos pass transistor for adopting preparation method of the present invention, is that example describes with the groove nmos pass transistor, and method of the present invention is integrated in traditional trenched mos transistor technology, is being specially:
(1) under the protection that hard barrier layer is arranged, etched substrate forms groove, then channel bottom is carried out ion and injects, and the ionic conduction type of being injected is identical with the tagma, forms the trap (see figure 5) at channel bottom.Preferably carry out annealing in process after injecting again to advance the degree of depth of trap.The ion dose scope of injecting is: 10
12～10
15Atom/cm
2, the injection energy is: 10～2000KeV.The temperature of annealing in process is: 400～1200 ℃, the processing time is: 10 seconds～10 hours.
(2) then adopt ion implantation technology, in part trench wall surface and the silicon face formation conduction type implanted layer (see figure 6) identical with the tagma, the contact hole that is used to utilize follow-up formation is electrically connected the trap of said channel bottom with source electrode.Form in the technology of implanted layer with silicon face on part trench wall surface, the angle that ion beam and vertical axis inject in institute is: 1～80 spends, and the injection ion dose is greater than 10
14Atom/cm
2, the injection energy is 1～100kev.
(3) the growth sacrificial oxide layer is then removed sacrificial oxide layer, then forms complete grid (see figure 7) for gate oxide growth, polysilicon deposit and polysilicon return to carve.These technologies are with earlier consistent with technology.
(4) formation in tagma and source region (seeing Fig. 8 and Fig. 9).
(5) interlayer film deposit, film forms the contact hole (see figure 10) between etch layer.
(6) ion injects, and forms the contact zone of high concentration in the contact hole bottom, to form ohmic contact regions (seeing Figure 11).
(7) next fill and the metal deposit for contact hole, etching finally forms structure shown in figure 12.
The ion implantation step of groove of the present invention also after the sacrificial oxidation layer growth, carries out before removing.
In the above-mentioned introduction, step 3 to step 7 is existing standard technology commonly used.The present invention is through forming deep trap at channel bottom, and forms ohmic contact at trenched side-wall and connect back and source end short circuit through contact opening, thereby makes the depletion region of the outer Yanzhong of deep trap can produce pinch off, improves the withstand voltage of device.
Claims (8)
1. the preparation method of a trenched mos transistor; It is characterized in that: after the groove of said trenched mos transistor forms; Comprise to said groove carry out that ion is infused in that channel bottom forms the step of the conduction type trap identical with the tagma and on part trench wall surface the step of the implanted layer identical with the tagma with silicon face formation conduction type, the contact hole that said implanted layer is used to utilize follow-up formation is electrically connected the trap of said channel bottom with source electrode.
2. preparation method according to claim 1 is characterized in that: said ion implantation step forms afterwards at groove, the sacrificial oxidation layer growth advances row.
3. preparation method according to claim 1 is characterized in that: said ion implantation step is behind the sacrificial oxidation layer growth, and said sacrificial oxide layer carries out before removing.
4. according to the described preparation method of each claim in the claim 1 to 3, it is characterized in that: after the said ion implantation technology that forms trap at channel bottom, also carry out annealing in process, to advance formed trap.
5. according to the described preparation method of each claim in the claim 1 to 3, it is characterized in that: said in the ion implantation technology of channel bottom formation trap, the ion dose scope of injection is: 10
12～10
15Atom/cm
2, the injection energy is: 10～2000KeV.
6. according to the described preparation method of each claim in the claim 1 to 3; It is characterized in that: said in the technology of part trench wall surface and silicon face formation implanted layer; Inject ion and vertical axis angle be: 1～80 degree, the ion dose that is injected is greater than 10
14Atom/cm
2, the injection energy is 1～100keV.
7. preparation method according to claim 4 is characterized in that: the temperature of said annealing in process is: 400～1200 ℃, the time is: 10 seconds～10 hours.
8. a trenched mos transistor structure is characterized in that: bottom the trench gate of said trenched mos transistor, the conduction type trap identical with the tagma arranged, and said trap is electrically connected with source electrode; At part trench wall surface and the silicon face formation conduction type implanted layer identical with the tagma, the contact hole that utilizes follow-up formation is electrically connected the trap of said channel bottom with the source electrode of silicon face.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910201959 CN102103998B (en) | 2009-12-18 | 2009-12-18 | Structure and preparation method of trench metal oxide semiconductor (MOS) transistor |
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| CN 200910201959 CN102103998B (en) | 2009-12-18 | 2009-12-18 | Structure and preparation method of trench metal oxide semiconductor (MOS) transistor |
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| CN102103998A CN102103998A (en) | 2011-06-22 |
| CN102103998B true CN102103998B (en) | 2012-12-12 |
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| TW201443999A (en) * | 2013-05-14 | 2014-11-16 | Anpec Electronics Corp | Method for fabricating trench type semiconductor power device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342709B1 (en) * | 1997-12-10 | 2002-01-29 | The Kansai Electric Power Co., Inc. | Insulated gate semiconductor device |
| US20060273386A1 (en) * | 2005-05-26 | 2006-12-07 | Hamza Yilmaz | Trench-gate field effect transistors and methods of forming the same |
| CN101578689A (en) * | 2005-06-29 | 2009-11-11 | 飞兆半导体公司 | Structures and methods for forming shielded gate field effect transistors |
-
2009
- 2009-12-18 CN CN 200910201959 patent/CN102103998B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6342709B1 (en) * | 1997-12-10 | 2002-01-29 | The Kansai Electric Power Co., Inc. | Insulated gate semiconductor device |
| US20060273386A1 (en) * | 2005-05-26 | 2006-12-07 | Hamza Yilmaz | Trench-gate field effect transistors and methods of forming the same |
| CN101578689A (en) * | 2005-06-29 | 2009-11-11 | 飞兆半导体公司 | Structures and methods for forming shielded gate field effect transistors |
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| CN102103998A (en) | 2011-06-22 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |