CN102129968A - Double-patterning method - Google Patents
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- CN102129968A CN102129968A CN2010106194445A CN201010619444A CN102129968A CN 102129968 A CN102129968 A CN 102129968A CN 2010106194445 A CN2010106194445 A CN 2010106194445A CN 201010619444 A CN201010619444 A CN 201010619444A CN 102129968 A CN102129968 A CN 102129968A
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Abstract
The invention relates to a double-patterning method which comprises the following steps: sequentially depositing a pattern layer and spin-coating a first photoresist layer on a substrate from bottom to top; utilizing a first-layer photoetching pattern plate to photoetch the first photoresist layer, and taking the first photoresist layer after photoetching as a mask for etching the pattern layer; removing the first photoresist layer, and depositing a hard mask layer on the surface of the pattern layer and a pattern gap formed by etching the pattern layer; performing planarization treatment on the surface of the hard mask layer; depositing a second photoresist layer on the flat surface of the hard mask layer; utilizing a second-layer photoetching pattern plate to photoetch the second photoresist layer, and taking the second photoresist layer after photoetching as the mask for etching the hard mask layer and the pattern layer; and removing the second photoresist layer and the hard mask layer. By adopting the double-patterning method, the planeness of the surface on which the second-layer photoetching process is performed is increased, the process window of the second-layer photoetching process is further added, and the second-layer photoetching appearance control capability and the etching process window can be improved.
Description
Technical field
The present invention relates to the integrated circuit fabrication process field, relate in particular to a kind of double-pattern method.
Background technology
Be accompanied by the continuous progress of integrated circuit fabrication process, it is more and more littler that the volume of semiconductor device and critical size are just becoming.Along with critical size is more and more littler, IC industry faces increasing challenge.One of significant challenge that is faced is because the photo-etching machine exposal light source determines, the photoetching critical size is near the limiting resolution of exposure bench.The semiconductor product industry is devoted to prolong the life-span of optical lithography platform always, and multiple resolution enhance technology and optics close on the widespread usage that correction technique has obtained industry.
Photoetching resolution enhancement techniques such as double-patternization, photoetching double exposure, high index of refraction immersion lithography and extreme ultraviolet lithography have generally been expressed great expectations at realization 32nm technology node.Because the raising of the productivity ratio that the progress of mask aligner software and hardware technology causes, the significance level of double-pattern technology and photoetching double exposure grows with each passing day, and has become present industry 32nm mainstream solution.
The starting point of double-pattern technology is two layer patterns that the design configuration that will exceed the mask aligner limiting resolution is split into the resolution that mask aligner can reach, and produce corresponding two reticle, in the double-pattern metallization processes by photoetching-etching-photoetching-etching, finally reach the final graphics of demand then.
Fig. 1 is each step schematic diagram of a kind of double-pattern method of prior art to Fig. 5.At first, on substrate 10 successively the deposition or the growth finish graph layer 11, hard mask layer 12 and first photoresist layer 13, as shown in Figure 1.Then, expose with 14 pairs of described first photoresist layers 13 of the first litho pattern version, described first photoresist layer 13 of development after etching and described hard mask layer 12, figure on the described first litho pattern version 14 is formed on the described hard mask layer 12, thereby finish the etching first time, as shown in Figure 2 to described hard mask layer 12.
Remove described first photoresist layer 13 and clean, deposition second photoresist layer 15 on described hard mask layer 12, with the second litho pattern version (figure do not show) to described second photoresist layer 15 expose, development, etching processing, make the figure on the described second litho pattern version be formed on described second photoresist layer 15, as shown in Figure 3.With described second photoresist layer 15 is the described hard mask layer 12 of mask etching, removes described second photoresist layer 15 and cleaning then, and the figure on the described first litho pattern version 14 and the second litho pattern version is formed on the described hard mask layer 12, as shown in Figure 4.With described hard mask layer 12 is mask, and described graph layer 11 is carried out etching, and after described hard mask layer 12 was removed, double-pattern metallization processes flow process was finished, as shown in Figure 5.
Although the double-pattern method of prior art has realized the extension to limiting resolution, this technology has the shortcoming of self.Wherein one of emphasis is when finishing first time to described hard mask layer 12 after the etching, and the gap between described hard mask layer 12 figures can make a big impact to the evenness on hard mask layer surface.Carrying out the second time during photoetching process, the antireflecting coating of figure spin coating and photoresist need be filled the inter-pattern space between the described hard mask layer 12, make at the thickness evenness of the photomask surface glue in interstitial area and non-gap widely different, cause to the second time photoetching process process window and photoresist morphology control cause very big difficulty.And because the distance of the inter-pattern space of described hard mask layer 12 and described second lithography layer 15 is too near, the inter-pattern space of described hard mask layer 12 can cause interference to the figure optical imagery that described second lithography layer 15 carries out.
Summary of the invention
The object of the present invention is to provide a kind of flatness that promptly can improve photoresist layer in the photoetching process can reduce the double-pattern method that pattern imaging disturbs again in the second time.
A kind of double-pattern method comprises the steps: from bottom to top deposition pattern layer and spin coating first photoresist layer on substrate successively; Utilize described first photoresist layer of ground floor litho pattern version photoetching, and be the described graph layer of mask etching with described first photoresist layer after the photoetching; Remove described first photoresist layer, in the inter-pattern space that the surface of described graph layer and described graph layer etching form, deposit hard mask layer; Planarization is carried out on surface to described hard mask layer; Flat surfaces at described hard mask layer deposits second photoresist layer; Utilize described second photoresist layer of second layer litho pattern version photoetching and be described hard mask layer of mask etching and described graph layer with described second photoresist layer after the photoetching; Remove described second photoresist layer and described hard mask layer.
A kind of double-pattern method comprises the steps: from bottom to top deposition pattern layer and spin coating first photoresist layer on substrate successively; Utilize described first photoresist layer of ground floor litho pattern version photoetching, and be the described graph layer of mask etching with described first photoresist layer after the photoetching; Remove described first photoresist layer, in the inter-pattern space that the surface of described graph layer and described graph layer etching form, deposit hard mask layer; Planarization is carried out on surface to described hard mask layer; Flat surfaces at described hard mask layer deposits second photoresist layer; Utilize described second photoresist layer of second layer litho pattern version photoetching, be the described hard mask layer of mask etching with described second photoresist layer after the photoetching; Remove described second photoresist layer, with the described graph layer of described hard mask layer etching after the etching; Remove described hard mask layer.
The preferred a kind of technical scheme of the present invention utilizes the mode of cmp that planarization is carried out on the surface of described hard mask layer.
The preferred a kind of technical scheme of the present invention, the material of described hard mask layer are silicon nitride or silicon oxynitride or tetraethyl-metasilicate or nitrogenize is smooth or titanium nitride.
The preferred a kind of technical scheme of the present invention, the thickness range of described hard mask layer is 100～1000 nanometers.
The preferred a kind of technical scheme of the present invention, described graph layer are the polysilicon lines-groove layer of semiconductor device or the through hole contact layer of semiconductor device.
The preferred a kind of technical scheme of the present invention utilizes chemistry or physical vapour deposition (PVD) mode to form described hard mask layer.
The preferred a kind of technical scheme of the present invention is removed described hard mask layer with wet etching.
Compared with prior art, double-pattern method of the present invention is owing to be ability deposited hard mask layer after photoetching of ground floor figure and etching, and increased the flatening process of hard mask layer, the influence of having avoided the gap between the figure behind the traditional approach ground floor pattern etching that the evenness on hard mask layer surface is caused, make that photoresist is spun on the smooth plane when carrying out second layer photoetching process, so the second photoresist layer uniformity improves greatly, thereby increased the process window of second layer photoetching process.Further, double-pattern method of the present invention has avoided in the traditional approach because the too near process disturbance that causes of ground floor inter-pattern space and second layer litho pattern distance, thereby makes second layer photoetching morphology control ability and etching technics window all be improved.
Description of drawings
Fig. 1 is each step schematic diagram of a kind of double-pattern method of prior art to Fig. 5.
Fig. 6 is each step schematic diagram of first execution mode of double-pattern method of the present invention to Figure 12.
Figure 13 is the part steps schematic diagram of second execution mode of double-pattern method of the present invention to Figure 15.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
In the double-pattern method of the present invention, in the double-pattern metallization processes of photoetching-etching-photoetching-etching, graph layer is finished in deposition or growth on substrate, cancel the hard mask layer depositing operation of traditional approach earlier, directly on graph layer, carry out the photoetching first time and the etching of double-patternization, and remove photoresist and clean.On the silicon chip of finishing the ground floor graphics art, by chemistry or physical vapour deposition (PVD) mode deposited hard mask layer, and the hard mask layer of deposition being finished by chemical machinery mask mode carries out flatening process, finish the photoetching second time of carrying out double-patternization on the hard mask layer of flatening process, and finishing etching hard mask layer.Utilize hard mask layer that the final graphics layer is carried out etching, finish and remove photoresist and clean, remove hard mask layer, finally finish the double-pattern manufacturing process after the optimization with wet etching.Arrive Figure 15 below in conjunction with Fig. 6, in detail each step of described double-pattern method of the present invention.
See also Fig. 6 to Figure 12, Fig. 6 is each step schematic diagram of first execution mode of double-pattern method of the present invention to Figure 12.
Utilize described first photoresist layer 22 of ground floor litho pattern version 23 photoetching, and be the described graph layer 21 of mask etching, as shown in Figure 7 with described first photoresist layer 22 after the photoetching.The figure of described ground floor litho pattern version 23 is formed on the described graph layer 21.
Remove described first photoresist layer 22 and cleaning, thereby finish the ground floor figure of double-pattern metallization processes.Deposition hard mask layer 24 in the inter-pattern space that the surface of described graph layer 21 and described graph layer 21 etchings form, as shown in Figure 8.Preferably, utilize chemistry or physical vapour deposition (PVD) mode to form described hard mask layer 24, the material of described hard mask layer 24 is silicon nitride or silicon oxynitride or tetraethyl-metasilicate (TEOS) or nitrogenize is smooth or all materials that can be deposited as hard mask layer and can be flattened by the cmp mode such as titanium nitride.Preferably, the thickness range of described hard mask layer 24 is 100～1000 nanometers.
Planarization is carried out on surface to described hard mask layer 24, as shown in Figure 9.Preferably, utilize the mode of cmp that planarization is carried out on the surface of described hard mask layer 24.
Flat surfaces at described hard mask layer 24 deposits second photoresist layer 25, utilizes second layer litho pattern version (figure does not show) described second photoresist layer 25 of photoetching, as shown in figure 10.
With described second photoresist layer 25 after the photoetching is mask, described hard mask layer 24 of etching and described graph layer 21, as shown in figure 11.The figure of described second layer litho pattern version is formed on the described graph layer 21, thereby finishes the second layer figure of double-pattern metallization processes.
Remove described second photoresist layer 25 and described hard mask layer 24, as shown in figure 12, thereby finish double-pattern method of the present invention.Preferably, adopt the mode of wet etching to remove described hard mask layer 24.
See also Figure 13 to Figure 15, Fig. 3 is the part steps schematic diagram of second execution mode of double-pattern method of the present invention to Figure 15.The double-pattern method of present embodiment is similar to the double-pattern method of first execution mode, and difference is, behind photoetching second photoresist layer, is mask with second photoresist layer 35 after the photoetching, the described hard mask layer 34 of etching, as shown in figure 13.Removing described second photoresist layer 35, is the described graph layer 31 of mask etching with the described hard mask layer after the etching 24, as shown in figure 14.Remove described hard mask layer 24,, as shown in figure 15, thereby finish the second layer figure of double-pattern metallization processes.
Compared with prior art, double-pattern method of the present invention, in the double-pattern metallization processes of photoetching-etching-photoetching-etching, by optimizing and the process sequence of the hard mask layer of change traditional approach and increase the flatening process of hard mask layer, thereby increase second layer photoetching and etching technics window.Double-pattern method of the present invention is owing to be deposited hard mask layer and increased the flatening process of hard mask layer just after photoetching of ground floor figure and etching, the influence of having avoided the gap between the figure behind the traditional approach ground floor pattern etching that the evenness on hard mask layer surface is caused, make that photoresist is spun on the smooth plane when carrying out second layer photoetching process, so the second photoresist layer uniformity improves greatly, thereby increased the process window of second layer photoetching process.Further, double-pattern method of the present invention has avoided in the traditional approach because the too near process disturbance that causes of ground floor inter-pattern space and second layer litho pattern distance, thereby makes second layer photoetching morphology control ability and etching technics window all be improved.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the specific embodiment described in the specification.
Claims (10)
1. a double-pattern method is characterized in that, comprises the steps:
Deposition pattern layer and spin coating first photoresist layer on substrate successively from bottom to top;
Utilize described first photoresist layer of ground floor litho pattern version photoetching, and be the described graph layer of mask etching with described first photoresist layer after the photoetching;
Remove described first photoresist layer, in the inter-pattern space that the surface of described graph layer and described graph layer etching form, deposit hard mask layer;
Planarization is carried out on surface to described hard mask layer;
Flat surfaces at described hard mask layer deposits second photoresist layer;
Utilize described second photoresist layer of second layer litho pattern version photoetching and be described hard mask layer of mask etching and described graph layer with described second photoresist layer after the photoetching;
Remove described second photoresist layer and described hard mask layer.
2. double-pattern method as claimed in claim 1 is characterized in that, utilizes the mode of cmp that planarization is carried out on the surface of described hard mask layer.
3. double-pattern method as claimed in claim 1 is characterized in that, the material of described hard mask layer is silicon nitride or silicon oxynitride or tetraethyl-metasilicate or nitrogenize is smooth or titanium nitride.
4. double-pattern method as claimed in claim 1 is characterized in that, the thickness range of described hard mask layer is 100～1000 nanometers.
5. double-pattern method as claimed in claim 1 is characterized in that, described graph layer is the polysilicon lines-groove layer of semiconductor device or the through hole contact layer of semiconductor device.
6. double-pattern method as claimed in claim 1 is characterized in that, utilizes chemistry or physical vapour deposition (PVD) mode to form described hard mask layer.
7. double-pattern method as claimed in claim 1 is characterized in that, removes described hard mask layer with wet etching.
8. a double-pattern method is characterized in that, comprises the steps:
Deposition pattern layer and spin coating first photoresist layer on substrate successively from bottom to top;
Utilize described first photoresist layer of ground floor litho pattern version photoetching, and be the described graph layer of mask etching with described first photoresist layer after the photoetching;
Remove described first photoresist layer, in the inter-pattern space that the surface of described graph layer and described graph layer etching form, deposit hard mask layer;
Planarization is carried out on surface to described hard mask layer;
Flat surfaces at described hard mask layer deposits second photoresist layer;
Utilize described second photoresist layer of second layer litho pattern version photoetching, be the described hard mask layer of mask etching with described second photoresist layer after the photoetching;
Remove described second photoresist layer, with the described graph layer of described hard mask layer etching after the etching;
Remove described hard mask layer.
9. double-pattern method as claimed in claim 8 is characterized in that, the material of described hard mask layer is silicon nitride or silicon oxynitride or tetraethyl-metasilicate or nitrogenize is smooth or titanium nitride.
10. double-pattern method as claimed in claim 8 is characterized in that, the thickness range of described hard mask layer is 100～1000 nanometers.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102881564A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | MOM (metal oxide metal) capacitor manufacturing method |
| CN102881565A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | Method for forming metal-oxide-metal (MOM) capacitor |
| CN103048875A (en) * | 2012-12-27 | 2013-04-17 | 上海集成电路研发中心有限公司 | Photomask structure and manufacturing method thereof |
| CN103426810A (en) * | 2012-05-15 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Double patterning method in back-end-of-line |
| CN103904175A (en) * | 2014-04-18 | 2014-07-02 | 中国科学院半导体研究所 | Method for manufacturing photonic crystal light-emitting diode of waveguiding structures |
| CN105097442A (en) * | 2014-05-09 | 2015-11-25 | 力晶科技股份有限公司 | Semiconductor Manufacturing Process |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
| CN110161809A (en) * | 2019-05-27 | 2019-08-23 | 德淮半导体有限公司 | A kind of structure and its method for improving photoresist caking property |
| CN111725179A (en) * | 2020-06-24 | 2020-09-29 | 西安微电子技术研究所 | Wafer-level multilayer wiring structure and preparation method thereof |
| WO2022100055A1 (en) * | 2020-11-11 | 2022-05-19 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure and semiconductor structure |
| CN118281114A (en) * | 2024-04-02 | 2024-07-02 | 北京智创芯源科技有限公司 | Infrared detector manufacturing method and infrared detector |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426810A (en) * | 2012-05-15 | 2013-12-04 | 中芯国际集成电路制造(上海)有限公司 | Double patterning method in back-end-of-line |
| CN103426810B (en) * | 2012-05-15 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Double-patterning method in back-end process |
| CN102881565B (en) * | 2012-10-22 | 2018-05-29 | 上海集成电路研发中心有限公司 | A kind of forming method of metal-oxide-metal capacitor |
| CN102881565A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | Method for forming metal-oxide-metal (MOM) capacitor |
| CN102881564A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | MOM (metal oxide metal) capacitor manufacturing method |
| CN103048875A (en) * | 2012-12-27 | 2013-04-17 | 上海集成电路研发中心有限公司 | Photomask structure and manufacturing method thereof |
| CN103904175A (en) * | 2014-04-18 | 2014-07-02 | 中国科学院半导体研究所 | Method for manufacturing photonic crystal light-emitting diode of waveguiding structures |
| CN103904175B (en) * | 2014-04-18 | 2016-07-06 | 中国科学院半导体研究所 | There is the manufacture method of waveguiding structure photonic crystal light-emitting diode |
| CN105097442A (en) * | 2014-05-09 | 2015-11-25 | 力晶科技股份有限公司 | Semiconductor Manufacturing Process |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
| CN110161809A (en) * | 2019-05-27 | 2019-08-23 | 德淮半导体有限公司 | A kind of structure and its method for improving photoresist caking property |
| CN110161809B (en) * | 2019-05-27 | 2022-06-28 | 德淮半导体有限公司 | Structure and method for improving adhesiveness of photoresist |
| CN111725179A (en) * | 2020-06-24 | 2020-09-29 | 西安微电子技术研究所 | Wafer-level multilayer wiring structure and preparation method thereof |
| WO2022100055A1 (en) * | 2020-11-11 | 2022-05-19 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure and semiconductor structure |
| US11978637B2 (en) | 2020-11-11 | 2024-05-07 | Changxin Memory Technologies, Inc. | Manufacturing method for semiconductor structure and semiconductor structure |
| CN118281114A (en) * | 2024-04-02 | 2024-07-02 | 北京智创芯源科技有限公司 | Infrared detector manufacturing method and infrared detector |
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Application publication date: 20110720 |