CN102116979B - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
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- CN102116979B CN102116979B CN 200910248078 CN200910248078A CN102116979B CN 102116979 B CN102116979 B CN 102116979B CN 200910248078 CN200910248078 CN 200910248078 CN 200910248078 A CN200910248078 A CN 200910248078A CN 102116979 B CN102116979 B CN 102116979B
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Abstract
The invention provides a liquid crystal display device. The liquid crystal display device comprises a pixel array consisting of a plurality of sub-pixel arrays arranged in an array way; each sub-pixel array comprises a structure which contains two rows and two columns of pixels and consists of four pixel electrodes, four thin film transistors, a data line and four sequentially arranged scanning lines; the sources of the four thin film transistors share the data line; the drain of each thin film transistor is connected with a pixel electrode; the grids of the two thin film transistors of one column are connected with the two scanning lines in the middle respectively, and the grids of the two thin film transistors of the other column are connected with the other two scanning lines; and when the liquid crystal display device is driven, the four scanning lines are used for scanning sequentially. As the pixel electrodes having gray scale variation are arranged on the different columns, a vertical bar phenomenon due to non-uniform periodic gray scales can be avoided; and the aperture opening ratio can be guaranteed.
Description
Technical field
The present invention relates to liquid crystal indicator, relate in particular to the pel array of liquid crystal indicator.
Background technology
See also Fig. 1 to shown in Figure 3, prior art provides a kind of pel array of liquid crystal indicator, this pel array comprises a plurality of array of sub-pixels 1 of arranging with array way, each array of sub-pixels 1 comprises four pixel electrode 11A, 11B, 11C and 11D, four thin film transistor (TFT) 12A, 12B, 12C and 12D,, the structure of two row, two row that form of data line S11 and four sweep trace G11 to G14 sequentially arranging, in this structure, the drain electrode of each thin film transistor (TFT) is connected with a pixel electrode, the grid of the pixel electrode of every delegation by thin film transistor (TFT) connects respectively two sweep traces and forms dual scanning line structure (dual gate), concrete, pixel electrode 11A and 11B are respectively by thin film transistor (TFT) 12A, 12B is connected in sweep trace G11 and G12, pixel electrode 11C and 11D are respectively by thin film transistor (TFT) 12C, 12D is connected in sweep trace G14 and G13, the source electrode of four thin film transistor (TFT)s shares a data line, concrete, the pixel electrode 11A of first row is connected thin film transistor (TFT) 12A is connected source electrode and data line S11 and is connected and is positioned at the left side of data line S11 with 11D with 12D, secondary series pixel electrode 11B and 11C are by thin film transistor (TFT) 12B, 12C and data line S11 are connected and are positioned at the right side of data line S11.Fig. 1 only is schematic diagram, has expressed the pel array of 4 row, 6 row that are comprised of six array of sub-pixels 1, and in actual production technique, the pel array of liquid crystal indicator is comprised of a plurality of array of sub-pixels 1.
See also Fig. 1, Fig. 2 and Fig. 3, with Vcom (public electrode) direct current, " two dot inersion " (two 1 groups, reversal of poles) situation is example, the procedure for displaying of the pel array that above-mentioned array of sub-pixels 1 is formed is as follows: at first open sweep trace G11, the thin film transistor (TFT) that sweep trace G11 opens the first row first row, the 3rd row and the 5th row that are connected in sweep trace G11 charges to pixel electrode 11A, after charging is finished, the data of data line S11, S12 and S13 input pixel electrode 11A; Then, close sweep trace G11, sweep trace G12 opens thin film transistor (TFT) and to the first row secondary series, the pixel electrode 11B charging of the 4th row and the 6th row, in the process to pixel electrode 11B charging, between first row and the secondary series because data line S11 arranged, the distance of two row is done greatlyr, the impact of stray capacitance (not shown) is less, can ignore, and between secondary series and the 3rd row because there is not a data line, in order to improve aperture opening ratio, do the distance of two row less, stray capacitance 12 impacts are larger, therefore, the first row secondary series, the voltage of the pixel electrode 11B of the 4th row can affect the first row the 3rd row, voltage on the pixel electrode 11A of the 5th row is so that the voltage of pixel electrode 11A changes (such as reducing), thereby, the first row the 3rd row, the GTG of the pixel electrode 11A of the 5th row raises, after the pixel electrode 11B charging of the first row is finished, data line S 11, the data input pixel electrode 11B of S12 and S 13, then close sweep trace G12, open sweep trace G13, sweep trace G13 by thin film transistor (TFT) to the second row first row, the pixel electrode 11D charging of the 3rd row and the 5th row, the data input pixel electrode 11D of data line S11, then open sweep trace G14 to the secondary series of the second row, the pixel electrode 11C charging of the 4th row and the 6th row, same, at the secondary series to the second row, in the process of the pixel electrode 11C charging of the 4th row and the 6th row, secondary series, the pixel electrode 11C of the 4th row and the 6th row affects the voltage of the second row the 3rd row and the 5th pixel electrode 11D that is listed as so that the GTG rising of pixel electrode 11D by stray capacitance.
From the above analysis, the pixel electrode that gray scale variation occurs is pixel electrode 11A and the 3rd row of the second row and the pixel electrode 11D of the 5th row of the first row the 3rd row and the 5th row, and gray scale variation does not occur in the secondary series of the secondary series of the first row and the 4th row and the second row and the 4th row, by that analogy, in whole pel array, always the change in voltage of the pixel electrode on the odd column and so that GTG change, and GTG does not change on the even column, therefore, the pixel that gray scale variation occurs concentrates on one and lists, on macroscopic view, vertical bar can appear because the periodicity GTG is uneven in the display screen in liquid crystal indicator.
In addition, produce the phenomenon of vertical bar for the impact that reduces stray capacitance, at present, can strengthen the distance between the adjacent two row pixels, to reduce the impact of stray capacitance, still, like this, can reduce aperture opening ratio.
Summary of the invention
The technical matters that the present invention solves is that the periodicity GTG inequality of liquid crystal indicator causes the vertical bar phenomenon and strengthens the distance between the two row pixels and affect the problem of aperture opening ratio.
For addressing the above problem, the invention provides a kind of liquid crystal indicator, comprise the pel array that is consisted of by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels that form of data line and four sweep traces sequentially arranging, the source electrode of described four thin film transistor (TFT)s shares described data line, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan successively described four sweep traces.
Alternatively, described each sub-pixel array structure is identical.
Alternatively, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the odd column of whole pel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of whole pel array.
Alternatively, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the even column of whole pel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the odd column of whole pel array.
Alternatively, in the described pel array, in adjacent four array of sub-pixels that are arranged in delegation, the structure of each array of sub-pixels is incomplete same.
Alternatively, in the described pel array, in adjacent four array of sub-pixels that are arranged in matrix pattern, the structure of each array of sub-pixels is incomplete same.
Alternatively, there are three sub-pixel array structure identical in described four array of sub-pixels.
Alternatively, there is the structure of two array of sub-pixels identical in described four array of sub-pixels.
Compared with prior art, the present invention is because in the two row thin film transistor (TFT)s that are connected with data line, wherein a row thin film transistor (TFT) is connected with two sweep traces of centre respectively, the thin film transistor (TFT) of other row is connected with the two other sweep trace, and when described liquid crystal indicator drives, scan successively described four sweep traces.Therefore, in an array of sub-pixels, the voltage of the pixel electrode of another array of sub-pixels that impact row is adjacent in two pixel electrodes of same row and gray scale variation occurs, the pixel voltage of another pixel electrode then be subject to another adjacent array of sub-pixels of its row pixel electrode impact and gray scale variation occurs, therefore, in whole pel array, the pixel electrode that gray scale variation occurs is dispersed to different listing, and unlike prior art, always concentrating on one lists, therefore, the vertical bar phenomenon that the present invention has avoided periodicity GTG inequality to cause by grid and the connected mode between the sweep trace of the thin film transistor (TFT) of adjustment pixel electrode, and the distance that need not increase between the two adjacent pixels just can achieve the goal, the aperture opening ratio that has guaranteed.
Description of drawings
Fig. 1 is the structural representation of the pel array of existing liquid crystal indicator;
Fig. 2 is the schematic diagram during the N two field picture among Fig. 1;
Fig. 3 is the schematic diagram during the N+1 two field picture among Fig. 1;
Fig. 4 is the structural representation of pel array first embodiment of liquid crystal indicator of the present invention;
Fig. 5 is the structural representation of pel array second embodiment of liquid crystal indicator of the present invention;
Fig. 6 is the structural representation of pel array the 3rd embodiment of invention liquid crystal indicator of the present invention;
Fig. 7 is the structural representation of pel array the 4th embodiment of liquid crystal indicator of the present invention;
Fig. 8 is the structural representation of pel array the 5th embodiment of liquid crystal indicator of the present invention;
Fig. 9 is the structural representation of pel array the 6th embodiment of liquid crystal indicator of the present invention;
Figure 10 is the structural representation of pel array the 7th embodiment of liquid crystal indicator of the present invention;
Figure 11 is the structural representation of pel array the 8th embodiment of liquid crystal indicator of the present invention.
Embodiment
The present inventor finds because of the impact of stray capacitance so that the pixel electrode of generation gray scale variation is present in same listing and causes the vertical bar phenomenon in the process of making liquid crystal indicator.
The present inventor finds through performing creative labour, the connected mode of adjusting between grid and the sweep trace of thin film transistor (TFT) of each pixel electrode is distributed in different row so that the pixel electrode of gray scale variation occurs, thereby, the vertical bar phenomenon of having avoided the pixel electrode of gray scale variation to concentrate on row and having caused, and, need not increase the distance of two adjacent columns pixels, guarantee aperture opening ratio.
For above-mentioned purpose of the present invention, feature ﹠ benefits can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
See also Fig. 4, Fig. 4 represents the first embodiment of this invention, and in this embodiment, the pel array of liquid crystal indicator comprises a plurality of the first array of sub-pixels 2 of arranging with array way, and the structure of each the first array of sub-pixels 2 is identical.Take one of them first array of sub-pixels 2 as example, this first array of sub-pixels 2 comprises four pixel electrode 21A, 21B, 21C and 21D, four thin film transistor (TFT) 22A, 22B, 22C and 22D,, a data line S21 and sequentially four sweep trace G21 of arrangement, G22, the structure of two row, two row that G23 and G24 form, in this structure, the pixel electrode of every delegation forms dual scanning line structure (dual gate) by two sweep traces of grid connection of thin film transistor (TFT) respectively, concrete, the pixel electrode 21A of the first row and 21B are respectively by thin film transistor (TFT) 22A, 22B is connected in sweep trace G21 and G22, and the pixel electrode 21C of the second row and 21D are respectively by thin film transistor (TFT) 22C, 22D is connected in sweep trace G23 and G24; The source electrode of two row thin film transistor (TFT)s shares a data line, concrete, the thin film transistor (TFT) 22A of first row is connected source electrode and data line S21 and is connected and is positioned at the left side of data line S21 with 22D, secondary series thin film transistor (TFT) 22B is connected source electrode and data line S21 and is connected and is positioned at the right side of data line S21 with 22C.In the two row thin film transistor (TFT)s that are connected with data line S21, wherein a row thin film transistor (TFT) 22B is connected with G23 with two sweep trace G22 of centre respectively with 22C, the thin film transistor (TFT) 22A of other row, 22D is connected with G24 with two other sweep trace G21, by that analogy to whole pel array, be connected with four sweep traces that are arranged in order respectively at four thin film transistor (TFT)s of arbitrary neighborhood two row that are connected with data line, wherein the grid of a row thin film transistor (TFT) is connected with two sweep traces in the middle of being positioned in these four sweep traces respectively, and the grid of the thin film transistor (TFT) of other row is connected with the two other sweep trace.Fig. 4 has shown 4 row, the 6 row picture element array structures that are comprised of 6 the first array of sub-pixels 2, in this structure, have three data line S21, S22 and S23, eight sweep trace G21, G22, G23, G24, G25, G26, G27 and G28 and some pixel electrode and thin film transistor (TFT)s that is positioned at sweep trace and data line intersection.Shown in 4 row, 6 row picture element array structures in, what the thin film transistor (TFT) that is connected with two sweep traces of centre was positioned at this structure is secondary series, the 4th row and the 6th row, the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at first row, the 3rd row and the 5th row of this structure, by that analogy to whole pel array, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the even column of whole pel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is in the odd column of whole pel array.
Please continue to consult Fig. 4, the procedure for displaying of this embodiment is as follows, at first, to sweep trace G21 input scan signal so that sweep trace G21 open.After sweep trace G21 opened, the pixel electrode 21A of the first row of the first row, the 3rd row and the 5th row was recharged; Then, close sweep trace G21, the thin film transistor (TFT) 22A that is connected with pixel electrode 21A turn-offs, pixel electrode 21A enters the voltage hold mode, open sweep trace G22, the secondary series of the first row, the pixel electrode 21B of the 4th row and the 6th row is recharged, because the pixel electrode 21A of adjacent two row, exist between the 21B stray capacitance (such as, there is stray capacitance between the pixel electrode 21B of secondary series and the tertial pixel electrode 21A), below just as an example of the first row secondary series and tertial pixel electrode 21B and 21A and the second row secondary series and tertial pixel electrode 21C and 21D example the present embodiment is described, in the process that the pixel electrode 21B of the first row secondary series is recharged, voltage on the pixel electrode 21B of the first row secondary series by stray capacitance so that the voltage of the tertial pixel electrode 21A of the first row change, such as, voltage decreases on the tertial pixel electrode 21A of the first row, for the normal white mode of twisted nematic, the GTG of the tertial pixel electrode 21A of this first row raises; Follow again, close sweep trace G22, open sweep trace G23, the pixel electrode 21C of the second row secondary series that is connected with sweep trace G23 is recharged (certainly, at this moment, the 4th row of the second row and the pixel electrode 21C of the 6th row also can be recharged), after turn-offing sweep trace G23, the pixel electrode 21C of the second row secondary series enters the voltage hold mode, then, open sweep trace G24, the pixel electrode 21D that is connected with sweep trace G24 is recharged (certainly, at this moment, the pixel electrode 21D of the second row the 3rd row and the 5th row also can be recharged), the tertial pixel electrode 21D of the second row is in the process of charging, equally, owing to having stray capacitance, the voltage on the pixel electrode 21C of voltage influence the second row secondary series of the tertial pixel electrode 21D of the second row, thereby the GTG of pixel electrode 21C uprises.
To sum up, the tertial pixel electrode of the first row that gray scale variation occurs for the first time is 21A, the pixel electrode that the second row secondary series of gray scale variation occurs for the second time is 21C, pixel electrode 21A and pixel electrode 21C do not list same, by that analogy to whole pel array, the pixel electrode of gray scale variation occurs just not at same row, compare in the situation of same row with the pixel electrode that gray scale variation occurs in the prior art, this implementation column has avoided periodicity GTG inequality to cause the situation of vertical bar, but also need not increase distance (secondary series and the 3rd row between) between adjacent two row, guaranteed aperture opening ratio.
See also Fig. 5, Fig. 5 is the second embodiment of the present invention, and among this embodiment, the pel array of described liquid crystal indicator also comprises a plurality of the second array of sub-pixels 3 of arranging with array way, and the structure of each the second array of sub-pixels 3 is identical.Take one of them second array of sub-pixels 3 as example, the second array of sub-pixels 3 comprises four pixel electrode 31A, 31B, 31C and 31D, four thin film transistor (TFT) 32A, 32B, 32C and 32D,, a data line S31 and sequentially four sweep trace G31 of arrangement, G32, the structure of two row, two row that G33 and G34 form, in this structure, the pixel electrode of every delegation forms dual scanning line structure (dual gate) by two sweep traces of grid connection of thin film transistor (TFT) respectively, concrete, the pixel electrode 31A of the first row and 31B are respectively by thin film transistor (TFT) 32A, 32B is connected in sweep trace G32 and G31, and the pixel electrode 31C of the second row and 31D are respectively by thin film transistor (TFT) 32C, 32D is connected in sweep trace G34 and G33; The source electrode of two row thin film transistor (TFT)s shares a data line, concrete, the thin film transistor (TFT) 32A of first row is connected source electrode and data line S31 and is connected and is positioned at the left side of data line S31 with 32D, secondary series thin film transistor (TFT) 32B is connected source electrode and data line S31 and is connected and is positioned at the right side of data line S31 with 32C.In the two row thin film transistor (TFT)s that are connected with data line S31, wherein the grid of a row thin film transistor (TFT) 32A, 32D is connected with G33 with sweep trace G32, and the grid of an other row thin film transistor (TFT) 32B, 32C is connected with G34 with two other sweep trace G31.By that analogy to whole pixel permutation, by that analogy to whole pel array, be connected with four sweep traces that are arranged in order respectively at four thin film transistor (TFT)s of arbitrary neighborhood two row that are connected with data line, wherein the grid of a row thin film transistor (TFT) is connected with two sweep traces in the middle of being positioned in these four sweep traces respectively, and the grid of the thin film transistor (TFT) of other row is connected with the two other sweep trace.Fig. 5 has shown the structure of 4 row, 6 row that are comprised of 6 the second array of sub-pixels 3, in this structure, have three data line S31, S32 and S33, eight sweep trace G31, G32, G33, G34, G35, G36, G37 and G38 and some pixel electrode and thin film transistor (TFT)s that is positioned at sweep trace and data line intersection.Shown in the pel array of 4 row 6 row in, what the thin film transistor (TFT) that is connected with two sweep traces of centre was positioned at this structure is first row, the 3rd row and the 5th row, the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at secondary series, the 4th row and the 6th row of this structure, by that analogy to whole pel array, the thin film transistor (TFT) that two middle sweep traces connect is positioned at the odd column of whole pel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of whole pel array.
Please continue to consult Fig. 5, because among this embodiment, the course of work of sweep trace and data line is identical, therefore, does not repeat them here.The below is that example is described to affected pixel electrode only, in this embodiment, the tertial pixel electrode 31A of the first row affect the first row secondary series pixel electrode 31B and so that the GTG of pixel electrode 31B change, the pixel electrode 31C of the second row secondary series affect the tertial pixel electrode 31D of the second row and so that the GTG of pixel electrode 31D change, in this embodiment, the pixel 31B that GTG changes and 32D do not list same, by that analogy to the pel array of whole liquid crystal indicator, the pixel electrode of gray scale variation occurs just not at same row, thereby, the vertical bar phenomenon of having avoided the pixel electrode of grey scale transformation to concentrate on row and having caused, and, need not increase the distance between the two adjacent columns pixels, guarantee aperture opening ratio.
In Fig. 4 and the pel array shown in Figure 5, the structure of each array of sub-pixels is identical, and certainly, the structure of each array of sub-pixels in the pel array can be not identical yet, the below is take Fig. 6 to Figure 10 as example, and the structure of the different pel array of sub-pixel array structure is described as follows:
See also Fig. 6, Fig. 6 is the third embodiment of the present invention, in this embodiment, line up matrix pattern in adjacent four array of sub-pixels, in these four pel arrays, there is the structure of three array of sub-pixels identical, concrete, comprise three the second array of sub-pixels 3 and first array of sub-pixels 2, described the first array of sub-pixels 2 is positioned at the lower right corner of matrix pattern, in this embodiment, all is at sweep trace G41, G42, G43, G44, G45, G46, G47 be connected with G48 obtain to open after the corresponding sweep signal be connected with pixel electrode thin film transistor (TFT), then corresponding data-signal does not repeat them here the input of signal by data line S41 and S42 input.In Fig. 6, the thin film transistor (TFT) of the first row secondary series and tertial pixel electrode is scanned line G41 and opens simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned simultaneously line G44 and opens, therefore, stray capacitance can not affect the GTG of pixel electrode, the sweep signal of obtaining G45 when the thin film transistor (TFT) of the pixel electrode 41B of the third line secondary series is opened and when entering the voltage hold mode, when sweep trace G46 charges to the tertial pixel electrode 41A of the third line, this pixel electrode 41A can affect the third line secondary series pixel electrode 41B so that the GTG of pixel electrode 41B change, same reason, obtain the signal of sweep trace G47 and when entering the voltage hold mode at the thin film transistor (TFT) of the tertial pixel electrode 41D of fourth line, the pixel electrode 41C of fourth line secondary series can affect the tertial pixel electrode 41D of fourth line voltage and so that the GTG of pixel electrode 41D change, in this embodiment, the pixel electrode 41B of generation gray scale variation and 41D be not at same row, be pushed into whole pel array with this reason class, the pixel electrode that gray scale variation occurs does not list same, therefore, the pixel electrode array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 7, Fig. 7 is the fourth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are arranged in matrix pattern, in these four array of sub-pixels, there is the structure of two array of sub-pixels identical, concrete, comprise two the second array of sub-pixels 3 and two the first array of sub-pixels 2, two the second array of sub-pixels 3 form a line, two the first array of sub-pixels 2 form a line, in this embodiment, when sweep trace was scanned line by line, the first row secondary series and the 3rd row were scanned simultaneously line G51 and open, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned simultaneously line G54 and opens, the thin film transistor (TFT) of the third line secondary series and tertial pixel electrode is scanned simultaneously line G55 and opens, the thin film transistor (TFT) of fourth line secondary series and tertial pixel electrode is scanned simultaneously line G58 and opens, and therefore, stray capacitance can not affect the GTG of pixel electrode, therefore, the pixel electrode array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 8, Fig. 8 is the fifth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are lined up in the matrix pattern, in these four array of sub-pixels, the structure of two array of sub-pixels that are in the crossed position is identical, concrete, comprise two the second array of sub-pixels 3 and two the first array of sub-pixels 2, two array of sub-pixels 2 are positioned on the diagonal line, two array of sub-pixels 3 are positioned on the diagonal line, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned simultaneously line G62 and open, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned simultaneously line G63 and opens, the thin film transistor (TFT) of the third line secondary series and tertial pixel electrode is scanned simultaneously line G65 and opens, the thin film transistor (TFT) of fourth line secondary series and tertial pixel electrode is scanned simultaneously line G68 and opens, therefore, stray capacitance can not affect the GTG of pixel electrode, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 9, Fig. 9 is the sixth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are lined up matrix pattern, in these four array of sub-pixels, there is the structure of three array of sub-pixels identical, concrete, comprise three the first array of sub-pixels 2 and second array of sub-pixels 3, the second array of sub-pixels 3 is positioned at the lower left corner of matrix pattern, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned line G71 and open simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned simultaneously line G74 and opens, therefore, stray capacitance can not affect the GTG of pixel electrode, the sweep signal of obtaining G76 when the thin film transistor (TFT) of the pixel electrode 71B of the third line secondary series is opened and when entering the voltage hold mode, sweep trace G76 is to the pixel electrode 71B of the third line secondary series charging the time, this pixel electrode 71B can affect the tertial pixel electrode 71A of the third line so that the GTG of pixel electrode 71A changes, same reason, obtain the signal of sweep trace G77 and when entering the voltage hold mode at the thin film transistor (TFT) of the pixel electrode 71C of fourth line secondary series, the tertial pixel electrode 71D of fourth line can affect the fourth line secondary series pixel electrode 71C voltage and so that the GTG of pixel electrode 71C change, in this embodiment, the pixel electrode 71A of generation gray scale variation and 71C be not at same row, be pushed into whole pel array with this reason class, the pixel electrode that gray scale variation occurs does not list same, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Figure 10, Figure 10 is the seventh embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are arranged in matrix pattern, in these four array of sub-pixels, there is the structure of three array of sub-pixels identical, concrete, comprise three the first array of sub-pixels 2 and second array of sub-pixels 3, described the second array of sub-pixels 3 is positioned at the lower right corner of matrix pattern, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned line G82 and open simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned simultaneously line G83 and opens, therefore, stray capacitance can not affect the GTG of pixel electrode, when sweep signal that the thin film transistor (TFT) of the tertial pixel electrode 81A of the third line is obtaining sweep trace G85 is opened so that when pixel electrode 81A enters the voltage hold mode, sweep trace G86 is to the pixel electrode 81B of the third line secondary series charging the time, this pixel electrode 81B can affect the tertial pixel electrode 81A of the third line so that the GTG of pixel electrode 81A changes, same reason, obtain the signal of sweep trace G87 and when entering the voltage hold mode at the thin film transistor (TFT) of the pixel electrode 81C of fourth line secondary series, the tertial pixel electrode 81D of fourth line can affect the fourth line secondary series pixel electrode 81C voltage and so that the GTG of pixel electrode 81C change, in this embodiment, the pixel electrode 81A of generation gray scale variation and 81C be not at same row, be pushed into whole pel array with this reason class, the pixel electrode that gray scale variation occurs does not list same, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
Above-mentioned the 3rd embodiment to the seven embodiment are all in adjacent four array of sub-pixels that are arranged in matrix pattern, the situation that the structure of each array of sub-pixels is incomplete same, but, predictably, when four array of sub-pixels are arranged in delegation or row, described liquid crystal indicator the phenomenon that the GTG inequality causes vertical bar can not occur equally
See also Figure 11, Figure 11 is the eighth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are in line, in this embodiment, comprise three the second array of sub-pixels 3 and first array of sub-pixels 2, described three the second array of sub-pixels 3 are adjacent, in this embodiment, described four pel arrays are lined up the structure of two row, eight row, in this structure, the pixel electrode 91B1 of the first row secondary series and tertial pixel electrode 91A are scanned line G92 and charge simultaneously, therefore, the phenomenon that the GTG inequality can not occur, equally, the pixel electrode 91C1 of the second row secondary series and tertial pixel electrode 91D are scanned line G93 and charge simultaneously, the phenomenon of GTG inequality also can not occur; The pixel electrode 91B of the first row the 4th row is by the pixel electrode 91A impact of the first row the 5th row and GTG changes, the pixel electrode 91D of the second row the 5th row is by the pixel electrode 91C impact of the second row the 4th row and GTG changes, thereby, pixel electrode 91D and 91B that gray scale variation occurs do not list same, thereby, can avoid the phenomenon of GTG inequality, same reason, the 91D of the 91B of the first row the 6th row of generation gray scale variation and the second row the 7th row is not at same row, therefore, in the situation that adjacent four array of sub-pixels are in line, the vertical bar phenomenon can not appear yet.By that analogy, described three the second array of sub-pixels 3 and the first array of sub-pixels 2 are arranged in a row according to other modes, also can avoid occurring the phenomenon of vertical bar.
Although the present invention with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (5)
1. liquid crystal indicator, comprise the pel array that is consisted of by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels that form of data line and four sweep traces sequentially arranging, the source electrode of described four thin film transistor (TFT)s shares described data line, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, it is characterized in that, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan successively described four sweep traces;
Described each sub-pixel array structure is identical;
Wherein, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the odd column of whole pel array, the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of whole pel array, the thin film transistor (TFT) that perhaps is connected with two sweep traces of centre is positioned at the even column of whole pel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the odd column of whole pel array.
2. liquid crystal indicator, comprise the pel array that is consisted of by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels that form of data line and four sweep traces sequentially arranging, the source electrode of described four thin film transistor (TFT)s shares described data line, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, it is characterized in that, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan successively described four sweep traces; In the described pel array, in adjacent four array of sub-pixels that are arranged in delegation, the structure of each array of sub-pixels is incomplete same.
3. liquid crystal indicator, comprise the pel array that is consisted of by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels that form of data line and four sweep traces sequentially arranging, the source electrode of described four thin film transistor (TFT)s shares described data line, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, it is characterized in that, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan successively described four sweep traces; In the described pel array, in adjacent four array of sub-pixels that are arranged in matrix pattern, the structure of each array of sub-pixels is incomplete same.
4. liquid crystal indicator as claimed in claim 3 is characterized in that, has three sub-pixel array structure identical in described four array of sub-pixels.
5. liquid crystal indicator as claimed in claim 3 is characterized in that, has the structure of two array of sub-pixels identical in described four array of sub-pixels.
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| CN102269903A (en) * | 2011-07-19 | 2011-12-07 | 南京中电熊猫液晶显示科技有限公司 | Pixel driving framework |
| CN103207489A (en) * | 2013-03-27 | 2013-07-17 | 京东方科技集团股份有限公司 | Pixel structure, driving method thereof and display device |
| CN104808406B (en) * | 2015-05-07 | 2017-12-08 | 深圳市华星光电技术有限公司 | A kind of substrate and its liquid crystal display device |
| CN105304640B (en) * | 2015-09-22 | 2018-07-06 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN107065354A (en) * | 2017-05-08 | 2017-08-18 | 深圳市华星光电技术有限公司 | A kind of liquid crystal display panel and device |
| CN107134464A (en) * | 2017-07-03 | 2017-09-05 | 京东方科技集团股份有限公司 | A kind of array base palte, its driving method and display device |
| CN107741660B (en) * | 2017-11-30 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving framework, display panel and display device |
| TWI696021B (en) * | 2018-11-16 | 2020-06-11 | 友達光電股份有限公司 | Display device |
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Effective date of registration: 20201211 Address after: 5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Haiyun Communication Co.,Ltd. Address before: 201201, 889, Qing Qing Road, Shanghai, Pudong New Area Patentee before: SHANGHAI TIANMA MICRO-ELECTRONICS Co.,Ltd. Effective date of registration: 20201211 Address after: Room a-430, 4 / F, block a, phase II, Guangxi Huike Technology Co., Ltd., No. 336, Beihai Avenue East extension line, Beihai Industrial Park, Guangxi Zhuang Autonomous Region Patentee after: BEIHAI HKC PHOTOELECTRIC TECHNOLOGY Co.,Ltd. Address before: 5-6 / F, building D, huilongda Industrial Park, Shuitian Private Industrial Park, Shiyan street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Haiyun Communication Co.,Ltd. |