CN102116785A - Device and method for analyzing static transient voltage drop - Google Patents

Abstract

A static transient voltage drop analysis device is applied to a multi-threshold complementary metal oxide semiconductor transistor. The static transient voltage drop analysis device includes an estimation module, a processing module and a measurement module. The estimation module estimates a transient voltage drop tolerance value according to the transient voltage drop characteristic of the multi-threshold complementary metal oxide semiconductor transistor. The processing module selects a corresponding dummy metal layer from multiple candidate dummy metal layers according to the transient voltage drop tolerance value, and adds the dummy metal layer into the multi-threshold CMOS transistor. The measurement module measures a transient voltage drop of the dummy metal layer added to the multi-threshold CMOS transistor. The measured transient voltage drop is substantially the static transient voltage drop of the multi-threshold CMOS transistor.

Description

Static transient voltage drop analysis device and method

【Technical field】

The present invention is related to power gating technology, in particular, about a multi-threshold complementary metal-oxide semiconductor (Multi-Threshold Complementary Metal-Oxide Semiconductor) in a power gating circuit without using expensive special analysis tools. -Semiconductor, MTCMOS) transistor static transient voltage drop (static IR drop) measurement device and static transient voltage drop analysis method.

【Background technique】

As ASIC (Application Specific Integrated Circuit, ASIC) and System on Chip (SoC) gradually adopt the IC process below 0.13 micron, in order to be able to produce smaller and faster IC, wafer generation Factories began to adopt new materials and process technologies, such as smaller process scale, adjustable threshold (scaled threshold) and unscaled voltage (unscaled voltage), etc., but it also produced more and more serious leakage current (leakage current) and static power consumption (static power consumption) and other issues.

Especially for IC processes below 90nm and below 65nm, power management has become a very important consideration for IC designers. In order to effectively respond to the issue of power management, IC designers use various techniques to reduce the static power consumption of their designed circuits, such as multi-threshold (multi-threshold) design, multi-voltage (multi-voltage) design, clock grid Control (clock gating) and power gate control (power gating), etc.

Wherein, in the power gate control circuit of the mobile communication device, a multi-threshold complementary metal oxide semiconductor (MTCMOS) transistor composed of a PMOS device or an NMOS device is often arranged. The multi-threshold complementary metal oxide semiconductor transistor achieves the effect of power gate control by separating the equal power supply voltage (constant VDD) and the switched power supply voltage (switchedVDD), so as to turn off the modules that will not be used temporarily in the mobile communication device. Its static power consumption can be greatly reduced.

Please refer to FIG. 1A and FIG. 1B . FIG. 1A and FIG. 1B are respectively schematic diagrams of two different general power gate control circuits. As shown in FIG. 1A and FIG. 1B, the power gate control circuit 1 includes a PMOS device 10 and the power gate control circuit 11' includes PMOS devices 11 and 12, and respectively have constant VDD and switched VDD.

Please also refer to FIG. 2A and FIG. 2B. FIG. 2A and FIG. 2B respectively depict a schematic circuit layout of a general power gate control circuit and a cross-sectional view of a multi-threshold complementary metal oxide semiconductor transistor 20 obtained along the dotted line L in FIG. 2A. , is shown by taking the structure of the PMOS switch VDD as an example, as shown in FIG. 2A and FIG. 2B . However, it can be clearly seen from FIG. 2B that since the multi-threshold complementary metal oxide semiconductor transistor 20 achieves the power gate control effect by separating the equal power supply voltage (constant VDD) and the switched power supply voltage (switched VDD), that is to say , there is no coupling relationship between the constant VDD and the switched VDD, which makes it difficult to measure the static transient voltage drop of the multi-threshold complementary metal oxide semiconductor transistor 20 .

Although the current Electronic Design Automation (EDA) software can also analyze the static transient voltage drop of multi-threshold complementary metal oxide semiconductor transistors through some specially designed analysis software, the cost of its purchase is very considerable, even A spectrum that can reach several million Taiwan dollars is a very heavy burden for both IC designers and IC manufacturers.

Therefore, the main scope of the present invention is to provide a static transient voltage drop analysis device and a static transient voltage drop analysis method to solve the above problems.

【Content of invention】

The first specific embodiment according to the present invention is a static transient voltage drop analysis device. In this embodiment, the static transient voltage drop analysis device is applied to a multi-threshold CMOS transistor. The static transient voltage drop analysis device includes an estimation module, a processing module and a measurement module. The estimating module is used for estimating a transient voltage drop tolerance value according to the transient voltage drop characteristic of the multi-threshold complementary metal oxide semiconductor transistor. The processing module is used for selecting a corresponding dummy metal layer from multiple candidate dummy metal layers according to the transient voltage drop tolerance value, and adding the dummy metal layer into the multi-threshold CMOS transistor. The measurement module is used for measuring a transient voltage drop of the dummy metal layer added to the multi-threshold complementary metal oxide semiconductor transistor. Wherein, the transient voltage drop measured by the measurement module is substantially the static transient voltage drop of the multi-threshold CMOS transistor.

The second specific embodiment according to the present invention is a static transient voltage drop analysis method. In this embodiment, the static transient voltage drop analysis method is applied to a multi-threshold CMOS transistor. First, the method estimates a transient voltage drop tolerance value according to the transient voltage drop characteristic of the multi-threshold complementary metal oxide semiconductor transistor; then, the method selects a plurality of candidate simulation metal layers according to the transient voltage drop tolerance value Selecting a corresponding simulated metal layer; then, the method adds the simulated metal layer to the multi-threshold complementary metal oxide semiconductor transistor; afterward, the method measures the simulated metal layer added to the multi-threshold complementary metal oxide semiconductor transistor This simulates a transient voltage drop across the metal layer. Wherein, the measured transient voltage drop is substantially the static transient voltage drop of the multi-threshold CMOS transistor.

Compared with the prior art, according to the static transient voltage drop analysis device and the static transient voltage drop analysis method of the present invention, a transient voltage of the multi-threshold complementary metal oxide semiconductor transistor to be tested is first estimated by a common SPICE simulation program After reducing the tolerance value, a dummy metal layer corresponding to the transient voltage drop tolerance value is added to the multi-threshold complementary metal oxide semiconductor transistor, so that the originally separated equal power supply voltage (constant VDD) and switching power supply voltage ( switched VDD) are coupled together through the simulated metal layer to form a short circuit, and then accurately measure the static transient voltage drop of the multi-threshold complementary metal oxide semiconductor transistor through the simulated metal layer.

Therefore, the static transient voltage drop analysis device and the static transient voltage drop analysis method proposed by the present invention can accurately measure the static transient voltage of the multi-threshold complementary metal oxide semiconductor transistor only by using general EDA software Therefore, it is possible to avoid the extra huge cost required to purchase some specially designed analysis software in the prior art.

The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

【Description of drawings】

FIG. 1A and FIG. 1B respectively illustrate schematic diagrams of two different general power gate control circuits.

2A and 2B respectively illustrate a schematic circuit layout of a general power gate control circuit and a cross-sectional view of a multi-threshold complementary metal-oxide-semiconductor transistor along the dotted line L in FIG. 2A .

FIG. 3 is a functional block diagram of a static transient voltage drop analysis device according to a first embodiment of the present invention.

FIG. 4 shows an I _DS -V _DS characteristic curve of a multi-threshold complementary metal-oxide-semiconductor transistor simulated by a SPICE simulation program.

FIG. 5A and FIG. 5B respectively show the top views of the multi-threshold complementary metal oxide semiconductor transistor without adding the dummy metal layer and the multi-threshold complementary metal oxide semiconductor transistor with the dummy metal layer added.

6A and 6B are cross-sectional views of a multi-threshold complementary metal oxide semiconductor transistor without adding a dummy metal layer and a multi-threshold complementary metal oxide semiconductor transistor with a dummy metal layer, respectively.

FIG. 7A and FIG. 7B respectively show the program code of the netlist before changing the power source coupled to the power pin and the program code of the netlist after changing the power source coupled to the power pin.

FIG. 8 is a schematic diagram of current flowing from the power pad to the multi-threshold CMOS transistor.

FIG. 9 is a flowchart of a static transient voltage drop analysis method according to a second embodiment of the present invention.

[Description of main component symbols]

S10～S14: process steps

1, 1', 2, 6: power grid control circuit

10～12, 20: multi-threshold complementary metal oxide semiconductor transistor

3: Static transient voltage drop analysis device 30: Estimation module

32: Processing module 34: Change module

36: Measurement module D: Sink

S: Source G: Gate

L: Section line M: Metal layer

P: power pad std cell: standard electronic component

5': Multi-threshold complementary metal oxide semiconductor transistor with metal layer added

【Detailed ways】

The first specific embodiment according to the present invention is a static transient voltage drop analysis device. In this embodiment, in this embodiment, the static transient voltage drop analysis device is used to analyze the static transient voltage drop of a multi-threshold complementary metal oxide semiconductor transistor disposed in a power gate control circuit, and the The power gate control circuit can be arranged in a mobile communication device or other electronic devices, and is used to turn off modules whose functions will not be used temporarily in the mobile communication device or other electronic devices, such as communication modules, short message modules or game modules, In order to reduce its overall total power consumption, but not limited thereto.

Please refer to FIG. 3 , which is a functional block diagram of the static transient voltage drop analysis device. As shown in FIG. 3 , the static transient voltage drop analysis device 3 includes an estimation module 30 , a processing module 32 , a modification module 34 and a measurement module 36 . Wherein, the estimation module 30 is coupled to the processing module 32 ; the processing module 32 is coupled to the modification module 34 ; the modification module 34 is coupled to the measurement module 36 . Next, each module and its function of the static transient voltage drop analysis device 3 will be introduced respectively.

In this embodiment, the estimation module 30 is used for estimating a transient voltage drop tolerance value according to the transient voltage drop characteristic of the multi-threshold complementary metal oxide semiconductor transistor. In fact, the estimation module 30 can execute a general SPICE simulation program or other simulation programs to simulate the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor, and thereby estimate the corresponding multi-threshold complementary metal oxide semiconductor transistor. The transient voltage drop tolerance value of the transistor, but not limited thereto.

Next, the processing module 32 is used for selecting a corresponding simulated metal layer from a plurality of candidate simulated metal layers according to the transient voltage drop tolerance value. In practical applications, the multiple candidate dummy metal layers and their corresponding transient voltage drop tolerance values can be pre-recorded in a lookup table, and the respective sizes and resistance values of the multiple candidate dummy metal layers are recorded, But not limited to this.

For example, the estimation module 30 can execute a general SPICE simulation program to obtain the I _DS -V _DS characteristic curve of the multi-threshold complementary metal oxide semiconductor transistor, as shown in FIG. 4 . According to V=IR, when the gate voltage V _G is fixed, the resistance value R=V _DS /I _DS , which is the reciprocal of the slope of the dotted line in FIG. 4 . Assuming that the transient voltage drop tolerance value ΔV of the multi-threshold complementary metal oxide semiconductor transistor obtained by the estimation module 30 is 3%, the method can further select the corresponding transient voltage drop from the numerous candidate simulation metal layers recorded in the lookup table. The simulated metal layer M has a state voltage drop tolerance value of 3%, and the simulated metal layer M has a width of 0.06 microns and a resistance value of 0.067 ohms according to the information recorded in the following look-up table.

Chart

Transient voltage drop tolerance value Type of simulated metal layer Simulated metal layer width Simulation metal layer resistance 1% N 0.02 microns 0.027 ohms 3% m 0.06 micron 0.067 ohms 5% N 0.09 microns 0.101 ohms 7% m 0.11 microns 0.122 ohms

Next, the processing module 32 further adds the dummy metal layer to the multi-threshold CMOS transistor. Please refer to FIG. 5A and FIG. 5B. FIG. 5A and FIG. 5B respectively show a multi-threshold complementary metal oxide semiconductor transistor 5 that has not yet been added to the dummy metal layer M and a multi-threshold complementary metal oxide semiconductor transistor 5' that has been added to the dummy metal layer M. top view of .

As shown in Figure 5A, the multi-threshold complementary metal oxide semiconductor transistor 5 includes a switched power supply voltage (switched VDD), an equal power supply voltage (constant VDD), and a common connection ground voltage (VSS), wherein the switched power supply voltage and the equal power supply voltage are not connected to each other. In normal mode, only the equal power supply voltage is connected to the system voltage source, and the part to be measured is the static transient voltage drop between the equal power supply voltage and the switching power supply voltage.

As shown in FIG. 5B , the processing module 32 couples the dummy metal layer M between the equal power supply voltage and the switching power supply voltage, so that the equal power supply voltage and the switching power supply voltage that are originally separated from each other in FIG. 5A can be coupled through the dummy metal layer M. are connected together to form a short circuit, and since the resistance R of the simulated metal layer M is obtained according to V _DS /I _DS , the simulated metal layer M can exhibit the equivalent of Characteristics of transient voltage drop tolerance value ΔV. As for FIG. 6A and FIG. 6B , they respectively show cross-sectional views of the multi-threshold complementary metal oxide semiconductor transistor 5 that has not been added to the dummy metal layer M and the multi-threshold complementary metal oxide semiconductor transistor 5 ′ that has been added to the dummy metal layer M. I will repeat them separately.

Afterwards, the changing module 34 will change the power source coupled to the power pin VDD of the multi-threshold complementary metal oxide semiconductor transistor 5'. Please refer to FIG. 7A and FIG. 7B. FIG. 7A and FIG. 7B show the program code of the netlist (netlist) before changing the power supply coupled to the power pin VDD and the program code after changing the power supply coupled to the power pin VDD, respectively. Netlist program code. It can be seen from FIG. 7A and FIG. 7B that the changing module 34 changes the power supply coupled to the power supply pin VDD of the multi-threshold complementary metal oxide semiconductor transistor 5' from the original switched VDD to the constant VDD. , but not limited to this.

As for FIG. 8 , a schematic diagram of current flowing from the power pad to the multi-threshold CMOS transistor is shown. As shown by the arrow in FIG. 8, the current between the power terminal/ground terminal will flow from the power supply pad P to the multi-threshold complementary metal oxide semiconductor transistor 5', and flow from the multi-threshold complementary metal oxide semiconductor transistor 5' to The network (mesh) and the current flowing from the network to the standard electronic component std cell, that is, the current between the power terminal/ground terminal can flow from the power pad P to all nodes (nodes) coupled to the network.

Finally, the measurement module 36 will measure a transient voltage drop of the dummy metal layer added to the multi-threshold CMOS transistor. It is worth noting that since the originally separated constant VDD and switched VDD in the multi-threshold complementary metal oxide semiconductor transistor have been coupled together through the dummy metal layer to form a short circuit, the The method only needs to use general EDA software to accurately measure the static transient voltage drop of the multi-threshold complementary metal oxide semiconductor transistor. That is, the transient voltage drop measured by the measuring module is substantially the static transient voltage drop of the multi-threshold CMOS transistor.

The second specific embodiment according to the present invention is a static transient voltage drop analysis method. In this embodiment, the static transient voltage drop analysis method is used to analyze the static transient voltage drop of a multi-threshold complementary metal oxide semiconductor transistor disposed in a power gate control circuit, and the power gate control circuit can be configured In a mobile communication device or other electronic devices, it is used to turn off modules whose functions will not be used temporarily in the mobile communication device or other electronic devices, such as communication modules, short message modules or game modules, so as to reduce its overall total power Consumption, but not limited to this.

Please refer to FIG. 9 , which is a flow chart of the static transient voltage drop analysis method. As shown in FIG. 9 , first, the method executes step S10 , estimating a transient voltage drop tolerance value according to the transient voltage drop characteristic of the multi-threshold complementary metal oxide semiconductor transistor. In fact, the method simulates the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor through a general SPICE simulation program, and thereby estimates the transient voltage drop tolerance corresponding to the multi-threshold complementary metal oxide semiconductor transistor. value.

Next, the method executes step S11, selecting a corresponding simulated metal layer from a plurality of candidate simulated metal layers according to the transient voltage drop tolerance value. In practical applications, the plurality of candidate dummy metal layers and their corresponding transient voltage drop tolerance values can be pre-recorded in a look-up table, and the respective sizes and resistance values of the plurality of candidate dummy metal layers are recorded.

Then, the method executes step S12, adding the dummy metal layer into the multi-threshold CMOS transistor. More specifically, the method couples the dummy metal layer between the equal power supply voltage and the switching power supply voltage, so that the originally separated equal power supply voltage and switching power supply voltage can form a short circuit through the dummy metal layer.

Afterwards, the method executes step S13 , changing the power source coupled to the power pin of the multi-threshold complementary metal oxide semiconductor transistor. In this embodiment, the method changes the power source coupled to the power pin of the multi-threshold complementary metal oxide semiconductor transistor from the original switching power supply voltage to an equal power supply voltage, but not limited thereto.

Finally, the method executes step S14 to measure a transient voltage drop of the dummy metal layer added to the multi-threshold CMOS transistor. It is worth noting that since the originally separated equal power supply voltage and switching power supply voltage in the multi-threshold complementary metal oxide semiconductor transistor have been coupled together through the dummy metal layer to form a short circuit, so this method only needs to pass through the general EDA software The static transient voltage drop of the multi-threshold complementary metal oxide semiconductor transistor can be accurately measured through the simulated metal layer. That is, the measured transient voltage drop is substantially the static transient voltage drop of the multi-threshold CMOS transistor.

For example, assuming that the transient voltage drop tolerance value of the multi-threshold complementary metal-oxide-semiconductor transistor obtained in step S10 of the method is 5%, the method can further select from the numerous candidate simulated metal layers recorded in the look-up table The simulated metal layer N corresponding to 5% of the transient voltage drop tolerance value is selected, and the width of the simulated metal layer N is 0.09 microns and its resistance value is 0.101 ohms according to the information recorded in the look-up table.

Next, in the method, the dummy metal layer N is coupled between the equal power supply voltage and the switching power supply voltage, so that the equal power supply voltage and the switching power supply voltage form a short circuit through the dummy metal layer N, and the multi-threshold complementary metal oxide semiconductor transistor The power source coupled to the power pin is changed from the original switching power supply voltage to the equal power supply voltage. Therefore, in the end, the method can accurately measure the static transient voltage drop of the multi-threshold complementary metal oxide semiconductor transistor through common EDA software.

Compared with the prior art, according to the static transient voltage drop analysis device and the static transient voltage drop analysis method of the present invention, a transient voltage of the multi-threshold complementary metal oxide semiconductor transistor to be tested is first estimated by a common SPICE simulation program After reducing the tolerance value, a dummy metal layer corresponding to the transient voltage drop tolerance value is added to the multi-threshold complementary metal oxide semiconductor transistor, so that the originally separated equal power supply voltage and switching power supply voltage pass through the dummy metal layer are coupled together to form a short circuit, and then accurately measure the static transient voltage drop of the multi-threshold CMOS transistor through the dummy metal layer.

Therefore, the static transient voltage drop analysis device and the static transient voltage drop analysis method proposed by the present invention do not need to rely on some specially designed analysis software like the prior art, and only need to use general EDA software to accurately measure The static transient voltage drop of the multi-threshold complementary metal-oxide-semiconductor transistor can save the huge cost of additionally setting these specially designed analysis software.

Through the above detailed description of the preferred embodiments, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

Claims (15)

1. A static transient voltage drop analysis device for measuring a static transient voltage drop of a multi-threshold complementary metal oxide semiconductor transistor, the static transient voltage drop analysis device comprising: An estimation module, used to estimate a transient voltage drop tolerance value according to the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor; A processing module, coupled to the estimation module, is used to select a simulated metal layer from a plurality of candidate simulated metal layers according to the transient voltage drop tolerance value, and add the simulated metal layer to the multi-threshold complementary metal oxide In semiconductor transistors; and a measurement module for measuring a transient voltage drop of the dummy metal layer added to the multi-threshold complementary metal oxide semiconductor transistor; Wherein, the transient voltage drop measured by the measurement module is the static transient voltage drop of the multi-threshold CMOS transistor. 2. The static transient voltage drop analysis device according to claim 1, wherein the multi-threshold complementary metal oxide semiconductor transistor is arranged in a power gate control circuit, and the power gate control circuit includes a switching power supply voltage And first-class power supply voltage. 3. The static transient voltage drop analysis device according to claim 2, further comprising: A modification module, coupled to the processing module and the multi-threshold complementary metal oxide semiconductor transistor, for changing the power supply coupled to a power pin of the multi-threshold complementary metal oxide semiconductor transistor from the original switching power supply voltage Change to these supply voltages. 4. The static transient voltage drop analysis device according to claim 2, wherein the multi-threshold complementary metal oxide semiconductor transistor comprises a first electrode and a second electrode, and the first electrode is coupled to the a power supply voltage and the second electrode is coupled to the switching power supply voltage, the processing module couples the dummy metal layer between the first electrode and the second electrode, so that the first electrode and the second electrode form a short circuit . 5 . The static transient voltage drop analysis device according to claim 4 , wherein the measurement module measures the transient voltage drop of the simulated metal layer through general EDA software. 6 . The static transient voltage drop analysis device according to claim 1 , wherein the plurality of candidate simulated metal layers and corresponding transient voltage drop tolerance values are pre-recorded in a look-up table. 7. The static transient voltage drop analysis device according to claim 6, wherein the look-up table further records the sizes and resistance values of the plurality of candidate simulated metal layers, when the processing module selects the simulated metal layer , the processing module can also obtain the size and resistance value of the simulated metal layer from the look-up table, and set the simulated metal layer on the multi-threshold complementary metal oxide semiconductor transistor according to the size and resistance value of the simulated metal layer Inside. 8. The static transient voltage drop analysis device according to claim 1, wherein the estimation module executes a SPICE simulation program to simulate the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor to estimate the transient voltage drop state voltage drop tolerance value. 9. A static transient voltage drop analysis method for measuring a static transient voltage drop of a multi-threshold complementary metal oxide semiconductor transistor, the method comprising the following steps: Estimate a transient voltage drop tolerance value according to the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor; selecting a simulated metal layer from a plurality of candidate simulated metal layers according to the transient voltage drop tolerance value; adding the dummy metal layer to the multi-threshold CMOS transistor; and measuring a transient voltage drop of the dummy metal layer added to the multi-threshold CMOS transistor; Wherein, the measured transient voltage drop is the static transient voltage drop of the multi-threshold CMOS transistor. 10. The static transient voltage drop analysis method according to claim 9, wherein the multi-threshold complementary metal oxide semiconductor transistor is arranged in a power gate control circuit, and the power gate control circuit includes a switching power supply voltage And first-class power supply voltage. 11. The static transient voltage drop analysis method according to claim 10, characterized in that, after the step of adding the dummy metal layer to the multi-threshold CMOS transistor, the method further comprises the following steps: The power source coupled to a power pin of the multi-threshold complementary metal oxide semiconductor transistor is changed from the original switching power supply voltage to the power supply voltages. 12. The static transient voltage drop analysis method according to claim 10, wherein the multi-threshold complementary metal oxide semiconductor transistor comprises a first electrode and a second electrode, and the first electrode is coupled to the power supply voltage and the second electrode is coupled to the switching power supply voltage, in the step of adding the dummy metal layer to the multi-threshold complementary metal oxide semiconductor transistor, the dummy metal layer is coupled between the first electrode and the second Between the electrodes, the first electrode and the second electrode form a short circuit. 13. The static transient voltage drop analysis method according to claim 12, characterized in that, in the step of measuring the transient voltage drop of the simulated metal layer, the method measures the simulated metal by general EDA software layer for this transient voltage drop. 14. The static transient voltage drop analysis method according to claim 9, characterized in that, in the step of selecting the corresponding simulated metal layer, the method can also simultaneously obtain the size and resistance value of the simulated metal layer , and the dummy metal layer is set in the multi-threshold CMOS transistor according to the size and resistance value of the dummy metal layer. 15. The static transient voltage drop analysis method according to claim 9, characterized in that in the step of estimating the transient voltage drop tolerance value according to the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor transistor The method executes a SPICE simulation program to simulate the transient voltage drop characteristics of the multi-threshold complementary metal oxide semiconductor field transistor, so as to estimate the transient voltage drop tolerance value.

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