TWI539310B - Method and apparatus for conducting voltage drop analysis - Google Patents

Description

Method and device for power analysis

The present invention relates to a method and apparatus for power supply analysis, and more particularly to a method and apparatus for overall wafer drop (IR drop) analysis.

With the evolution of R&D technology, process technology is changing with each passing day. Due to the cost of area, chips reduce the size of devices to reduce the design size of the entire circuit. The reference voltage is also required to be reduced to reduce the power consumption of the power supply. The voltage of the wafer is reduced from the previous 3.3 volts, 2.5 volts, and 1.8 volts to 1.2 volts in the 0.13 μm process. It is now very common to operate voltages below 1 volt. Specifications. Therefore, under the premise that the size of the wafer is getting smaller and smaller, the voltage of the voltage source is reduced to reduce the power consumption, so that the ability of the wafer to withstand the noise margin is relatively reduced. Therefore, when designing the voltage source distribution of the entire wafer circuit, it is necessary to consider the effect of the voltage drop (IR-drop). Because the voltage source is stable or not, it directly affects the performance of the entire circuit. In other words, the design analysis of the voltage source needs to be more thorough to achieve a more realistic result.

Perform Chip Power Analysis to find out where the voltage drop on the wafer occurs and get information on various power consumption. For this analysis, it is necessary to input the relevant design reference materials of the integrated circuit design, and use the computer-aided design software to obtain the power grid models of the integrated circuit design, and then further develop the power network model of the integrated circuit design. Analysis, the magnitude and distribution of the pressure drop can be obtained.

The voltage drop is a phenomenon that indicates that the voltage on the power supply and the ground network is falling or rising in the integrated circuit. As the semiconductor process progresses, the width of the metal interconnect line becomes narrower and narrower, causing its resistance value to rise, so there will be a certain voltage drop across the entire wafer. In addition, a power management cell, a power gating switch, and a logic gate cell can be regarded as a unit having an equivalent resistance and generating a voltage drop when the turn-on current is passed.

Figure 1 is a schematic illustration of a conventional wafer. It is assumed that a top level design of the wafer 10 includes three circuit blocks 11, 12, 13 and other circuit cells having different functions, and is respectively connected to a power signal VDD and a ground signal VSS. At present, the integrated circuit design industry will directly obtain the design of the circuit block or circuit module of the specific function from the IP vendor (for example, ARM), and most of the intellectual property suppliers only provide the circuit block and then the winding. The layout of the GDSII format data, so there is no information on the internal circuit components of the circuit block. That is, if the power analysis of the wafer 10 is performed, the internal power network analysis of the circuit block needs to be skipped, so that the voltage drop size and distribution of the entire wafer cannot be obtained.

Figure 2 is a pressure drop profile of a conventional wafer. In the lower right corner of the figure, there is a black rectangular area 21, which is a circuit block that does not have the information of the internal power management unit, for example, a circuit block containing a multi-threshold voltage complementary metal oxide conductor (MTCMOS) unit, so The distribution of the pressure drop in this area is indicated by color.

In view of this, the Electronic Design Automation industry needs a way to obtain the results of the voltage drop analysis of a complete wafer in order to solve the problems encountered in current circuit design.

It is an object of the present invention to extract the power distribution within a circuit block from a circuit layout to obtain a voltage drop magnitude and distribution throughout the wafer after power analysis.

The method for power supply analysis according to an embodiment of the present invention comprises the steps of: receiving design data of a chip, wherein the chip comprises a circuit block of unknown internal power management unit, and the design data is a winding layout after the circuit block; The layout corresponds to the content of the composition, and the information of the internal power component of the circuit block is extracted from the rear winding layout; and the power analysis of the circuit block is performed according to the information of the internal power component.

A device for power analysis according to another embodiment of the present invention includes a circuit component extraction unit, a circuit component patterning unit, and a power analysis unit. The circuit component extracting unit extracts information of the internal power components of the circuit block from the winding layout of a circuit block whose internal structure is unknown according to the layout corresponding to the content of the composition. The circuit component patterning unit establishes complete design information of the circuit block according to the information of the internal power component. The power analysis unit performs power analysis of the circuit block.

The method of the present invention first extracts the information of the internal circuit components of the circuit block from the rear winding layout of the circuit block according to the content of the layout and line comparison check (LVS), and then performs power analysis of the circuit block. Therefore, even if the circuit block is directly obtained by the Wisdom provider, and only the GDSII format data of the winding layout of the circuit block is obtained, the present invention can still perform power analysis on the chip, and obtain the voltage drop size and distribution of the entire chip. And as the basis for circuit design engineers to improve circuit design.

The invention discussed herein is a method of power analysis and apparatus therefor. In order to thoroughly understand the present invention, detailed steps and compositions will be set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the circuit design. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. .

3 is a schematic diagram of circuit blocks in accordance with an embodiment of the present invention. The circuit block 30 is connected to the power signal VDD of the chip, and the power signal VDD is connected to the internal virtual power signal 32 by a plurality of multiple threshold voltage complementary metal oxide conductor (MTCMOS) power gate switches 31. The circuit components in circuit block 30 are directly supplied with power required by the network composed of virtual power signals 32, such as logic elements and memory cells. The MTCMOS power gate switch 31 can be used to reduce the leakage current in the circuit block 30 for low power integrated circuit design techniques. However, when the MTCMOS power gate switch 31 is in the on state, the current will pass through the MTCMOS, and the switch can be regarded as a power consuming component having an equivalent resistance to generate a voltage drop.

As mentioned above, the current integrated circuit design industry will directly obtain the design data of the circuit block or circuit module of the specific function from the supplier of the intellectual property, and most of the suppliers of the smart money only provide the layout of the circuit after the circuit. GDSII format data, so users do not have access to the information of the internal MTCMOS power gate switch of the circuit block.

In order to improve the conventional technology, it is impossible to analyze the problem of the power supply of the circuit block which is unknown inside. 4 is a flow chart showing a power analysis method according to an embodiment of the present invention. As shown in step 41, the method first receives design data of a chip, wherein the chip includes a plurality of circuit blocks and a plurality of circuit units having different functions, wherein it is assumed that the first circuit block is provided by the provider of the intellectual property, The second circuit block is designed by the user, and the design data of the first circuit block is a rear winding layout, and the first circuit block and the second circuit block belong to each of the top level design structures. Module. Since the pattern in the winding layout after the circuit block cannot directly know which of the first circuit block is the power management unit, the power gate switch, and the logic gate unit, it is necessary to correspond to the composition content (LVS) according to the layout. The information of the internal circuit components of the first circuit block is extracted from the rear winding layout, as shown in step S42. It is also to find out the corresponding circuit components, especially the power management unit and the power gate switch, by the layout corresponding to the pattern in the layout of the rear winding.

As shown in step S43, the information of the internal circuit components of the first circuit block obtained in step S42 is integrated with the design data of the second circuit block, and the purpose of integration is to facilitate circuit simulation of the entire chip.

As shown in step S44, the power analysis of the first circuit block and the second circuit block is performed, and the analysis work can be performed using synopsys. The software's software PrimeRail is completed to effectively analyze static and dynamic voltage drops and electron migration (EM) on the complete wafer. Finally, as shown in step S45, information on the voltage drop and power consumption of the entire wafer is obtained. This information can be used by integrated circuit designers to compare and evaluate compliance with design specifications or to further correct circuit design to reduce power consumption.

Figure 5 is a pressure drop profile obtained from power analysis in accordance with an embodiment of the present invention. Compared to Figure 2, Figure 5 can show the voltage drop distribution across the wafer without any areas that bypass the circuit blocks. In addition, the distribution of the voltage drop across the wafer can be indicated by color, and the occurrence of the maximum voltage drop can be clearly seen, so the circuit design can be corrected to solve the problem of too large a voltage drop.

Compared with the prior art, since the conventional technology cannot completely analyze the voltage drop distribution and power consumption information of the entire wafer, it is obvious that the integrated circuit design manufacturer cannot immediately know the true design result of the chip. However, the present invention can improve such problems encountered in the prior art, and can find the presence of hot spots during the placement and winding stages, and correct the design in advance in the design flow.

Figure 6 is a functional block diagram of a power analysis device in accordance with an embodiment of the present invention. The power analysis device 60 includes a circuit component extraction unit 61, a circuit component patterning unit 62, and a power analysis unit 63 for analyzing a wafer including at least a first circuit block and at least a second circuit. The power supply. The circuit component extraction unit 61 extracts information about the internal circuit components of the first circuit block from the wire layout of the first circuit block according to the layout corresponding to the content of the composition (LVS), for example, the layout pattern Identify components such as power management unit, power gate switch and logic gate unit and related specifications. The circuit component patterning unit 62 then establishes complete design information of the first circuit block based on the information of the internal circuit components. For example, if the first circuit block is a memory block, the circuit component patterning unit 62 generates a composition of the memory block model according to the output of the circuit component extraction unit 61. The power analysis unit 63 further integrates the complete design data of the first circuit block and the complete design data of the second circuit block, and performs power analysis of the first circuit block and the second circuit block, so that the entire chip can be obtained. Information on voltage drop and power consumption.

The method of the present invention first extracts the information of the internal circuit components of the circuit block from the rear winding layout of the circuit block according to the layout corresponding to the content of the composition (LVS), and then performs power analysis of the circuit block. Therefore, even if the circuit block is directly obtained by the Wisdom provider, and only the GDSII format data of the winding layout of the circuit block is obtained, the present invention can still perform power analysis on the chip, and obtain the voltage drop size and distribution of the entire chip. And as the basis for circuit design engineers to improve circuit design.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

10. . . Wafer

11. . . Circuit block

12. . . Circuit block

13. . . Circuit block

twenty one. . . Rectangular area

30. . . Circuit block

31. . . Power switch

32. . . Virtual power signal VDD

33. . . Short circuit critical area

60. . . Power analysis device

61. . . Circuit component extraction unit

62. . . Circuit component composition unit

63. . . Power analysis unit

VDD. . . Power signal

VSS. . . Ground signal

Figure 1 is a schematic view of a conventional wafer;

Figure 2 is a pressure drop distribution diagram of a conventional wafer;

Figure 3 is a schematic illustration of the concept in accordance with the present invention;

4 is a flow chart of a method for analyzing a power supply according to an embodiment of the present invention;

5 is a pressure drop distribution diagram obtained by power supply analysis according to an embodiment of the present invention;

Figure 6 is a functional block diagram of a power analysis device in accordance with an embodiment of the present invention.

S41～S45. . . step

Claims (12)

A method for power analysis of a chip design, the chip design including a circuit block of an internal power supply unit, the circuit block being presented in a post-wrap layout, the method comprising: using a layout corresponding to the composition of the material from the The circuit block of the chip design then extracts a plurality of components inside the circuit block and respectively corresponds to each component to a known component model, wherein the components include a first component and cannot correspond to a known component. a component model; and performing a power analysis of the circuit block to obtain a component model of the first component based on the known component models of the extracted plurality of components. The method of claim 1, wherein the power analysis comprises: obtaining an internal power supply voltage drop and power consumption of the circuit block. According to the method of claim 1, the method further comprises: integrating the internal structure of the entire chip to calculate internal power supply voltage drop information and power consumption information of the entire chip. The method of claim 1, wherein the internal power supply unit is one of a power management unit, a power gate switch, or a logic gate unit. The method of claim 1, wherein the first component is a multiple threshold voltage complementary metal oxide conductor (MTCMOS) power gate switch, wherein the multiple threshold voltage complementary metal oxide conductor power gate switch cannot correspond to a known Component model. According to the method of claim 3, wherein the internal power supply voltage drop information is the crystal The complete pressure drop distribution of the film. According to the method of claim 3, the method further comprises: comparing the information of the internal power supply voltage drop and power consumption with the design specifications of the chip; and correcting the chip design according to the comparison result. A device for power supply analysis, comprising: a circuit component extraction unit, extracting a plurality of components inside the circuit block from a rear winding layout of one of the circuit blocks of one of the internal power supply units of one of the wafers according to the layout corresponding to the composition data And corresponding to each component to a known component model, wherein the components comprise a first component and cannot correspond to a known component model; a circuit component patterning unit, according to the component model and the first component Establishing a component composition of the circuit block; and a power analysis unit performing power analysis of the circuit block to learn the component model of the first component. The device of claim 8, wherein the power analysis unit outputs information on internal power supply voltage drop and power consumption of the entire chip. The device of claim 8, wherein the internal power supply unit is one of a power management unit, a power gate switch, or a logic gate unit. The device of claim 8, wherein the first component is a multiple threshold voltage complementary metal oxide semiconductor (MTCMOS) power gate switch, wherein the multiple threshold voltage complementary metal oxide conductor power gate switch cannot correspond to a known Component model. The device of claim 9, wherein the pressure drop is a complete pressure drop profile of the wafer.