CN102103991A - Manufacturing methods of epitaxial layer and transistor - Google Patents
Manufacturing methods of epitaxial layer and transistor Download PDFInfo
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- CN102103991A CN102103991A CN2009102013471A CN200910201347A CN102103991A CN 102103991 A CN102103991 A CN 102103991A CN 2009102013471 A CN2009102013471 A CN 2009102013471A CN 200910201347 A CN200910201347 A CN 200910201347A CN 102103991 A CN102103991 A CN 102103991A
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Abstract
The invention provides manufacturing methods of an epitaxial layer and a transistor. The manufacturing method of the epitaxial layer comprises the following steps of: providing a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; forming an isolating layer on the semiconductor substrate and the grid structure; forming a sacrificial spacing layer on a side wall of the isolating layer; forming a recess in the semiconductor substrate on two sides of the sacrificial spacing layer; and forming the epitaxial layer in the recess by using a selective epitaxial technology. By the manufacturing method of the epitaxial layer, a load effect is reduced and the performance of the transistor is improved.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of epitaxial loayer and transistor fabrication method.
Background technology
In traditional technology, stress (stress) can be incorporated in the channel region of MOS transistor (MOStransistor), with increase carrier mobility (carrier mobility), and then the performance of raising MOS transistor.General, for nmos pass transistor, wish at the channel region generation tensile stress (tensile stress) of source electrode to drain directions; And for the PMOS transistor, wish in the channel region generation compression (compressive stress) of source electrode to drain directions.
With the PMOS transistor is example, in order to produce compression at its channel region, need form epitaxial loayer at transistorized source electrode of PMOS and drain region, described epitaxial loayer is a SiGe, because SiGe has bigger lattice constant than silicon, so its rete inside has compression stress, and this compression pressure can be transferred on the horizontal direction, in the transistorized raceway groove of this PMOS, producing compression, and then improve the mobility in hole.And for nmos pass transistor, need be the epitaxial loayer of carborundum at its source electrode and drain region formation material then, to improve the mobility of electronics.
Detailed, please refer to Figure 1A～1E, it is the generalized section of each step corresponding construction of existing epitaxial loayer manufacture method.
With reference to Figure 1A, Semiconductor substrate 100 at first is provided, described Semiconductor substrate 100 can be silicon substrate.Be formed with grid structure on the Semiconductor substrate 100, also be formed with shallow channel isolation area 110 in the Semiconductor substrate 100.Described grid structure comprises gate dielectric 121 and gate electrode 122.Wherein, the material of gate dielectric 121 is a silicon dioxide, and the material of gate electrode 122 is polysilicons, also can mix foreign ion in the described polysilicon, to reduce the resistivity of grid structure.
Wherein, described grid structure be utilize traditional deposition, photoetching and lithographic technique form, owing in the process that forms grid structure, adopted dry etching technology, plasma in the described dry etching can cause the lattice structure on grid structure surface destroyed, thus the performance of the semiconductor device that influence forms.In order to repair grid structure surface etch damage, usually to described grid structure carry out rapid thermal oxidation (Rapid ThermalOxidation, RTO).
Shown in Figure 1B; described rapid thermal oxidation process is exposed in the oxygen atmosphere of high temperature by the surface with described grid structure; sidewall surfaces at described grid structure forms first oxide layer 131; reach the purpose of repairing the ruined lattice structure of described grid structure; and described first oxide layer 131 also can be protected described grid structure, guarantees that described grid structure is not subjected to the damage of follow-up etch step of carrying out.Yet described rapid thermal oxidation process makes that also the Semiconductor substrate 100 of gate dielectric 121 both sides is oxidized when repairing the damage of grid structure sidewall, generate second oxide layer 132.
With reference to figure 1C, on the sidewall of first oxide layer 131, form sacrificial spacer layer 140.
With reference to figure 1D, second oxide layer 132 and the Semiconductor substrate 100 of dry etching sacrificial spacer layer 140 both sides form depressed area 150a in the Semiconductor substrate 100 of sacrificial spacer layer 140 both sides.Because the dry etching anisotropic, second oxide layer 132 of first oxide layer 131 and sacrificial spacer layer 140 belows is not etched away, and still keeps the residue second oxide layer 132a of a part.
With reference to figure 1E, (selective epitaxial growth, SEG) technology forms epitaxial loayer 150, the material SiGe or the carborundum of described epitaxial loayer 150 in the 150a of depressed area to utilize selective epitaxial.
To form silicon Germanium films is example, and the manufacturing method thereof that is commonly used to carry out the selective epitaxial deposition is to use dichlorosilane as silicon source gas, and germane is as germanium source gas, and hydrogen chloride is as etching gas, and with hydrogen or nitrogen as carrier gas.Described selective epitaxial process comprises deposition reaction and etching reaction, and described deposition reaction is carried out on Semiconductor substrate 100 with different relatively reaction rates with etching reaction.When comprising the silicon face that comes out and other material surface on the Semiconductor substrate 100, can carry out the growth step of selectivity silicon-containing film.The deposition reaction of described selective epitaxial process is at silicon face growth germanium atom and silicon metal, and at other material surface growth germanium atom and indefinite form silicon or polysilicon.Described etching gas can be than fast many of the etch-rate of the germanium atom of silicon face and silicon metal to the etch-rate of the germanium atom of other material surface growth and indefinite form silicon or polysilicon, thereby can finish optionally epitaxial growth.
Yet, in actual production, find, because the existence of the residue second oxide layer 132a makes to comprise two kinds of surfaces that in the 150a of depressed area a kind of is silicon face.Another is a silica surface.Therefore, in the 150a of depressed area, the silicon face that comes out can form SiGe, and it is leading that the second oxide layer 132a surface then is that etching reaction accounts for, and can't form SiGe.Therefore, shown in Fig. 1 E, the epitaxial loayer 150 that forms does not fill up depressed area 150a, that is to say, the surface of epitaxial loayer 150 not with the flush of Semiconductor substrate 100, epitaxial loayer 150 miss the mark thickness also are called this phenomenon load effect (loadingdefect) usually, load effect will influence the mobility of charge carrier rate, make transistorized decreased performance.
Summary of the invention
The invention provides a kind of epitaxial loayer manufacture method, load effect occurs when prior art forms epitaxial loayer, can't form the problem of the epitaxial loayer of target thickness, improved transistorized performance to solve.
For solving the problems of the technologies described above, the invention provides a kind of epitaxial loayer manufacture method, comprising: Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate; On described Semiconductor substrate and described grid structure, form separator; On the sidewall of described separator, form sacrificial spacer layer; In the Semiconductor substrate of described sacrificial spacer layer both sides, form the depressed area; Utilize selective epitaxial process in described depressed area, to form epitaxial loayer.
Optionally, the thickness of described separator is
The material of described separator is a silicon dioxide, and described separator is that the mode by chemical vapour deposition (CVD) forms.
Optionally, described grid structure comprises gate dielectric and is formed at gate electrode on the described gate dielectric, and the material of described gate dielectric is a silicon dioxide, and the material of described grid conducting layer is a polysilicon.
Optionally, the material of described sacrificial spacer layer is a silicon nitride.
Optionally, the material of described epitaxial loayer is SiGe or carborundum.
Optionally, utilize selective epitaxial process to form in described depressed area after the epitaxial loayer, this epitaxial loayer manufacture method also comprises: remove described sacrificial spacer layer and described separator.
Optionally, remove after the described separator, this epitaxial loayer manufacture method also comprises: described grid structure is carried out boiler tube thermal oxidation or rapid thermal oxidation process.
The present invention also provides a kind of transistor fabrication method, comprising: Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate; On described Semiconductor substrate and described grid structure, form separator; On the sidewall of described separator, form sacrificial spacer layer; In the Semiconductor substrate of described sacrificial spacer layer both sides, form the depressed area; Utilize selective epitaxial process in described depressed area, to form epitaxial loayer; Remove described sacrificial spacer layer and described separator; Described grid structure is carried out boiler tube thermal oxidation or rapid thermal oxidation process; Form side wall layer at described grid structure sidewall; With described grid structure and described side wall layer is mask, carries out ion implantation technology, to form source electrode and drain electrode in the Semiconductor substrate of described side wall layer both sides.
Optionally, the thickness of described separator is
The material of described separator is a silicon dioxide, and described separator is that the mode by chemical vapour deposition (CVD) forms.
Optionally, described grid structure comprises gate dielectric and is formed at gate electrode on the described gate dielectric, and the material of described gate dielectric is a silicon dioxide, and the material of described grid conducting layer is a polysilicon.
Optionally, the material of described sacrificial spacer layer is a silicon nitride.
Optionally, the material of described epitaxial loayer is SiGe or carborundum.
Compared with prior art, epitaxial loayer manufacture method provided by the invention has the following advantages:
Described epitaxial loayer manufacture method forms separator on Semiconductor substrate and grid structure; described separator can be protected described grid structure; guarantee that described grid structure is not subjected to the damage of follow-up etch step of carrying out; and described epitaxial loayer manufacture method is being utilized selective epitaxial process forms epitaxial loayer in the depressed area before; grid structure is not carried out boiler tube thermal oxidation or rapid thermal oxidation process; avoid the Semiconductor substrate of grid structure both sides oxidized; guarantee that the epitaxial loayer that utilizes selective epitaxial process to form fills up the depressed area; can form epitaxial loayer with target thickness; load effect appears in minimizing, has improved transistorized performance.
Description of drawings
Figure 1A to Fig. 1 E is the generalized section of each step corresponding construction of existing epitaxial loayer manufacture method;
Fig. 2 is the flow chart of the epitaxial loayer manufacture method that the embodiment of the invention provided;
Fig. 3 A to Fig. 3 E is the generalized section of each step corresponding construction of the epitaxial loayer manufacture method that the embodiment of the invention provided;
Fig. 4 is the flow chart of the transistor fabrication method that the embodiment of the invention provided.
Embodiment
Core concept of the present invention is; a kind of epitaxial loayer manufacture method is provided; this epitaxial loayer manufacture method forms separator on Semiconductor substrate and grid structure; described separator can be protected described grid structure; guarantee that described grid structure is not subjected to the damage of follow-up etch step of carrying out; and described epitaxial loayer manufacture method is being utilized selective epitaxial process forms epitaxial loayer in the depressed area before; grid structure is not carried out boiler tube thermal oxidation or rapid thermal oxidation process; avoid the Semiconductor substrate of grid structure both sides oxidized; guarantee that the epitaxial loayer that utilizes selective epitaxial process to form fills up the depressed area; can form epitaxial loayer with target thickness; load effect appears in minimizing, has improved transistorized performance.
Please refer to Fig. 2, the flow chart of the epitaxial loayer manufacture method that its embodiment of the invention provided, in conjunction with this figure, the method comprising the steps of:
Step S21 provides Semiconductor substrate, is formed with grid structure on the described Semiconductor substrate;
Step S22 forms separator on described Semiconductor substrate and described grid structure;
Step S23 forms sacrificial spacer layer on the sidewall of described separator;
Step S24 forms the depressed area in the Semiconductor substrate of described sacrificial spacer layer both sides;
Step S25 utilizes selective epitaxial process to form epitaxial loayer in described depressed area.
Below in conjunction with generalized section epitaxial loayer manufacture method of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
With reference to Fig. 3 A, at first, provide Semiconductor substrate 300, be formed with grid structure on the described Semiconductor substrate 300.
Wherein, Semiconductor substrate 300 is silicon substrates, also is formed with one or more shallow channel isolation areas 310 in the described Semiconductor substrate 300, and described shallow channel isolation area 310 is used for the active area in the isolation of semiconductor substrate 300.Can utilize traditional photoetching, etching and dielectric substance fill method to form shallow channel isolation area 310, not repeat them here.
Described grid structure can utilize traditional thin film deposition, photoetching and lithographic technique to form, and described grid structure comprises gate dielectric 321 and is formed at gate electrode 322 on the gate dielectric 321.
The material of described gate dielectric 321 is a silicon dioxide, and the material of gate dielectric 321 also can be silicon oxynitride or other dielectric material certainly.
The material of gate electrode 322 is polysilicons, the mode that can utilize in-situ doped or the injection of dystopy (ex-situ) ion is at described polysilicon impurity ion, described foreign ion can be boron ion, arsenic ion or phosphonium ion, and the concentration range of the foreign ion that is used to mix is generally 1 * 10
18～1 * 10
20/ cm
2, in order to adjust the resistance of polysilicon.
With reference to figure 3B, on Semiconductor substrate 300 and grid structure, form separator 330.Described separator 330 can be protected described grid structure, guarantees that described grid structure is not subjected to the damage of follow-up etch step of carrying out, to improve transistorized performance.
The material of described separator 330 can be silicon dioxide, and it can form by the mode of chemical vapour deposition (CVD) or ald.For example, can utilize tetraethoxysilane (TEOS) to form silica membrane as liquid source material, adopt time aumospheric pressure cvd (Sub-Atmospheric Chemical VaporDeposition is called for short SACVD) equipment, as the PRODUCER chamber of company of Applied Materials.
According to the difference of the technological requirement of semiconductor device, the thickness of separator 330 also can be different.Preferably, the thinner thickness of separator 330 can guarantee can not have influence on the depressed area size of follow-up formation.In a specific embodiment of the present invention, the thickness of separator 330 is
With reference to figure 3C, on the sidewall of separator 330, form sacrificial spacer layer (disposable spacer) 340.In the process of follow-up formation depressed area, sacrificial spacer layer 340 is as mask layer.The material of described sacrificial spacer layer 340 can be a silicon nitride.
With reference to figure 3D, the separator 330 of dry etching sacrificial spacer layer 340 both sides and Semiconductor substrate 300 form depressed area 350a in the Semiconductor substrate 300 of sacrificial spacer layer 340 both sides.
With reference to figure 3E, utilize selective epitaxial (selective epitaxial growth, SEG) technology forms epitaxial loayer 350 in the 350a of depressed area, the material of described epitaxial loayer 350 is SiGe or carborundum.
Described epitaxial loayer 350 can utilize epitaxial device to finish, for example, and Epi Centura system and PolyGen system that company of Applied Materials produces.Certainly, can also be traditional batch high temperature furnace etc.Pressure in the process chamber of described epitaxial device can remain on 1～200Torr, and is preferable, and the pressure in the described process chamber remains between the 3Torr to 15Torr.In described process chamber, Semiconductor substrate 300 can be heated to 500～1000 ℃.Drive with mode of heating and to be combined into by multiple gases that mixture reacts and the epitaxial growth silicon metal.Preferable, Semiconductor substrate 300 is heated between 600 ℃ to 750 ℃.
If the material of epitaxial loayer 350 is SiGes, can use silane or dichlorosilane as silicon source (silicon forerunner), germane is as germanium source (germanium forerunner), hydrogen chloride or hydrogen bromide be as etching gas, and with hydrogen or nitrogen as carrier gas.If the material of described epitaxial loayer 350 is a carborundum, then can use silane or dichlorosilane as the silicon source, methyl carbon alkane is as carbon source (carbon forerunner), hydrogen chloride or hydrogen bromide be as etching gas, and with hydrogen or nitrogen as carrier gas.
Owing to utilizing selective epitaxial process forms epitaxial loayer 350 in the 350a of depressed area before, described grid structure is not carried out boiler tube thermal oxidation or rapid thermal oxidation process, therefore the Semiconductor substrate 300 of described grid structure both sides can be not oxidized, when guaranteeing to utilize the epitaxial loayer 350 of selective epitaxial process formation, depressed area 350a only exposes silicon face, therefore can guarantee that the SiGe or the carbofrax material of filling fill up depressed area 350a, make the surface of epitaxial loayer 350 and the flush of Semiconductor substrate 300, form the epitaxial loayer of target thickness, avoid occurring load effect.
In a specific embodiment of the present invention, utilize selective epitaxial process in the 350a of depressed area, to form after the epitaxial loayer 350, remove sacrificial spacer layer 340 and separator 330 again.Can utilize phosphoric acid solution to remove sacrificial spacer layer 340.Because the existence of separator 330 can guarantee that described phosphoric acid solution can not damage described grid structure.Afterwards, utilize the mode of dry etching or wet etching to remove described separator 330 again.
Remove after the separator 330, can carry out boiler tube thermal oxidation or rapid thermal oxidation process to described grid structure, be exposed to by surface in the oxygen atmosphere of high temperature described grid structure, sidewall surfaces at described grid structure forms oxide layer, reaches the purpose of repairing the ruined lattice structure of described grid structure.
The present invention also provides a kind of transistor fabrication method, specifically please refer to Fig. 4, the flow chart of the transistor fabrication method that its embodiment of the invention provided, and in conjunction with this figure, the method comprising the steps of:
Step S41 provides Semiconductor substrate, is formed with grid structure on the described Semiconductor substrate;
Step S42 forms separator on described Semiconductor substrate and described grid structure;
Step S43 forms sacrificial spacer layer on the sidewall of described separator;
Step S44 forms the depressed area in the Semiconductor substrate of described sacrificial spacer layer both sides;
Step S45 utilizes selective epitaxial process to form epitaxial loayer in described depressed area;
Step S46 removes described sacrificial spacer layer and described separator;
Step S47 carries out boiler tube thermal oxidation or rapid thermal oxidation process to described grid structure;
Step S48 forms side wall layer at described grid structure sidewall;
Step S49 is a mask with described grid structure and described side wall layer, carries out ion implantation technology, to form source electrode and drain electrode in the Semiconductor substrate of described side wall layer both sides.
Wherein, the thickness of described separator is
The material of described separator is a silicon dioxide, and described separator is that the mode by chemical vapour deposition (CVD) forms, and the material of described sacrificial spacer layer is a silicon nitride, and the material of described epitaxial loayer is SiGe or carborundum, and the material of described side wall layer is a silicon nitride.
Described transistor fabrication method forms separator on Semiconductor substrate and grid structure; described separator can be protected described grid structure; guarantee that described grid structure is not subjected to the damage of follow-up etch step of carrying out; and utilize selective epitaxial process in the depressed area, to form before the epitaxial loayer; grid structure is not carried out boiler tube thermal oxidation or rapid thermal oxidation process; avoid the Semiconductor substrate of described grid structure both sides oxidized; guarantee that the epitaxial loayer that utilizes selective epitaxial process to form fills up the depressed area; avoid occurring load effect; can guarantee to form epitaxial loayer with target thickness; increase carrier mobility, and then improved transistorized performance.
In sum, the invention provides a kind of epitaxial loayer manufacture method, this method comprises: Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate; On described Semiconductor substrate and described grid structure, form separator; On the sidewall of described separator, form sacrificial spacer layer; In the Semiconductor substrate of described sacrificial spacer layer both sides, form the depressed area; Utilize selective epitaxial process to form epitaxial loayer in described depressed area, this extension manufacture method can reduce load effect.The present invention also provides a kind of transistor fabrication method, to improve the mobility of charge carrier rate, improves transistorized performance.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (20)
1. epitaxial loayer manufacture method comprises:
Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate;
On described Semiconductor substrate and described grid structure, form separator;
On the sidewall of described separator, form sacrificial spacer layer;
In the Semiconductor substrate of described sacrificial spacer layer both sides, form the depressed area;
Utilize selective epitaxial process in described depressed area, to form epitaxial loayer.
2. epitaxial loayer manufacture method as claimed in claim 1 is characterized in that, the thickness of described separator is 20～
3. epitaxial loayer manufacture method as claimed in claim 1 or 2 is characterized in that, the material of described separator is a silicon dioxide.
4. epitaxial loayer manufacture method as claimed in claim 3 is characterized in that, described separator is that the mode by chemical vapour deposition (CVD) forms.
5. epitaxial loayer manufacture method as claimed in claim 4 is characterized in that, described grid structure comprises gate dielectric and is formed at gate electrode on the described gate dielectric.
6. epitaxial loayer manufacture method as claimed in claim 5 is characterized in that the material of described gate dielectric is a silicon dioxide.
7. epitaxial loayer manufacture method as claimed in claim 5 is characterized in that the material of described grid conducting layer is a polysilicon.
8. epitaxial loayer manufacture method as claimed in claim 4 is characterized in that the material of described sacrificial spacer layer is a silicon nitride.
9. epitaxial loayer manufacture method as claimed in claim 8 is characterized in that, the material of described epitaxial loayer is SiGe or carborundum.
10. epitaxial loayer manufacture method as claimed in claim 9 is characterized in that, utilizes selective epitaxial process to form after the epitaxial loayer in described depressed area, also comprises: remove described sacrificial spacer layer and described separator.
11. epitaxial loayer manufacture method as claimed in claim 10 is characterized in that, removes after the described separator, also comprises: described grid structure is carried out boiler tube thermal oxidation or rapid thermal oxidation process.
12. a transistor fabrication method comprises:
Semiconductor substrate is provided, is formed with grid structure on the described Semiconductor substrate;
On described Semiconductor substrate and described grid structure, form separator;
On the sidewall of described separator, form sacrificial spacer layer;
In the Semiconductor substrate of described sacrificial spacer layer both sides, form the depressed area;
Utilize selective epitaxial process in described depressed area, to form epitaxial loayer;
Remove described sacrificial spacer layer and described separator;
Described grid structure is carried out boiler tube thermal oxidation or rapid thermal oxidation process;
Form side wall layer at described grid structure sidewall;
With described grid structure and described side wall layer is mask, carries out ion implantation technology, to form source electrode and drain electrode in the Semiconductor substrate of described side wall layer both sides.
13. transistor fabrication method as claimed in claim 12 is characterized in that, the thickness of described separator is 20～
14., it is characterized in that the material of described separator is a silicon dioxide as claim 12 or 13 described transistor fabrication methods.
15. transistor fabrication method as claimed in claim 14 is characterized in that, described separator is that the mode by chemical vapour deposition (CVD) forms.
16. transistor fabrication method as claimed in claim 15 is characterized in that, described grid structure comprises gate dielectric and is formed at gate electrode on the described gate dielectric.
17. transistor fabrication method as claimed in claim 16 is characterized in that the material of described gate dielectric is a silicon dioxide.
18. transistor fabrication method as claimed in claim 16 is characterized in that the material of described grid conducting layer is a polysilicon.
19. transistor fabrication method as claimed in claim 15 is characterized in that the material of described sacrificial spacer layer is a silicon nitride.
20. transistor fabrication method as claimed in claim 19 is characterized in that, the material of described epitaxial loayer is SiGe or carborundum.
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| CN2009102013471A CN102103991A (en) | 2009-12-17 | 2009-12-17 | Manufacturing methods of epitaxial layer and transistor |
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| CN2009102013471A CN102103991A (en) | 2009-12-17 | 2009-12-17 | Manufacturing methods of epitaxial layer and transistor |
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Application publication date: 20110622 |