CN102097381B - CMOS (Complementary Metal-Oxide-Semiconductor) transistor and stress memory treatment method thereof - Google Patents
CMOS (Complementary Metal-Oxide-Semiconductor) transistor and stress memory treatment method thereof Download PDFInfo
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Abstract
The invention discloses a CMOS (Complementary Metal-Oxide-Semiconductor) transistor and a stress memory treatment method thereof. The method comprises the following steps of: providing a substrate with a formed CMOS transistor, wherein the lower surface of the substrate is provided with a silicon oxide layer corresponding to the inner layer of the side wall of a grid of the CMOS transistor and a silicon nitride layer corresponding to the outer layer of the side wall of the grid; sequentially depositing a buffer oxide layer and a stress silicon nitride layer on the upper surface of the CMOS transistor; removing the stress silicon nitride layer on the upper surface of a PMOS (P-channel Metal Oxide Semiconductor) transistor and annealing the substrate if the CMOS transistor comprises a NMOS (N-channel Metal Oxide Semiconductor) transistor and the PMOS transistor; directly annealing the substrate if the CMOS transistor comprises the NMOS transistor; and removing the stress silicon nitride layer on the upper surface of the NMOS transistor and the buffer oxide layer and keeping the silicon oxide layer and the silicon nitride layer, corresponding to the side wall of the grid, on the lower surface of the substrate. The stress memory treatment method in the invention is favorable for decreasing the occurrence probability of PID (Proportion Integration Differentiation) and saving cost, and is simple.
Description
Technical field
The present invention relates to the semiconductor device processing technology field, especially relate to the transistorized stress memory processing method of a kind of CMOS and CMOS transistor.
Background technology
Plasma treatment has been widely used in field of manufacturing semiconductor devices.But in manufacture process, plasma is known from experience the grid 1 ' upper (referring to Fig. 1) that is accumulated in device, when the plasma charge of accumulation reaches certain threshold quantity, the electric field that is positioned on the gate oxide 3 ' between grid 1 ' and the substrate 2 ' can puncture gate oxide 3 ', damage device, this phenomenon is called PID(Plasma Induced Damage, plasma-induced damage).
PID is at 65G(Generic) in the technological process than at 65LL(Low Leakage) even more serious in the technological process, this mainly is because the flow process of 65G arts demand application plasma treatment is more, the SMT(Stress Memorization Technology of its use for example, stress memory technique).
The CMOS transistor is divided into nmos pass transistor and PMOS transistor, and each CMOS transistor comprises grid, source electrode, drain electrode, gate oxide, gate lateral wall and conducting channel, and the internal layer of described gate lateral wall is silicon oxide layer, and skin is silicon nitride layer.After forming the transistorized gate lateral wall 30 ' of CMOS, inject formation source S, drain D (as shown in Figure 2) by foreign ion, use afterwards SMT that the CMOS transistor is processed.The process of SMT is: 1) adopt first PECVD(Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) be formed with the transistorized substrate top surface deposit of CMOS buffer oxide layer 40 ' and stress SiN layer 50 ' (referring to Fig. 3); 2) upper surface at nmos pass transistor 10 ' keeps stress SiN layer 50 ', does not carry out stress memory for PMOS transistor 20 ' and processes; Therefore need first the stress SiN layer 50 ' on the PMOS transistor 20 ' to be removed; Can be first the upper surface of nmos pass transistor 10 ' be protected with photoresist, the using plasma etching is removed the stress SiN layer 50 ' of PMOS transistor 20 ' upper surface, and described etching gas can adopt CF
4, CHF
3, O
2Composition gas with Ar; Behind the stress SiN layer 50 ' of removing PMOS transistor 20 ' upper surface, remove the photoresist (as shown in Figure 4) on nmos pass transistor 10 ' surface; 3) to carrying out annealing in process with the transistorized substrate of CMOS, the tensile stress in the stress SiN layer 51 ' of nmos pass transistor 10 ' upper surface is remembered in the conducting channel of nmos pass transistor 10 '; 4) then with wet etching the stress SiN layer 51 ' of described substrate top surface and the SiN layer 5 ' of lower surface and synchronously formation of CMOS transistor gate sidewall 30 ' are removed (referring to Fig. 5); 5) will remove again the synchronously SiO of formation of the buffer oxide layer 40 ' of substrate top surface of stress SiN layer 51 ' and SiN layer 5 ' and lower surface and CMOS transistor gate sidewall
2Layer 4 ' is removed, and obtains nmos pass transistor 10 ' with the CMOS transistor (referring to Fig. 6) of tensile stress.With the nmos pass transistor 100 ' of tensile stress, its conducting channel is owing to the stretching action of tensile stress, and the mobility of electronics can improve; When grid voltage changed, the reaction speed of nmos pass transistor 100 ' was faster, had put forward thus the reaction sensitivity of device.
SMT is widely used in the transistorized manufacturing process of CMOS.But possibility and degree that the CMOS transistor that uses SMT to process is affected by PID are higher, cause the stability of product and yield to be affected.
In U.S.'s application for a patent for invention prospectus that on September 10th, 2009, disclosed publication number was US20090224326A1; a kind of method of using protective circuit to reduce PID is disclosed; but obviously; increasing protective circuit can increase the area of whole integrated circuit, is not suitable with the development trend of integrated circuit miniaturization.Also exist some to reduce other trials that occur the PID phenomenon after SMT techniques in the prior art, as reduce the depositing temperature of stressed silicon nitride layers among the SMT, with the technique of deposit buffer oxide layer by LDSRO(Low Deposition Rate Silicon Rich Oxide, low rate deposition silicon rich oxide) changes SACVD(Sub-Atmospheric Chemical Vapor Deposition into, inferior aumospheric pressure cvd), or the etching bias voltage of change stressed silicon nitride layers etc., but abundant experimental results shows that the effect of above-mentioned way is all undesirable, and the probability that occurs PID through the CMOS transistor behind the SMT is still very high.
Summary of the invention
The purpose of this invention is to provide the transistorized stress memory processing method of a kind of CMOS and CMOS transistor, occur the probability of plasma-induced damage to be reduced in CMOS transistor after the SMT technique.
The invention provides the transistorized stress memory processing method of a kind of CMOS, comprising:
Provide one to be formed with the transistorized substrate of CMOS, the lower surface of described substrate has the silicon oxide layer corresponding with the transistorized gate lateral wall internal layer of described CMOS and is positioned at described silicon oxide layer lower surface and the silicon nitride layer corresponding with described gate lateral wall skin;
At the transistorized upper surface of described CMOS successively deposit buffer oxide layer and stressed silicon nitride layers;
If described CMOS transistor comprises nmos pass transistor and PMOS transistor, then remove the stressed silicon nitride layers of described PMOS transistor upper surface; Described substrate is annealed, the tensile stress of nmos pass transistor surface stress silicon nitride layer is remembered in the conducting channel of nmos pass transistor; Remove the stressed silicon nitride layers of described nmos pass transistor upper surface and remove described buffer oxide layer, the lower surface of described substrate remains with the silicon oxide layer corresponding with described gate lateral wall and silicon nitride layer;
If described CMOS transistor comprises nmos pass transistor, then described substrate is annealed, the tensile stress of nmos pass transistor surface stress silicon nitride layer is remembered in the conducting channel of nmos pass transistor; Remove stressed silicon nitride layers and the buffer oxide layer of described nmos pass transistor upper surface, the lower surface of described substrate remains with the silicon oxide layer corresponding with described gate lateral wall and silicon nitride layer.
Described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt dry etch process.
Described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt the processing step of first dry etching, rear wet etching.
Removing described nmos pass transistor upper surface stressed silicon nitride layers is specially: use dry etching to remove the stressed silicon nitride layers of the first thickness; Use wet etching to remove the stressed silicon nitride layers of the second thickness; Described the first thickness and the second thickness and be the gross thickness of described stressed silicon nitride layers, and the second thickness is less than the silicon nitride layer thickness of described substrate lower surface.
Removing described nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer is specially: use dry etching to remove the buffer oxide layer of described stressed silicon nitride layers and the 3rd thickness; Use wet etching to remove the buffer oxide layer of the 4th thickness; Described the 3rd thickness and the 4th thickness and be the gross thickness of described buffer oxide layer.
After to described substrate annealing and before removing nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer, also be included on the silicon nitride layer of described substrate lower surface armor coated; Then described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt wet-etching technology, and remove described protective layer behind wet-etching technology.
The etching gas of removing described stressed silicon nitride layers comprises: CF4, CHF3 and O2.
The etching gas of removing described buffer oxide layer comprises: CF4 and CHF3.
The etching liquid of removing described stressed silicon nitride layers comprises: phosphoric acid.
The etching liquid of removing described buffer oxide layer comprises: hydrofluoric acid.
The stressed silicon nitride layers of PMOS transistor upper surface is specially on the described removal substrate: apply photoresist in the stressed silicon nitride layers that covers CMOS transistor upper surface; Described photoresist is carried out exposure imaging to remove the photoresist of PMOS transistor upper surface; Dry etching is removed the stressed silicon nitride layers that exposes on the described PMOS transistor surface; Remove the photoresist on the stressed silicon nitride layers.
The present invention also provides a kind of CMOS transistor, and described CMOS transistor uses above-mentioned method to process and forms: the lower surface of described CMOS transistor place substrate has the silicon oxide layer corresponding with described gate lateral wall internal layer and the silicon nitride layer corresponding with described gate lateral wall skin; The conducting channel of nmos pass transistor is with tensile stress in the described CMOS transistor.
The transistorized stress memory processing method of CMOS of the present invention and CMOS transistor, by keeping silicon oxide layer and the silicon nitride layer of substrate lower surface, increased thickness of insulating layer, and then reduced the electric field that the accumulation plasma charge forms at substrate, reduce PID appears in device after the SMT PROCESS FOR TREATMENT possibility, carried stability and the yield of product; In addition, the method for reduction PID of the present invention does not increase extra manufacturing technology steps, and is therefore very good with existing technological process amalgamation when reducing the PID probability of occurrence, simple and saving cost.
Description of drawings
Fig. 1 is the device schematic cross-section of prior art applying plasma charge accumulation;
Fig. 2-Fig. 6 is that prior art is carried out the transistorized schematic cross-section of CMOS that SMT processes;
Fig. 7 is the schematic flow sheet of the transistorized stress memory processing method of CMOS of the present invention;
Fig. 8-Figure 10 is the transistorized stress memory processing method of CMOS of the present invention CMOS transistor schematic cross-section before removing stressed silicon nitride layers and buffer oxide layer;
Figure 11, Figure 12 are that the present invention removes the transistorized schematic cross-section of CMOS in the first implementation of stressed silicon nitride layers and buffer oxide layer;
Figure 13-Figure 17 is that the present invention removes the transistorized schematic cross-section of CMOS in the second implementation of stressed silicon nitride layers and buffer oxide layer;
Figure 18-Figure 20 is that the present invention removes the transistorized schematic cross-section of CMOS in the third implementation of stressed silicon nitride layers and buffer oxide layer;
Figure 21 is the schematic cross-section with the transistorized substrate of CMOS provided by the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments the embodiment of the invention is described in further detail.
The inventor is in realizing process of the present invention, do not solve problem from the angle that changes process means and technological parameter, but consider the formed electric field of accumulation plasma charge: E=Q/T(Q is the plasma charge amount of accumulating in the grid, T is the thickness of insulating barrier in the substrate), want to reduce E, will reduce Q and/or improve T, but, because Q is cumulative gradually in the device production process, be subjected to the prior art Restricted requirement, reduce Q and be difficult to realize, therefore can be from improving the angle set off in search solution of T.The inventor finds after the CMOS transistor has formed sidewall after the technological process to SMT carefully analyzes, at the corresponding formation SiO of substrate lower surface meeting
2Layer and SiN layer, they all belong to insulating barrier.Usually, the thickness of gate oxide is
Described SiO
2The thickness of layer and SiN layer can reach respectively
With
Therefore, can be in follow-up removal stressed silicon nitride layers and buffer oxide layer, with the SiO of substrate lower surface
2Layer and SiN layer remain, and improve T, to reduce the probability of occurrence of plasma-induced damage.
Based on the foregoing invention design, below in conjunction with accompanying drawing technical scheme of the present invention is introduced.
Embodiment one
The present embodiment provides the transistorized stress memory processing method of a kind of CMOS, as shown in Figure 7, comprising:
S101 provides one to be formed with the transistorized substrate of CMOS.
Each CMOS transistor comprises grid, source electrode, drain electrode, conducting channel, gate oxide and gate lateral wall, and the internal layer of described gate lateral wall is silicon oxide layer, and skin is silicon nitride layer.Wherein, source electrode, drain electrode and conducting channel are arranged in the trap of described substrate and source/drain transoid, and (technical scheme of the present invention does not relate to, all simplify in the accompanying drawings not shown) and be between source electrode and the drain electrode, gate oxide is positioned at the substrate top surface corresponding with described conducting channel position, grid (being generally polysilicon) is positioned at the upper surface of described gate oxide, described gate lateral wall surrounds the side of grid and gate oxide, can adopt sandwich construction, be that silicon oxide layer, skin are silicon nitride layer such as internal layer.The lower surface of described substrate has the silicon oxide layer corresponding with the transistorized gate lateral wall internal layer of described CMOS and is positioned at described silicon oxide layer lower surface and the silicon nitride layer (referring to Fig. 8) corresponding with described gate lateral wall skin.
When forming gate lateral wall 300, can form silicon oxide layer 40 and silicon nitride layer 50 by corresponding lower surface at substrate 10.Afterwards, inject the transistorized source electrode of formation CMOS and drain electrode (not shown) in the both sides of gate lateral wall 300 by foreign ion.
S102 is in the transistorized upper surface of described CMOS successively deposit buffer oxide layer and stressed silicon nitride layers (referring to Fig. 9).
When the transistorized upper surface of described CMOS forms buffer oxide layer 80, can adopt LPCVD(Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition), also can adopt PECVD.Reacting gas can be SIH
4, O
2And He, temperature is 400-700 ℃, buffer oxide layer 80 thickness that form at CMOS transistor upper surface are
(the excessively thin effect that does not have buffering stress, the blocked up stress that can make again all is cushioned), the reaction time is different and different with buffer oxide layer 80 thickness, is approximately dozens of minutes.
When described buffer oxide layer 80 forms stressed silicon nitride layers 90, usually adopt PECVD, deposit stressed silicon nitride layers cross section after 90s is as shown in Figure 9.Reacting gas can be SIH
4, NH
3And N
2, temperature is 300-600 ℃, stressed silicon nitride layers 90 thickness that form at buffer oxide layer 80 are
(excessively thinly do not provide enough stress, blocked up meeting makes the stress of cmos device excessive), the reaction time is different and different with stressed silicon nitride layers 90 thickness, is approximately dozens of minutes.In the present invention, use has the stressed silicon nitride layers 90 of tensile stress, the stress types of stressed silicon nitride layers 90 (being compression and tensile stress) can realize control by the growth conditions of proof stress silicon nitride layer, described growth conditions comprises gas flow, temperature, gas componant proportioning etc., belong to prior art, the present invention does not repeat them here.
S103 if described CMOS transistor comprises nmos pass transistor and PMOS transistor, then removes the stressed silicon nitride layers (referring to Figure 10) of described PMOS transistor upper surface; If described CMOS transistor comprises nmos pass transistor, direct execution in step S104 then.
The stressed silicon nitride layers 90 of removing PMOS transistor 222 upper surfaces in the CMOS transistor is specifically as follows:
Apply photoresist in the stressed silicon nitride layers 90 that covers CMOS transistor upper surface;
Described photoresist is carried out exposure imaging to remove the photoresist of PMOS transistor 222 upper surfaces;
The upper stressed silicon nitride layers 90 that exposes in dry etching PMOS transistor 222 surfaces;
Remove the photoresist on the stressed silicon nitride layers 900.
S104 anneals to described substrate, and the tensile stress of nmos pass transistor surface stress silicon nitride layer is remembered in the conducting channel of nmos pass transistor.
The temperature of annealing can be used various method for annealing between 600 ~ 800 ℃, for example use Halogen lamp LED or tungsten lamp.Tensile stress in the stressed silicon nitride layers 900 after the annealing can be remembered in the conducting channel of nmos pass transistor 111.
S105 removes stressed silicon nitride layers and the described buffer oxide layer of described nmos pass transistor upper surface, and the lower surface of described substrate remains with the silicon oxide layer corresponding with described gate lateral wall and silicon nitride layer (referring to Figure 12).
Prior art is to adopt wet etching when removing stressed silicon nitride layers and buffer oxide layer.At first, the etching liquid that use contains phosphoric acid erodes the silicon nitride layer of stressed silicon nitride layers and substrate lower surface, even the silicon nitride layer thickness of stressed silicon nitride layers and substrate lower surface is different, but because etching liquid can stop at the silicon oxide layer surface to the high selectivity (can adjust etching liquid to the etching selection ratio of different materials by the composition ratio of etching liquid) of etching material behind the complete silicon nitride of etching.Then, use the etching liquid contain hydrofluoric acid that the silicon oxide layer of buffer oxide layer and lower surface is eroded, stay structure as shown in Figure 6.
But in the present invention, need in the stressed silicon nitride layers 900 and buffer oxide layer 80 of removing nmos pass transistor 111 upper surfaces, keep silicon oxide layer 40 and the silicon nitride layer 50 of substrate 10 lower surfaces.For this reason, the invention provides following three kinds of implementations:
1) adopts dry etch process.
When the stressed silicon nitride layers 900 of etching N MOS transistor 111 upper surfaces, can select CF
4, CHF
3And O
2As etching gas, also can in etching gas, add Ar as gas carrier, with dilution etching gas, mitigation etching reaction, make reaction more even; Reaction temperature is room temperature; Time decides according to the thickness of stressed silicon nitride layers 900, is approximately dozens of minutes (referring to Figure 11).
When etching buffer oxide layer 80, can select CF
4And CHF
3As etching gas, also can in etching gas, add Ar as gas carrier, with dilution etching gas, mitigation etching reaction, make reaction more even; Reaction temperature is room temperature; Time decides according to the thickness of buffer oxide layer 80, is approximately dozens of minutes.
When etching stressed silicon nitride layers 900 and buffer oxide layer 80, since the lower surface of substrate 10 be by vacuum suction on a pallet, the silicon oxide layer 40 of substrate 10 lower surfaces does not contact with plasma with silicon nitride layer 50, therefore, can be not influential to silicon oxide layer 40 and the silicon nitride layer 50 of substrate lower surface.
2) adopt the processing step of first dry etching, rear wet etching.
I. use dry etching to remove the stressed silicon nitride layers of the first thickness (referring to Figure 13);
Re-use wet etching and remove the stressed silicon nitride layers 91(of the second thickness referring to Figure 14); Described the first thickness and the second thickness and be the gross thickness of stressed silicon nitride layers 900, and the second thickness is less than silicon nitride layer 50 thickness of described substrate 10 lower surfaces.Comprise phosphoric acid in the etching liquid of etching stressed silicon nitride layers 91.
After stressed silicon nitride layers 900 is removed fully, can use wet etching also can adopt dry etching that buffer oxide layer 80 is removed.If the employing wet etching comprises hydrofluoric acid in the etching liquid of etching buffer oxide layer 80.Although the silicon nitride layer 50 of substrate 10 lower surfaces is etched away certain thickness when the stressed silicon nitride layers 91 of wet etching the second thickness; but the silicon nitride layer that remains 51 is when wet etching buffer oxide layer 80; still can form good protection to silicon oxide layer 40; last cross section is referring to Figure 15; the buffer oxide layer 80 of CMOS transistor upper surface and stressed silicon nitride layers 900 be complete disposing all, and substrate 10 lower surfaces also remain with silicon oxide layer 40 and silicon nitride layer 51.
Ii. use dry etching to remove the buffer oxide layer (referring to Figure 16) of described stressed silicon nitride layers 900 and the 3rd thickness;
Re-use wet etching and remove the buffer oxide layer 81 of the 4th thickness; Described the 3rd thickness and the 4th thickness and be the gross thickness of buffer oxide layer 80.
Owing to first stressed silicon nitride layers 900 is all removed, therefore, when the following adopted wet etching is removed buffer oxide layer 81, because silicon nitride layer 50 can not corrode by hydrofluoric acid, therefore can keep complete silicon oxide layer 40 and silicon nitride layer 50(referring to Figure 17 at substrate 10 lower surfaces).
Certainly, by above-mentioned disclosed technical scheme, those skilled in the art can also expect dry etching and wet etching are carried out repeatedly combined crosswise easily, can realize purpose of the present invention equally, because the scheme that combination derives is too much, the present invention does not enumerate one by one at this.
3) adopt wet-etching technology.
In this case, need to be at armor coated 100(on 50 layers of the silicon nitride layers of substrate 10 lower surfaces referring to Figure 18 before etching), protective layer 100 can be resisted the corrosion of the etching liquid that contains phosphoric acid.Protective layer 100 can be organic coating (such as photoresist etc.), also can be inorganic coating (such as amorphous carbon coating etc.).Afterwards, successively with stressed silicon nitride layers 900, buffer oxide layer 80 erosion removals (referring to Figure 19).Stressed silicon nitride layers 900 and buffer oxide layer are after 80s removing, and remove described protective layer 100(referring to Figure 20).For example for photoresist, can use sulfuric acid, H
2O
2Clean, for amorphous carbon coating, can pass into and contain O
2Plasma, at high temperature with the amorphous carbon coating oxidation removal, the removal means of protective layer 100 are known technology, the present invention repeats no more this.
Certainly, according to above-mentioned three kinds of implementations provided by the invention, those skilled in the art can be easy to these three kinds of implementations are made up, and derive multiple implementation, and the present invention does not introduce one by one to this.
Show according to the resulting series of experiments data of above-mentioned implementation, adopt the method for the present embodiment that the CMOS transistor is carried out the stress memory processing, the effect that reduces the PID probability of occurrence is very good.
The transistorized stress memory processing method of CMOS of the present invention, by keeping silicon oxide layer and the silicon nitride layer of substrate lower surface, increased thickness of insulating layer T, and then reduced the electric field E that the accumulation plasma charge forms at substrate, reduce PID appears in device after the stress memory PROCESS FOR TREATMENT possibility, carried stability and the yield of product; In addition, the method for the present embodiment does not increase extra manufacturing technology steps, and therefore, the method for the present embodiment is when reducing the PID probability of occurrence, and is very good with existing technological process amalgamation, simple and saving cost.
Embodiment two
The present invention also provides a kind of CMOS transistor, as shown in figure 21.
Described CMOS transistor comprises grid, source electrode, drain electrode, conducting channel (not shown), gate oxide 22 and gate lateral wall 33, the internal layer of described gate lateral wall 33 is silicon oxide layer, skin is silicon nitride layer, and the lower surface of described CMOS transistor place substrate 11 has silicon oxide layer 44 and the silicon nitride layer 55 corresponding with described gate lateral wall 33;
The conducting channel of nmos pass transistor 66 is with tensile stress in the described CMOS transistor, and the conducting channel of PMOS transistor 77 does not have stress.
CMOS transistor of the present invention, by keeping silicon oxide layer and the silicon nitride layer of substrate lower surface, increased thickness of insulating layer T, and then reduced the electric field E that the accumulation plasma charge forms at substrate, reduce PID appears in the CMOS transistor after the stress memory PROCESS FOR TREATMENT possibility, improved the transistorized job stability of CMOS and yield; In addition, the present embodiment in manufacture process, do not increase extra manufacturing technology steps with the transistorized substrate of CMOS, therefore, the present embodiment with the transistorized substrate of CMOS when reducing PID, very good with existing technological process amalgamation, simple and saving cost.
Because embodiment two is more to the similar content of embodiment one, that therefore describes is simpler, and relevant part sees also embodiment one.
Need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operating space, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
The above is preferred embodiment of the present invention only, is not for limiting protection scope of the present invention.All any modifications of doing within the spirit and principles in the present invention, be equal to replacement, improvement etc., all be included in protection scope of the present invention.
Claims (12)
1. the transistorized stress memory processing method of CMOS is characterized in that, comprising:
Provide one to be formed with the transistorized substrate of CMOS, the lower surface of described substrate has the silicon oxide layer corresponding with the transistorized gate lateral wall internal layer of described CMOS and is positioned at described silicon oxide layer lower surface and the silicon nitride layer corresponding with described gate lateral wall skin;
At the transistorized upper surface of described CMOS successively deposit buffer oxide layer and stressed silicon nitride layers;
Described CMOS transistor comprises nmos pass transistor and PMOS transistor, then removes the stressed silicon nitride layers of described PMOS transistor upper surface; Described substrate is annealed, the tensile stress of nmos pass transistor surface stress silicon nitride layer is remembered in the conducting channel of nmos pass transistor; Remove the stressed silicon nitride layers of described nmos pass transistor upper surface and remove described buffer oxide layer, the lower surface of described substrate remains with the silicon oxide layer corresponding with described gate lateral wall and silicon nitride layer.
2. the method for claim 1 is characterized in that, described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt dry etch process.
3. the method for claim 1 is characterized in that, described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt the processing step of first dry etching, rear wet etching.
4. method as claimed in claim 3 is characterized in that, removes described nmos pass transistor upper surface stressed silicon nitride layers and is specially:
Use dry etching to remove the stressed silicon nitride layers of the first thickness;
Use wet etching to remove the stressed silicon nitride layers of the second thickness; Described the first thickness and the second thickness and be the gross thickness of described stressed silicon nitride layers, and the second thickness is less than the silicon nitride layer thickness of described substrate lower surface.
5. method as claimed in claim 3 is characterized in that, removes described nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer and is specially:
Use dry etching to remove the buffer oxide layer of described stressed silicon nitride layers and the 3rd thickness;
Use wet etching to remove the buffer oxide layer of the 4th thickness; Described the 3rd thickness and the 4th thickness and be the gross thickness of described buffer oxide layer.
6. the method for claim 1, it is characterized in that, after to described substrate annealing and before removing nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer, also be included on the silicon nitride layer of described substrate lower surface armor coated;
Then described removal nmos pass transistor upper surface stressed silicon nitride layers and described buffer oxide layer adopt wet-etching technology, and remove described protective layer behind wet-etching technology.
7. such as each described method of claim 2-5, it is characterized in that, the etching gas of removing described stressed silicon nitride layers comprises: CF
4, CHF
3And O
2
8. such as claim 2 or 5 described methods, it is characterized in that, the etching gas of removing described buffer oxide layer comprises: CF
4And CHF
3
9. such as claim 4 or 6 described methods, it is characterized in that, the etching liquid of removing described stressed silicon nitride layers comprises: phosphoric acid.
10. such as claim 5 or 6 described methods, it is characterized in that, the etching liquid of removing described buffer oxide layer comprises: hydrofluoric acid.
11. such as each described method of claim 1-6, it is characterized in that, the stressed silicon nitride layers of PMOS transistor upper surface is specially on the described removal substrate:
Apply photoresist in the stressed silicon nitride layers that covers CMOS transistor upper surface;
Described photoresist is carried out exposure imaging to remove the photoresist of PMOS transistor upper surface;
Dry etching is removed the stressed silicon nitride layers that exposes on the described PMOS transistor surface;
Remove the photoresist on the stressed silicon nitride layers.
12. a CMOS transistor is characterized in that, described CMOS transistor use is processed such as each described method of claim 1-11 and is formed:
The lower surface of described CMOS transistor place substrate has the silicon oxide layer corresponding with described gate lateral wall internal layer and the silicon nitride layer corresponding with described gate lateral wall skin;
The conducting channel of nmos pass transistor is with tensile stress in the described CMOS transistor.
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| CN111477549B (en) * | 2020-04-26 | 2023-06-13 | 上海华力集成电路制造有限公司 | Method for manufacturing semiconductor device by stress memorization technology |
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| CN1983564A (en) * | 2005-12-06 | 2007-06-20 | 联华电子股份有限公司 | Method for fabricating strained-silicon cmos transistors |
| CN101026162A (en) * | 2006-02-24 | 2007-08-29 | 台湾积体电路制造股份有限公司 | Semiconductor device and its making method |
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