CN102097319B - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN102097319B CN102097319B CN2009102011828A CN200910201182A CN102097319B CN 102097319 B CN102097319 B CN 102097319B CN 2009102011828 A CN2009102011828 A CN 2009102011828A CN 200910201182 A CN200910201182 A CN 200910201182A CN 102097319 B CN102097319 B CN 102097319B
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- oxide layer
- cushion oxide
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Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises the following steps of: providing a semiconductor substrate, wherein the semiconductor substrate is N-type doped; forming a grid structure on the semiconductor substrate; performing ion implantation to form a light doped source region and a light doped drain region on the semiconductor substrate, wherein the implantation ions of the light doped source region and the light doped drain region are boron-containing ions; forming a gasket oxide layer on the semiconductor substrate; and performing plasma treatment on the gasket oxide layer. The plasma treatment can reduce the hydrogen content of the gasket oxide layer, and can also reduce diffusion of the doped ions of the light doped source region and the light doped drain region in subsequent annealing treatment to the gasket oxide layer so as to avoid over loss of the excessive ions.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to the manufacture method of semiconductor device.
Background technology
Integrated circuit is the IC continuous advancement in technology, and the component number that is integrated on the same chip has evolved to present millions of from tens initial hundreds ofs.Performance and the complexity of IC were far from originally and can imagine at present.For the requirement of satisfying complexity and current densities (that is: be integrated into the number of devices of confirming in the zone), minimum characteristic size, just " how much live widths " of known device is more and more littler along with the innovation of technology.Nowadays, the minimum feature of semiconductor device is less than 65 nanometers.
Along with constantly reducing of semiconductor device minimum feature, highlight day by day such as short-channel effects such as thermoelectronic effects, become the key factor that influences performance of semiconductor device.Therefore, in order to reduce the influence of said short-channel effect, light dope source region and lightly doped drain are introduced in the transistor arrangement, and be corresponding, and the side wall construction that is used for isolating heavy-doped source/drain region and grid is introduced in transistor simultaneously.Common, said side wall construction adopts the composite construction of cushion oxide layer and silicon nitride to form, and cushion oxide layer is as the etching stop layer of dry etching silicon nitride.
Application number is the formation method that the U.S. Patent application file of US11446912 discloses side wall construction in a kind of semiconductor device; Said side wall construction adopts the composite construction of cushion oxide layer and silicon nitride to form, and said cushion oxide layer can adopt low-pressure chemical vapor phase deposition (LPCVD), plasma chemical vapor deposition (PECVD) or inferior normal pressure chemical vapor deposition (SACVD) to form.Along with after semiconductor technology gets into 65 nanometer technologies, the integrated level of semiconductor device improves constantly, and the side wall construction size of MOS transistor is also constantly dwindled.In the prior art, for better step coverage effect and reduce heat budget, SACVD has replaced step and has covered relatively poor relatively LPCVD and PECVD, becomes the main flow manufacture craft of cushion oxide layer.Said normal pressure chemical vapor deposition forms the cushion oxide layer manufacture craft and comprise: reaction pressure is between 10torr to 600torr; Utilize ozone and silicon tetraethyl methane (TEOS) to form cushion oxide layer, again through of the cushion oxide layer densification of follow-up high annealing with formation as pre-reaction material.
Yet the reaction temperature that SACVD forms silica is lower, and hydrogen atom content will be far above the cushion oxide layer of the LPCVD formation of adopting higher reaction temperatures in the cushion oxide layer of formation.The hydrogen atom of high-load in the said cushion oxide layer both can influence the density of cushion oxide layer, also can produce defective (interface trapped charge) in silicon-silicon oxide interface, made and had reduced insulation property by the second-rate of said cushion oxide layer; Simultaneously, for PMOS transistor or flash memory transistor, said side wall construction below is light dope source region and lightly doped drain, and is common, and said light dope source region and lightly doped drain form through injecting the boron ion or fluoridizing inferior boron ion.The boron ion that hydrogen atom in the said cushion oxide layer can quicken in light dope source region and the lightly doped drain spreads in cushion oxide layer, causes light dope source region and the marked change of lightly doped drain impurity concentration, influences junction depth and causes device performance to descend.
Therefore, need to improve the manufacture craft of semiconductor device.
Summary of the invention
The problem that the present invention solves has provided a kind of manufacture method of semiconductor device; The manufacture method of said semiconductor device has reduced the hydrogen content in the semiconductor device cushion oxide layer, has also reduced the impurity loss in light dope source region and lightly doped drain in the Semiconductor substrate simultaneously.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, and said Semiconductor substrate is mixed for the N type; On said Semiconductor substrate, form grid structure; Carry out ion and inject, on said Semiconductor substrate, form light dope source region and lightly doped drain, the injection ion of said light dope source region and lightly doped drain is the boracic element ion; On said Semiconductor substrate, form cushion oxide layer; Said cushion oxide layer is carried out Cement Composite Treated by Plasma.
Optional, said cushion oxide layer adopts ozone and silicon tetraethyl methane (TEOS) reaction to form.
Optional, said cushion oxide layer adopts time normal pressure chemical vapor deposition to form.
Optional, the thickness of said cushion oxide layer is 50 to 200 dusts.
Optional, the condition of said Cement Composite Treated by Plasma is: reacting gas comprises N
2, O
2, He, Ne or O
3Reaction temperature is 400 degrees centigrade to 480 degrees centigrade; The radio-frequency power of reaction cavity is 200 to 1000 watts.
Optional, also be included in to form on the cushion oxide layer and stop dielectric layer, the said dielectric layer that stops is silicon nitride, silicon oxynitride or silica.
Optional, the dielectric layer using plasma chemical gas-phase deposition enhanced that stops on the said cushion oxide layer forms.
Optional, the reaction cavity that stops dielectric layer on the reaction cavity of said cushion oxide layer, the reaction cavity of Cement Composite Treated by Plasma and the cushion oxide layer is same cavity.
Optional, said grid structure comprises gate dielectric layer and gate electrode.
Optional, said grid structure comprises dielectric layer and control gate between gate dielectric layer, floating boom, grid.
Optional, the manufacture method of said semiconductor device also comprises successively: ion injects, and forms heavy doping source region and heavy doping drain region; Said Semiconductor substrate is carried out annealing in process.
Compared with prior art, the present invention has the following advantages:
1. Semiconductor substrate is carried out Cement Composite Treated by Plasma; Under the catalytic action of boron ion; Hydrogen atom on the said Semiconductor substrate in the cushion oxide layer and oxygen atom form hydrone and from said cushion oxide layer, escape away; Hydrogen atom content in the cushion oxide layer reduces greatly, has improved the quality of cushion oxide layer;
2. said Cement Composite Treated by Plasma reduces the hydrogen atom content in the cushion oxide layer; In source region and the processing of drain region subsequent anneal; Said lower hydrogen atom content can reduce in the Semiconductor substrate doped with boron ion and avoid the excessive loss of dopant ion in the Semiconductor substrate to the diffusion of cushion oxide layer;
3. stop that the reaction cavity of dielectric layer is same reaction cavity on the reaction cavity of the reaction cavity of said Cement Composite Treated by Plasma and formation cushion oxide layer and the formation cushion oxide layer; Need said Semiconductor substrate not taken out from reaction cavity, it is integrated to be beneficial to technology.
Description of drawings
Fig. 1 is the process chart of the manufacturing method of semiconductor device of one embodiment of the invention.
Fig. 2 to Fig. 6 is the cross-sectional view of the manufacturing method of semiconductor device of one embodiment of the invention.
Embodiment
In the prior art, in the manufacture craft of PMOS transistor and flash memory transistor side wall construction, use ozone and silicon tetraethyl methane (TEOS) usually, adopt time normal pressure chemical vapor deposition to form cushion oxide layer as pre-reaction material.Because the reaction temperature of said normal pressure chemical vapor deposition is lower, hydrogen atom content will be far above the silica that adopts high-temperature low-pressure chemical vapor deposition (LPCVD) to form in the said cushion oxide layer.The existence of said hydrogen atom both can influence the density of cushion oxide layer, also can produce defective (interface trapped charge) in silicon-silicon oxide interface, made and reduced the cushion oxide layer insulation property by the second-rate of said cushion oxide layer.Simultaneously, for semiconductor device such as PMOS transistor and flash memory transistor, said side wall construction below is light dope source region and lightly doped drain, and is common, and said light dope source region and lightly doped drain form through injecting the boracic element ion.The boron ion that mixes in light dope source region and the lightly doped drain when hydrogen atom in the said cushion oxide layer can quicken the subsequent anneal processing spreads in cushion oxide layer; Cause the loss of said light dope source region and lightly doped drain impurity, cause said performance of semiconductor device to descend.
Yet, under the effect of boron ion, with OH-form (hydrogen atom that OH) is present in the cushion oxide layer can be participated in following chemical reaction:
H-O-Si≡+B
+→H-B-O-Si≡
Wherein, the chemical activation energy of said chemical reaction is merely 0.87eV.Through the said Semiconductor substrate that is formed with cushion oxide layer is carried out Cement Composite Treated by Plasma; The hydroxyl that comprises hydrogen atom obtains enough activation energies and reacts with the boron ion; Form the structure of H-B-O; Unreacted hydroxyl continues reaction in hydrogen atom in the said H-B-O structure and the cushion oxide layer, forms hydrone, and from cushion oxide layer, escapes away.Said Cement Composite Treated by Plasma has reduced the hydrogen atom content in the cushion oxide layer, has improved the insulation property of cushion oxide layer; Further, the boron ion of light dope source region and lightly doped drain spread in cushion oxide layer when said cushion oxide layer than low hydrogen content can reduce the subsequent anneal processing, thereby reduced the impurity loss.
Based on above-mentioned chemical principle; The inventor provides following technical proposals; Utilize the boron ion that has injected in light dope source region and the lightly doped drain to carry out catalytic reaction; And adopt the reaction cavity that forms cushion oxide layer to carry out the Cement Composite Treated by Plasma of original position, can when not reducing processing compatibility, improve the quality of cushion oxide layer.
Fig. 1 is the process chart of the manufacturing method of semiconductor device of one embodiment of the invention.Comprise: execution in step S202 provides Semiconductor substrate; Execution in step S204 forms grid structure on said Semiconductor substrate; Execution in step S206, ion injects, and on said Semiconductor substrate, forms light dope source region and lightly doped drain; Execution in step S208 forms cushion oxide layer on said Semiconductor substrate and grid structure; Execution in step S210 carries out Cement Composite Treated by Plasma to said cushion oxide layer; Execution in step S212, formation stops dielectric layer on said cushion oxide layer; Execution in step S214, the said cushion oxide layer of etching with stop dielectric layer, form side wall construction.
Fig. 2 to Fig. 6 is the cross-sectional view of the manufacturing method of semiconductor device of one embodiment of the invention.
As shown in Figure 2, Semiconductor substrate 201 is provided, in specific embodiment, the silicon substrate that said Semiconductor substrate 201 is mixed for the N type, the injection ion that said N type mixes is phosphonium ion, arsenic ion or other N type ions.Afterwards, on said Semiconductor substrate 201, form gate dielectric layer 205, in one embodiment of the invention, the present invention is used to form the PMOS transistor, the silicon oxide layer that said gate dielectric layer 205 forms for thermal oxidation; Afterwards, on said gate dielectric layer 205, form polysilicon layer, said polysilicon layer is graphical, form grid structure 207; In another embodiment of the present invention; The present invention is used to form flash memory transistor; Accordingly; Said gate dielectric layer 205 is the tunnel oxide of flash memory transistor, and the grid structure of 207 on the gate dielectric layer 205 for piling up, the said grid structure that piles up comprises from bottom to top successively: dielectric layer and control gate between the grid of floating boom, isolation floating boom and control gate.Then; Said Semiconductor substrate 201 is carried out ion to be injected; In said Semiconductor substrate 201, forming light dope source region 211 and lightly doped drain 213, mixes for the P type with lightly doped drain 213 in said light dope source region 211, and said injection ion is the boracic element ion.In specific embodiment, said boracic element ion is the boron ion or fluoridizes inferior boron ion that the implantation dosage of said boracic element ion is 5 * 10
14To 2 * 10
15Ion/square centimeter injects energy and is 1 to 3KeV; In the preferred embodiment, adopt and to fluoridize inferior boron ion and inject, the implantation dosage of fluoridizing inferior boron ion is 5 * 10
14Ion/square centimeter, the injection energy is 1KeV.
As shown in Figure 3, on said Semiconductor substrate 201 and grid structure 207, form cushion oxide layer 215.Said cushion oxide layer 215 is to adopt ozone and silicon tetraethyl methane (TEOS) as pre-reaction material; Utilize time normal pressure chemical vapor deposition (SACVD) to form, the hydrogen atom content of said cushion oxide layer 215 will be higher than the oxide layer that adopts low-pressure chemical vapor phase deposition (LPCVD) to form.In specific embodiment, the reaction temperature of said SACVD is 450 to 550 degrees centigrade, and cushion oxide layer 215 thickness are 50 to 200 dusts; In a preferred embodiment, the reaction temperature of SACVD is 540 degrees centigrade, and the thickness of cushion oxide layer 215 is 100 dusts.Said cushion oxide layer 215 belows are the light dope source region 211 of grid structure 207, the doping of P type and the lightly doped drain 213 that the P type mixes.
Afterwards, the cushion oxide layer 215 that said method generates is carried out Cement Composite Treated by Plasma, the reaction cavity that the reaction cavity of said Cement Composite Treated by Plasma and SACVD form cushion oxide layer 215 is same cavity.In specific embodiment, the reaction condition of said Cement Composite Treated by Plasma is: reacting gas is N
2, O
2, He, Ne or O
3, reaction temperature is 400 degrees centigrade to 480 degrees centigrade, and reaction pressure is 1 to 7torr, and the radio-frequency power of reaction cavity is 200 to 1000 watts, and the reaction time is 20 to 50 seconds; In the preferred embodiment, reacting gas is N
2, reaction temperature is 480 degrees centigrade, and reaction pressure is 2torr, and the radio-frequency power of reaction cavity is 500 watts, and the reaction time is 25 seconds.Said Cement Composite Treated by Plasma can make the hydroxyl in the cushion oxide layer 215 obtain enough activation energies and react with the boron ion; Form the structure of H-B-O; Unreacted hydroxyl reaction in hydrogen atom in the said H-B-O structure and the cushion oxide layer; Form hydrone, and from cushion oxide layer, escape away.Simultaneously, the annealing temperature after the temperature of said Cement Composite Treated by Plasma is injected far below ion can not cause the boron ion excess diffusion in cushion oxide layer 215 in light dope source region 211 and the lightly doped drain 213, so the impurity loss is very little.
As shown in Figure 4, on cushion oxide layer 215, continue to form to stop dielectric layer 217, in specific embodiment, the said composite material that stops dielectric layer 217 for silicon nitride, silicon oxynitride, silica or three.The said dielectric layer 217 that stops forms through plasma chemical vapor deposition; The reaction cavity of said plasma chemical vapor deposition is identical with the reaction cavity of the Cement Composite Treated by Plasma of said cushion oxide layer 215; Said Semiconductor substrate 201 need not taken out from reaction cavity, and it is integrated to help technology.In specific embodiment; The reaction temperature of said plasma chemical vapor deposition is 400 to 550 degrees centigrade; In the preferred embodiment, the reaction temperature of plasma chemical vapor deposition is 480 degrees centigrade, and is identical with the temperature of cushion oxide layer 215 Cement Composite Treated by Plasma; The temperature-fall period that do not heat up in two process steps has reduced the process time and has reduced the heat budget of technology; In specific embodiment, the thickness that stops dielectric layer 217 is 200 to 1000 dusts, and in the preferred embodiment, the thickness that stops dielectric layer 217 is 500 dusts.The Cement Composite Treated by Plasma of said cushion oxide layer 215 must stop that dielectric layer 217 carries out before forming; Otherwise; In the process of Cement Composite Treated by Plasma, stop that the hydrogen atom in the dielectric layer 217 meeting obstruction cushion oxide layer 215 is outwards escaped, the hydrogen atom content of cushion oxide layer 215 can't reduce.
As shown in Figure 5, said dielectric layer 217 and the cushion oxide layer 215 of stopping of etching forms by the compound side wall construction that stops that dielectric layer 217 and cushion oxide layer 215 are formed.Said compound side wall construction and grid structure 207 are as the mask of follow-up heavy doping source region and the injection of heavy doping drain region ion.
As shown in Figure 6, Semiconductor substrate 201 is carried out ion inject, form heavy doping source region 223 and heavy doping drain region 225.In specific embodiment, mix for the P type with lightly doped drain 225 in said heavy doping source region 223, and the material that said ion injects is the boron ion or fluoridizes inferior boron ion.Afterwards, carry out annealing in process to activate dopant ion and to recover the lattice damage of Semiconductor substrate 201.In specific embodiment, said annealing in process adopts short annealing to handle (RTA), and peak temperature is 1000 to 1100 degrees centigrade.Because the annealing temperature of said annealing in process is higher; The boron ion of light dope source region 211 and lightly doped drain 213 is easy to cushion oxide layer 215 diffusions; If cushion oxide layer 215 is without Cement Composite Treated by Plasma; Hydrogen atom in the then said cushion oxide layer 215 can order about the boron ion and in cushion oxide layer 215, spread, and causes said light dope source region 211 and lightly doped drain 213 impurity excessive loss.
After above-mentioned processing step enforcement, fabricate forms.Common, the quality of cushion oxide layer can be through wet etching speed (WER) check.The wet etching speed of said cushion oxide layer is low more, and compactness is good more.The inventor compares experimental verification, adopts with a kind of corrosive liquid, and to carrying out wet etching without the cushion oxide layer of Cement Composite Treated by Plasma with through the cushion oxide layer of Cement Composite Treated by Plasma, in specific embodiment, said corrosive liquid is a hydrofluoric acid.Test result is: without the wet etching speed of the cushion oxide layer of Cement Composite Treated by Plasma be 85 dusts/minute; Through the wet etching speed of the cushion oxide layer of Cement Composite Treated by Plasma be 65 dusts/minute, the wet etching speed ratio of said cushion oxide layer through Cement Composite Treated by Plasma will hang down 24% without the wet etching speed of the cushion oxide layer of Cement Composite Treated by Plasma.Said test result shows that cushion oxide layer is after the process Cement Composite Treated by Plasma, and the hydrogen atom content in the said cushion oxide layer reduces, and the density of cushion oxide layer improves.
For the Semiconductor substrate of mixing, the dopant ion concentration of said Semiconductor substrate can characterize through square resistance.The square resistance of the Semiconductor substrate of said doping is more little, and dopant ion concentration is high more.The inventor compares experimental verification, has tested respectively without the light dope source region of the Semiconductor substrate of Cement Composite Treated by Plasma and square resistance through the light dope source region of the Semiconductor substrate of Cement Composite Treated by Plasma.Test result is that the square resistance ratio in light dope source region is without the square resistance low 20% of the Semiconductor substrate of Cement Composite Treated by Plasma on the said process Semiconductor substrate of Cement Composite Treated by Plasma.Said test result shows that through after the Cement Composite Treated by Plasma, the light dope source region on the said Semiconductor substrate or the square resistance of lightly doped drain reduce, and the impurity loss is less.
Should be appreciated that above-mentioned specific embodiment only is exemplary, those skilled in the art can make various modifications and corrigendum under the situation of the spirit and scope of the present invention that do not deviate from the application and accompanying claims and limited.
Claims (10)
1. the manufacture method of a semiconductor device comprises: Semiconductor substrate is provided, and said Semiconductor substrate is that the N type mixes; On said Semiconductor substrate, form grid structure; Carry out ion and inject, on said Semiconductor substrate, form light dope source region and lightly doped drain, the injection ion of said light dope source region and lightly doped drain is the boracic element ion; On said Semiconductor substrate, form cushion oxide layer; Said cushion oxide layer is carried out Cement Composite Treated by Plasma, and wherein, the condition of said Cement Composite Treated by Plasma is: reacting gas comprises N
2, O
2, He, Ne or O
3Reaction temperature is 400 degrees centigrade to 480 degrees centigrade; The radio-frequency power of reaction cavity is 200 to 1000 watts.
2. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, said cushion oxide layer adopts ozone and silicon tetraethyl methane (TEOS) reaction to form.
3. manufacturing method of semiconductor device as claimed in claim 2 is characterized in that, said cushion oxide layer adopts time normal pressure chemical vapor deposition to form.
4. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the thickness of said cushion oxide layer is 50 to 200 dusts.
5. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, also is included in to form on the cushion oxide layer to stop dielectric layer, and the said dielectric layer that stops is silicon nitride, silicon oxynitride or silica.
6. manufacturing method of semiconductor device as claimed in claim 5 is characterized in that, the dielectric layer using plasma chemical gas-phase deposition enhanced that stops on the said cushion oxide layer forms.
7. manufacturing method of semiconductor device as claimed in claim 6 is characterized in that, the reaction cavity that stops dielectric layer on the reaction cavity of said cushion oxide layer, the reaction cavity of Cement Composite Treated by Plasma and the cushion oxide layer is same reaction cavity.
8. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, said grid structure comprises gate dielectric layer and gate dielectric layer and gate electrode.
9. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, said grid structure comprises dielectric layer and control gate between gate dielectric layer, floating boom, grid.
10. manufacturing method of semiconductor device as claimed in claim 1 is characterized in that, the manufacture method of said semiconductor device also comprises successively: ion injects, and forms heavy doping source region and heavy doping drain region; Said Semiconductor substrate is carried out annealing in process.
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| CN105590839B (en) * | 2016-03-22 | 2018-09-14 | 安徽三安光电有限公司 | Nitride bottom, light emitting diode and bottom preparation method |
| CN109037070A (en) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| CN109103111B (en) * | 2018-09-27 | 2022-05-31 | 武汉新芯集成电路制造有限公司 | Forming method of PMOS structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246931A (en) * | 2007-02-14 | 2008-08-20 | 北京行者多媒体科技有限公司 | trace amount of boron doped intrinsic silicon hydride thin film |
| KR20080088959A (en) * | 2007-03-30 | 2008-10-06 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| CN101515547A (en) * | 2008-02-20 | 2009-08-26 | 中国科学院微电子研究所 | Method for manufacturing hyperconjugation VDMOS device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101246931A (en) * | 2007-02-14 | 2008-08-20 | 北京行者多媒体科技有限公司 | trace amount of boron doped intrinsic silicon hydride thin film |
| KR20080088959A (en) * | 2007-03-30 | 2008-10-06 | 주식회사 하이닉스반도체 | Method for forming semiconductor device |
| CN101515547A (en) * | 2008-02-20 | 2009-08-26 | 中国科学院微电子研究所 | Method for manufacturing hyperconjugation VDMOS device |
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