CN101728269A - Method for manufacturing PMOS transistor and PMOS transistor - Google Patents
Method for manufacturing PMOS transistor and PMOS transistor Download PDFInfo
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- CN101728269A CN101728269A CN200810224805A CN200810224805A CN101728269A CN 101728269 A CN101728269 A CN 101728269A CN 200810224805 A CN200810224805 A CN 200810224805A CN 200810224805 A CN200810224805 A CN 200810224805A CN 101728269 A CN101728269 A CN 101728269A
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Abstract
The invention discloses a method for manufacturing a PMOS transistor and the PMOS transistor manufactured by the method, wherein the method comprises the following steps of: providing a semiconductor substrate; forming a gate oxide layer on the semiconductor substrate; forming a gate conductive layer on the gate oxide layer; doping F ions into the gate oxide layer through the gate conductive layer; etching the gate conductive layer and the gate oxide layer to form a grid; and forming a source electrode area and a drain electrode area in the semiconductor substrates on two sides of the grid. The method for manufacturing the PMOS transistor improves NBTI and the performance of the PMOS transistor.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly transistorized manufacture method of PMOS and PMOS transistor.
Background technology
In the manufacturing technology of existing MOS transistor, usually at first on Semiconductor substrate, form grid oxide layer, on grid oxide layer, form grid conductive layer, form grid by etching grid conductive layer and grid oxide layer then, then the substrate intermediate ion in the grid both sides injects and forms source area and drain region, thereby forms MOS transistor.Wherein, described grid oxide layer utilizes oxide to form usually, for example silicon dioxide SiO
2Perhaps doped silica.In the manufacture process of MOS transistor, in order to reduce the resistance of grid, after grid conductive layer forms, grid conductive layer to be mixed usually, the mode of for example utilizing ion to inject is injected the boron ion of P type at the grid conductive layer of PMOS device.Apply cut-in voltage by the grid of giving MOS transistor then, can between source area and drain region, form conducting channel, in conducting channel, produce drain current by the electrical potential difference between source area and the drain region.The phenomenon that worsens along with the variations in temperature drain current is called as back bias voltage temperature stability (NBTI).Interface between known Semiconductor substrate and the grid oxide layer exists some electric charges and electronic state, is called as interfacial state.Along with the described interfacial state of variation of temperature changes, thereby make drain current change, so the MOS transistor NBTI that said method forms is relatively poor.
Further along with the develop rapidly of semiconductor fabrication, semiconductor wafer develops towards the high integration direction, so the grid critical dimension of MOS transistor dwindles gradually, and for example critical dimension has narrowed down to 65nm or 45nm.Therefore in order to improve the performance of device, the very thin thickness of grid oxide layer usually, 20 dusts for example, in the process that above-mentioned grid conductive layer mixes, the N type ion that has injection enters grid oxide layer, thereby forms gate leak current, thereby influences the transistorized performance of PMOS.In order to solve the problem of grid leakage current, in grid oxide layer, introduce nitrogen usually, reduced the infiltration of boron, yet because introduced nitrogen, the mobility of charge carrier rate in the conducting channel has been exerted an influence, therefore further make the NBTI variation again.
For example, open day: on June 15th, 2005 was disclosed, Granted publication number is: CN100369209C, name is called: in the Chinese patent of the method for formation gate dielectric layer (grid oxide layer), a kind of method that forms gate dielectric layer is provided as shown in Figure 1, has comprised: on semi-conductive substrate 11, formed one silica layer; And use the plasma that contains inert gas and nitrogen that this silicon oxide layer is carried out first and second nitrating step, to form a gate dielectric layer 13, wherein this two nitrating step in comparison, the power of this first nitrating step is lower, pressure is lower, but inert gas/nitrogen is than higher.In the method, the hole of flowing in the lead raceway groove of Semiconductor substrate and gate dielectric layer intersection is made that varying with temperature the drain current that flows through MOS transistor worsens, just negative bias temperature stability (NBTI) variation because hinder.
Therefore the problem that exists in the said method mainly is that the NBTI of MOS transistor is relatively poor, secondly is that gate leak current makes the degradation of MOS transistor.
Summary of the invention
In order to address the above problem, the invention provides transistorized manufacture method of a kind of PMOS and PMOS transistor, make the transistorized NBTI of PMOS improve, the transistorized performance of PMOS improves.
The transistorized manufacture method of PMOS of the present invention comprises step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
On grid oxide layer, form grid conductive layer;
By grid conductive layer to grid oxide layer doped F ion;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Optionally, inject BF described comprising to the grid oxide layer ion to the mode of grid oxide layer doped F ion by grid conductive layer
2
Optionally, describedly after grid oxide layer doped with fluorine ion step, also further comprise to grid conductive layer doping P type ion by grid conductive layer.
Optionally, described P type ion is the boron ion.
Optionally, further comprise after the formation grid oxide layer on Semiconductor substrate described, to grid oxide layer doping nitrogen ion.
Optionally, described doping nitrogen ion is the method that adopts the decoupled plasma nitriding.
Corresponding the present invention also provides a kind of PMOS transistorized manufacture method, comprises step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
To grid oxide layer doped F ion;
On grid oxide layer, form grid conductive layer;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Optionally, describedly also further comprise to grid conductive layer doping P type ion after on grid oxide layer, forming the grid conductive layer step.
Accordingly, the present invention also provides a kind of PMOS transistor that utilizes above-mentioned manufacture method to make, and its grid oxide layer and Semiconductor substrate be contacted to have the Si-F chemical bond at the interface.
Optionally, grid oxide layer with the contacted nitrogen ion that contains at the interface of grid conductive layer.
The advantage of technique scheme is: by doped F ion in grid oxide layer, thereby at the Si-F of formation at the interface of grid oxide layer and Semiconductor substrate chemical bond, because the highly stable influence of temperature change that is subjected to of Si-F chemical bond is little, therefore the transistorized NBTI of the PMOS that makes improves.
In a technical scheme of the present invention, inject BF described comprising to the grid oxide layer ion to the mode of grid oxide layer doped with fluorine ion by grid conductive layer
2, in the doped F ion, realize reduced the resistance of grid, and step being simple in grid oxide layer in realization like this to grid conductive layer doped with boron ion.
In a technical scheme of the present invention, further comprise after the formation grid oxide layer on Semiconductor substrate described, to grid oxide layer doping nitrogen ion.Because the nitrogen ion has the ability of catching the hole, because P type ion is the hole ion, therefore reduced the ability that penetrates grid oxide layer of P type ion to grid oxide layer doping nitrogen ion, reduced gate leak current.
In a technical scheme of the present invention, a kind of PMOS transistor is disclosed, comprise Semiconductor substrate, on described Semiconductor substrate, has grid, described grid comprises grid oxide layer and the grid conductive layer that is positioned on the grid oxide layer, have source area and drain region in the Semiconductor substrate of described grid both sides, it is characterized in that, grid oxide layer and Semiconductor substrate be contacted to have the Si-F chemical bond at the interface.
Description of drawings
Fig. 1 is the transistorized manufacture process schematic diagram of a kind of PMOS of the prior art;
Fig. 2 is the flow chart of transistorized manufacture method first embodiment of PMOS of the present invention;
The schematic diagram of the transistorized manufacture method embodiment of Fig. 3-Fig. 4 PMOS of the present invention;
Fig. 5 is the flow chart of transistorized manufacture method second embodiment of PMOS of the present invention;
Fig. 6-Fig. 7 is for carrying out the data of NBTI test to PMOS transistor of the present invention;
Fig. 8 is the test data of transistorized grid oxide layer thickness of the PMOS of PMOS transistor of the present invention and prior art and gate leak current.
Embodiment
Interface during PMOS is transistorized between Semiconductor substrate and the grid oxide layer exists some electric charges and electronic state, is called as interfacial state.Along with the described interfacial state of variation of temperature changes, thereby make drain current change, so PMOS transistor NBTI is relatively poor.
And in present manufacturing process; in order to reduce gate leak current; regular meeting utilizes the technology of grid oxide layer nitrating; for example draw together nitriding in Rapid Thermal nitriding (RTN), the stove, remote plasma nitriding (RPN) and decoupled plasma nitriding (DPN) etc.; yet because introduced nitrogen; therefore mobility to the hole in the conducting channel exerts an influence, and further makes the NBTI variation again.
The invention provides the transistorized manufacture method of a kind of PMOS, comprise step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
On grid oxide layer, form grid conductive layer;
By grid conductive layer to grid oxide layer doped F ion;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Wherein, inject BF described comprising to the grid oxide layer ion to the mode of grid oxide layer doped F ion by grid conductive layer
2
Wherein, describedly after grid oxide layer doped with fluorine ion step, also further comprise to grid conductive layer doping P type ion by grid conductive layer.
Wherein, described P type ion is the boron ion.
Wherein, further comprise after the formation grid oxide layer on Semiconductor substrate described, to grid oxide layer doping nitrogen ion.
Wherein, described doping nitrogen ion is the method that adopts the decoupled plasma nitriding.
Corresponding the present invention also provides a kind of PMOS transistorized manufacture method, comprises step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
To grid oxide layer doped F ion;
On grid oxide layer, form grid conductive layer;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
Wherein, describedly also further comprise to grid conductive layer doping P type ion after on grid oxide layer, forming the grid conductive layer step.
Accordingly, the present invention also provides a kind of PMOS transistor, comprise Semiconductor substrate, on described Semiconductor substrate, has grid, described grid comprises grid oxide layer and the grid conductive layer that is positioned on the grid oxide layer, have source area and drain region in the Semiconductor substrate of described grid both sides, it is characterized in that, grid oxide layer and Semiconductor substrate be contacted to have the Si-F chemical bond at the interface.
Wherein, grid oxide layer with the contacted nitrogen ion that contains at the interface of grid conductive layer.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Embodiment one
Please refer to Fig. 2.
S110: semi-conductive substrate is provided.
As shown in Figure 3, provide Semiconductor substrate 100, described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described Semiconductor substrate 100 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on; Described Semiconductor substrate 100 can also be other semi-conducting material, enumerates no longer one by one here.
In described Semiconductor substrate 100, can have the P trap, described P trap can form with those skilled in the art's method known, for example, on Semiconductor substrate 100, define the zone that forms the P trap by photoetching process earlier, carrying out ion then injects, form the P trap, the ion of injection is P type ion, for example boron ion.
S120: on Semiconductor substrate, form grid oxide layer.
On Semiconductor substrate 100, form grid oxide layer 102.Grid oxide layer 102 can be earth silicon material.Grid oxide layer 102 utilizes the method for thermal oxide growth or deposit to produce in the present embodiment.Because this grid oxide layer 102 plays the effect of electric insulation, and, need this grid oxide layer 102 very thin, therefore adopt the mode of thermal oxide growth can obtain high-quality grid oxide layer 102 along with the reducing of process.For example this step can be specially: at first clean Semiconductor substrate 100, remove the contamination and the oxide layer on surface, need in several hours Semiconductor substrate 100 be put into oxidation furnace for fear of secondary pollution then, the grid oxide layer 102 at the earth silicon material of one deck 20 dust to 50 dusts is given birth on Semiconductor substrate 100 surfaces.
S130: on grid oxide layer 102, form grid conductive layer 104.
On grid oxide layer 102, form grid conductive layer 104.The material of grid conductive layer 104 can be polysilicon.For example grid conductive layer 104 can adopt chemical vapor deposition to form, and comprises normal pressure chemical vapor deposition (APCVD), low-pressure chemical vapor phase deposition (LPCVD), plasma auxiliary chemical vapor deposition etc.Because LPCVD has good step covering power.Therefore the forming process at grid conductive layer 104 adopts LPCVD in the present embodiment.Those skilled in the art can according to manufacturing process determine grid conductive layer 104 required thickness.
Further comprise after on Semiconductor substrate 100, forming grid oxide layer 102, to grid oxide layer 102 doping N ions.This step can be adopted Rapid Thermal nitriding (RTN), nitriding in the stove, remote plasma nitriding (RPN) or decoupled plasma nitriding modes such as (DPN).For example adopt decoupled plasma nitriding (DPN) method among the embodiment, can be doped into the N ion that dosage is 2E15～6E15 at grid oxide layer 102.
Form the nitrogenous thin layer 106 of one deck on the surface that contacts with grid conductive layer 104 of grid oxide layer 104 like this, because the nitrogen ion has the ability of catching the hole, because the P ion is the hole ion, therefore this nitrogenous thin layer 106 can play seizure enters grid oxide layer 102 from grid conductive layer 104 P type ion in follow-up step, make P type ion can not enter grid oxide layer 102, grid oxide layer 102 just can play better gate insulation effect like this.
S140: by grid conductive layer 104 to grid oxide layer 102 doped F ions.
In order to obtain the grid of specific electrical resistance, usually grid conductive layer 104 is mixed, for example the grid conductive layer doping P type ion of PMOS device, for example boron ion.Therefore in the present embodiment, employing is mixed to grid conductive layer 104 and is fluoridized boron F
2, also fluorine ion so also mixes in the doped with boron ion.The mode that the mode of mixing can adopt ion to inject, for example the ability injected of ion is 1kev-3kev, and dosage is 5E14-3E15, and the vertical upper surface with grid conductive layer 104 of direction carries out 30 minutes-60 minutes annealing then under 750 degree-950 are spent.The F ion enters in the grid oxide layer 104 like this, and generates the Si-F key at the intersection 101 of grid oxide layer 104 and Semiconductor substrate 100, because the Si-F key is highly stable, therefore the variation of interfacial state is less when variations in temperature.
Simultaneously, because have nitrogenous thin layer 106 on the surface of grid oxide layer 104, so this layer makes when the F ion enters grid oxide layer 104 by nitrogenous thin layer 106, and the boron ion passes through than difficulty.
S150: etching grid conductive layer 106 and grid oxide layer 104 form grid.
This step can be adopted method well known to those skilled in the art, for example applies photoresist layer earlier, carries out photoetching and etching behind the sample, as shown in Figure 4, forms grid 108.
S160: in the Semiconductor substrate of grid 108 both sides, form source area and drain region.
This step can be adopted method well known to those skilled in the art, the mode that for example adopts ion to inject is injected P type ion to the Semiconductor substrate with grid, boron ion for example just forms the source area 110 and the drain region 112 of high concentration in the Semiconductor substrate of grid both sides.On the side that can also be included in grid 108 before formation source area and the drain region, form side wall layer.
Because the grid oxide layer 102 of grid 108 and Semiconductor substrate 100 have the Si-F key at the interface because the Si-F key is highly stable, make that therefore interfacial state is stable, thereby NBTI improves.And, therefore reduced the infiltration and the diffusion of P type ion because have nitrogenous thin layer 106 at the intersection of grid oxide layer 102 and grid conductive layer 104, and reduced gate leak current, make the transistorized performance of PMOS improve.
Embodiment two
Please refer to Fig. 3-Fig. 5.
S210: semi-conductive substrate is provided.
This step is identical with step S110, repeats no more.
S220: on Semiconductor substrate, form grid oxide layer.
This step is identical with step S120, repeats no more.
S230: to grid oxide layer 102 doped F ions.
Therefore in the present embodiment, employing is to grid oxide layer 102 doped F ions, and the F ion enters in the grid oxide layer 102 like this, and generates the Si-F key at the intersection 101 of grid oxide layer 102 and Semiconductor substrate 100, because the Si-F key is highly stable, therefore the variation of interfacial state is less when variations in temperature.
Simultaneously, because have nitrogenous thin layer 106 on the surface of grid oxide layer 102, so this layer makes when the F ion enters grid oxide layer 102 by nitrogenous thin layer 106, and the boron ion passes through than difficulty.
S240: on grid oxide layer 102, form grid conductive layer 104.
On grid oxide layer 102, form grid conductive layer 104.The material of grid conductive layer 104 can be polysilicon.For example grid conductive layer 104 can adopt chemical vapor deposition to form, and comprises normal pressure chemical vapor deposition (APCVD), low-pressure chemical vapor phase deposition (LPCVD), plasma auxiliary chemical vapor deposition etc.Because LPCVD has good step covering power.Therefore the forming process at grid conductive layer 104 adopts LPCVD.Those skilled in the art can according to manufacturing process determine grid conductive layer 104 required thickness.
In order to obtain the grid of specific electrical resistance, usually grid conductive layer 104 is mixed, for example the grid conductive layer doping P type ion of PMOS device, for example boron ion.
S250: etching grid conductive layer 106 and grid oxide layer 104 form grid.
This step can be adopted method well known to those skilled in the art, for example applies photoresist layer earlier, carries out photoetching and etching behind the sample, forms grid 108.
S260: in the Semiconductor substrate of grid 108 both sides, form source area and drain region.
This step can be adopted method well known to those skilled in the art, the mode that for example adopts ion to inject is injected P type ion to the Semiconductor substrate with grid, boron ion for example just forms the source area 110 and the drain region 112 of high concentration in the Semiconductor substrate of grid both sides.On the side that can also be included in grid 108 before formation source area and the drain region, form side wall layer.
Embodiment three
As shown in Figure 4, the present invention also provides a kind of PMOS transistor, comprise Semiconductor substrate 100, on described Semiconductor substrate 100, has grid, described grid comprises grid oxide layer 102 and the grid conductive layer 104 that is positioned on the grid oxide layer 102, in the Semiconductor substrate 100 of described grid both sides, have source area 110 and drain region 112, grid oxide layer 102 and Semiconductor substrate 100 101 have the Si-F chemical bond at the interface.
And grid oxide layer 102 contact with grid conductive layer 104 can also have nitrogenous thin layer 106 at the interface.
Because the Si-F key is highly stable, make that therefore interfacial state is stable, thereby NBTI improves.And, therefore reduced the infiltration and the diffusion of P type ion because have nitrogenous thin layer 106 at the intersection of grid oxide layer 102 and grid conductive layer 104, and reduced gate leak current, make the transistorized performance of PMOS improve.
Fig. 6 is the experimental data of the NBTI test of pair pmos transistor.Fig. 7 for and Fig. 6 experimental data that NBTI under the situation of different grid voltages tests of exerting pressure.Abscissa is the time from Fig. 6 and Fig. 7, ordinate is the percentage that drain current increases, as can be seen from the figure, utilize manufacture method of the present invention to PMOS transistor drain current in the same testing time change and obviously to reduce, thereby explanation NBTI is improved.
Fig. 8 is the experimental data of gate leak current and grid oxide layer thickness.Wherein the discrete point 810 in Fig. 8 left side is the grid oxide layer that PMOS transistor testing of the present invention is obtained and the data of gate leak current.The grid oxide layer that the discrete point 820 in Fig. 8 right side obtains for the test to the existing P MOS transistor and the data of gate leak current, abscissa is the thickness of grid oxide layer, ordinate is a gate leak current, as can be seen from Figure 8, under the situation of same grid oxide layer thickness, the transistorized gate leak current of PMOS of the present invention reduces, and the present invention is guaranteeing can to make the thickness of grid oxide layer littler under the qualified situation of gate leak current.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the transistorized manufacture method of PMOS is characterized in that, comprises step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
On grid oxide layer, form grid conductive layer;
By grid conductive layer to grid oxide layer doped F ion;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
2. manufacture method as claimed in claim 1 is characterized in that, inject BF described comprising to the grid oxide layer ion to the mode of grid oxide layer doped F ion by grid conductive layer
2
3. manufacture method as claimed in claim 1 is characterized in that, describedly also further comprises after grid oxide layer doped with fluorine ion step to grid conductive layer doping P type ion by grid conductive layer.
4. manufacture method as claimed in claim 3 is characterized in that, described P type ion is the boron ion.
5. manufacture method as claimed in claim 3 is characterized in that, further comprises after the formation grid oxide layer on Semiconductor substrate described, to grid oxide layer doping nitrogen ion.
6. manufacture method as claimed in claim 5 is characterized in that, described doping nitrogen ion is the method that adopts the decoupled plasma nitriding.
7. the transistorized manufacture method of PMOS is characterized in that, comprises step:
Semi-conductive substrate is provided;
On Semiconductor substrate, form grid oxide layer;
To grid oxide layer doped F ion;
On grid oxide layer, form grid conductive layer;
Etching grid conductive layer and grid oxide layer form grid;
In the Semiconductor substrate of grid both sides, form source area and drain region.
8. manufacture method as claimed in claim 7 is characterized in that, describedly also further comprises to grid conductive layer doping P type ion form the grid conductive layer step on grid oxide layer after.
9. PMOS transistor, comprise Semiconductor substrate, on described Semiconductor substrate, has grid, described grid comprises grid oxide layer and the grid conductive layer that is positioned on the grid oxide layer, in the Semiconductor substrate of described grid both sides, have source area and drain region, it is characterized in that grid oxide layer and Semiconductor substrate be contacted to have the Si-F chemical bond at the interface.
10. PMOS transistor as claimed in claim 9 is characterized in that, grid oxide layer with the contacted nitrogen ion that contains at the interface of grid conductive layer.
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| CN102420117A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Method for improving negative bias temperature instability of gate-last positive channel metal oxide semiconductor (PMOS) |
| CN102427043A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102427042A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method of improving carrier mobility of NMO (N-Mental-Oxide-Semiconductor) device |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
| CN103199013A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Improving method for PMOS gate-oxide negative bias temperature instability |
| CN103295913A (en) * | 2013-06-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for improving negative bias temperature instability of semiconductor device |
| CN113380624A (en) * | 2020-03-09 | 2021-09-10 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1012117B (en) * | 1988-06-27 | 1991-03-20 | 中国科学院上海冶金研究所 | Metal-oxide-semiconductor type field-effect transistor |
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| CN102420117A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Method for improving negative bias temperature instability of gate-last positive channel metal oxide semiconductor (PMOS) |
| CN102427043A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102427042A (en) * | 2011-08-04 | 2012-04-25 | 上海华力微电子有限公司 | Method of improving carrier mobility of NMO (N-Mental-Oxide-Semiconductor) device |
| CN102427042B (en) * | 2011-08-04 | 2015-05-20 | 上海华力微电子有限公司 | Method of improving carrier mobility of NMO (N-Mental-Oxide-Semiconductor) device |
| CN102427043B (en) * | 2011-08-04 | 2015-06-17 | 上海华力微电子有限公司 | Method for improving carrier mobility of PMOS (P-channel Metal Oxide Semiconductor) device |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
| CN103199013A (en) * | 2013-03-14 | 2013-07-10 | 上海华力微电子有限公司 | Improving method for PMOS gate-oxide negative bias temperature instability |
| CN103199013B (en) * | 2013-03-14 | 2016-03-30 | 上海华力微电子有限公司 | Improve the method for PMOS grid oxygen Negative Bias Temperature Instability |
| CN103295913A (en) * | 2013-06-04 | 2013-09-11 | 上海华力微电子有限公司 | Method for improving negative bias temperature instability of semiconductor device |
| CN103295913B (en) * | 2013-06-04 | 2016-01-27 | 上海华力微电子有限公司 | Improve the method for semiconductor device Negative Bias Temperature Instability |
| CN113380624A (en) * | 2020-03-09 | 2021-09-10 | 长鑫存储技术有限公司 | Semiconductor device and manufacturing method thereof |
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