CN102097129B - The erasing voltage rise control circuit of flash memory - Google Patents
The erasing voltage rise control circuit of flash memory Download PDFInfo
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- CN102097129B CN102097129B CN201110061741.7A CN201110061741A CN102097129B CN 102097129 B CN102097129 B CN 102097129B CN 201110061741 A CN201110061741 A CN 201110061741A CN 102097129 B CN102097129 B CN 102097129B
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Abstract
The present invention discloses a kind of erasing voltage rise control circuit of flash memory, at least comprises: for generation of the charge pump of erasing voltage; To the sample circuit that this erasing voltage samples; For generation of the controllable duty ratio pulse-generating circuit of dutycycle controllable pulse; Be connected to a supply voltage and this controllable duty ratio pulse-generating circuit, to produce the reference voltage generating circuit of a reference voltage under the control of this controllable duty ratio pulse-generating circuit; Be connected to and the first electric capacity between this reference voltage generating circuit and ground; And compare to produce the comparator circuit of a feedback signal to this charge pump to this sampling voltage and this reference voltage, reference current of the present invention and charging current produce owing to can't help the High voltage output of charge pump, extra current loading can not be produced to the output of charge pump, also do not have the loss of voltage, the rise time of erasing voltage is also more accurate.
Description
Technical field
The present invention about a kind of erasing voltage rise control circuit, particularly about a kind of erasing voltage rise control circuit of flash memory.
Background technology
In flash memory particularly low voltage flash memory device, often need to produce erasing voltage by charge pump (Charge Pump).The erasing voltage produced under condition without any restrictions due to charge pump often deviates from desirable value, therefore in the flash memory of prior art, often arranges control circuit and control the erasing voltage that charge pump exports.
Fig. 1 is the circuit structure diagram of the erasing voltage control circuit of a kind of flash memory in prior art, as shown in Figure 1, this control circuit comprises charge pump 11, controllable duty ratio pulse-generating circuit 12, by PMOS transistor P1, the mirror-image constant flow source 13 that P2 and nmos pass transistor N1 is formed, electric capacity C and nmos pass transistor N2, wherein, charge pump 11 exports high pressure HV, the drain electrode controllable duty ratio pulse-generating circuit 12 of source electrode and nmos pass transistor N2 that its output terminal is connected to PMOS transistor P1 and P2 is connected to nmos pass transistor N1 grid, controllable duty ratio pulse-generating circuit 12 output duty cycle is that the pulse of dc=A is to nmos pass transistor N1 grid, what nmos pass transistor N2 source electrode exported is erasing voltage VEE.Fig. 2 is the erasing voltage rising schematic diagram of Fig. 1, when controllable duty ratio pulse-generating circuit 12 exports high pressure, nmos pass transistor N1 conducting, electric capacity C starts charging, PMOS transistor P2 drain voltage RAMP continues to rise, erasing voltage VEE continues to rise thereupon, therefore reaches the object controlling erasing voltage and rise.
According to Fig. 1, can obtain:
i.e. Q=CV;
It is differentiated, can obtain
And due to the charging current on electric capacity C
therefore
Because charging current I is obtained by image current Ibias mirror image, and produce by the dutycycle A cycle, therefore
namely
Elapsed time T, erasing voltage is climbed to VEE,
the i.e. rise time of erasing voltage
But, due in the prior art, image current Ibias and charging current I produces by high pressure HV, the load of high pressure HV is increased the weight of, and the load capacity of charge pump 11 is poor usually, the Stability and veracity of the direct impact to voltage HV of extra current drain, thus cause the rise time T of the erasing voltage VEE exported inaccurate, subsequent conditioning circuit process cannot perform accurately and quickly.
In sum, the Flash memory erase voltage rise control circuit of known prior art exists because image current and charging current cause the inaccurate problem of erasing voltage voltage rising time by the high pressure that charge pump exports produces, simultaneously due to the existence of nmos pass transistor N2, export high pressure and can there is a threshold value loss, therefore, be necessary the technological means proposing to improve in fact, solve this problem.
Summary of the invention
The erasing voltage rise time inaccurate problem causing subsequent conditioning circuit process to perform accurately and quickly that the Flash memory erase voltage rise control circuit existed for overcoming above-mentioned prior art exists, fundamental purpose of the present invention is the erasing voltage rise control circuit providing a kind of flash memory, produced by supply voltage by system negative feedback and by reference current and charging current, avoid producing extra current loading to the High voltage output of charge pump, make the rise time of erasing voltage more accurate.
For reaching above-mentioned and other object, the erasing voltage rise control circuit of a kind of flash memory of the present invention, at least comprises:
Charge pump, for generation of erasing voltage;
Sample circuit, is connected to this charge pump outputs, for sampling this erasing voltage, exports sampling voltage;
Controllable duty ratio pulse-generating circuit, for generation of the pulse that dutycycle is controlled;
Reference voltage generating circuit, is connected to a supply voltage and this controllable duty ratio pulse-generating circuit, under controlling at this controllable duty ratio pulse-generating circuit, produce a reference voltage;
First electric capacity, is connected to and between this reference voltage generating circuit and ground; And
Comparator circuit, receives this sampling voltage and this reference voltage, to compare to produce a feedback signal to this charge pump to this sampling voltage and this reference voltage, to control this charge pump.
Further, this reference voltage generating circuit comprises the first PMOS transistor and the second PMOS transistor that a resistance and source and drain be connected, this the first PMOS transistor source electrode connects this supply voltage, grid is connected with this controllable duty ratio pulse-generating circuit, the drain electrode of this second PMOS transistor is respectively by this resistance and this capacity earth, and the drain electrode of this second PMOS transistor is also connected to this comparator circuit.
Further, this second PMOS transistor grid is connected to a bandgap voltage reference.
Further, this sample circuit comprises the second electric capacity and the 3rd electric capacity, this second electric capacity and the 3rd electric capacity are connected in series between this electric charge delivery side of pump and ground mutually, and the intermediate node of this second electric capacity and the 3rd electric capacity exports this sampling voltage to this comparator circuit.
Further, this sample circuit exports the negative input end of this sampling voltage to this comparator circuit, and this reference voltage generating circuit exports the positive input terminal of this reference voltage to this comparator circuit.
Further, a pull-down control circuit is also set between this resistance and ground to control this reference voltage generating circuit.
Compared with prior art, the erasing voltage rise control circuit of a kind of flash memory of the present invention is by system negative feedback and by being connected reference voltage generating circuit with supply voltage, the reference current of reference voltage generating circuit and the charging current of electric capacity are provided by supply voltage, compared to existing technology, the present invention can not produce additional current load to the High voltage output of charge pump, make the erasing voltage rise time of the present invention more accurate, be convenient to subsequent conditioning circuit and perform accurately and quickly.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a kind of Flash memory erase voltage rise of prior art control circuit;
Fig. 2 is the rising schematic diagram of erasing voltage in Fig. 1;
Fig. 3 is the circuit diagram of the erasing voltage rise control circuit preferred embodiment of a kind of flash memory of the present invention;
Fig. 4 is the rising schematic diagram of erasing voltage in Fig. 3.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 3 is the circuit diagram of the erasing voltage rise control circuit preferred embodiment of a kind of flash memory of the present invention.As shown in Figure 3, the erasing voltage rise control circuit of a kind of flash memory of the present invention at least comprises charge pump 31, controllable duty ratio pulse-generating circuit 32, reference voltage generating circuit 33, sample circuit 34, comparator circuit 35 and electric capacity C1.
Wherein charge pump 31 output terminal is connected to sample circuit 34, exports the negative input end of comparator circuit 35 after the output voltage of sample circuit 34 pairs of charge pumps 31 samples to; Controllable duty ratio pulse-generating circuit 32 is connected to reference voltage generating circuit 33, be that the pulse of A produces reference voltage V REF to control reference voltage generating circuit 33 for generation of dutycycle, reference voltage generating circuit 33 is connected to supply voltage VDD, to produce the positive input terminal that reference voltage V REF exports comparator circuit 35 to; Electric capacity C1 is connected between reference voltage generating circuit 33 and ground; The output of comparator circuit 35 couples of reference voltage V REF and sample circuit 34 compares the input end of rear generation feedback signal FB to charge pump 31, to control charge pump.
Further, in the preferred embodiment of this religious name, reference voltage generating circuit 33 comprises PMOS transistor P1, PMOS transistor P2 and resistance R, PMOS transistor P1 source electrode meets supply voltage VDD, grid is connected with controllable duty ratio pulse-generating circuit 32, drains to be connected with PMOS transistor P2 source electrode, and PMOS transistor grid is connected to a bandgap voltage reference, drain electrode is by resistance R ground connection, and PMOS transistor P2 drain electrode output reference voltage VREF is to the positive input terminal of comparator circuit 35; The output voltage (i.e. erasing voltage VEE) that sample circuit 34 pairs of charge pumps 31 export is sampled, it is made up of electric capacity C2 and C3 mutually connected, the intermediate node of electric capacity C2 and C3 is sampling spot, be connected to the negative input end of comparator circuit 35, the sampling voltage VIN of acquisition feeding comparer and reference voltage V REF to be compared.Certainly, it is preferred that work for better controlling reference voltage generating circuit 33, a pull-down control circuit also can be set between resistance R and ground to control the work of reference voltage generating circuit 33.
Principle of work of the present invention is: when sampling voltage VIN exceedes reference voltage V REF, the feedback signal FB of comparator circuit 35 output low levels makes charge pump 31 quit work, thus reduce the erasing voltage VEE of high pressure, if when sampling voltage VIN is lower than VREF, the feedback signal FB that then comparator circuit 35 exports high level impels charge pump 31 continuous firing that the erasing voltage VEE of output is raised to charge pump 31, the negative feedback of system can make erasing voltage VEE be maintained at certain steady-state value, as 17V.
Visible, the charging current of the reference current IB2 that reference voltage generating circuit 33 of the present invention is used and electric capacity C is produced by supply voltage VDD, and do not produce additional current load to the output of charge pump 31, the charging voltage of electric capacity C1 linearly rises.According to Fig. 3, then can draw:
The charging current of electric capacity C
namely
Suppose that the time that electric capacity C charges to VREF is T, then
thus
The reference voltage determined by bandgap voltage reference and reference current IB2 when VREF is stable, and reference current IB2 can't help the output of charge pump produces, do not control by it, therefore, duration of charging T is comparatively accurate.Fig. 4 is the schematic diagram that the erasing voltage of Fig. 3 rises, and in figure, the generation of T1 fails very well work due to comparator circuit 35 when starting, but is also in a lower value due to now erasing voltage VEE, therefore can not have an impact.
In sum, the erasing voltage rise control circuit of a kind of flash memory of the present invention is by system negative feedback and by being connected reference voltage generating circuit with supply voltage, the reference current of reference voltage generating circuit and the charging current of electric capacity are provided by supply voltage, make the present invention can not produce additional current load to the High voltage output of charge pump, and then make the erasing voltage rise time of the present invention more accurate, be convenient to subsequent conditioning circuit and perform accurately and quickly
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (5)
1. an erasing voltage rise control circuit for flash memory, at least comprises:
Charge pump, for generation of erasing voltage;
Sample circuit, is connected to this charge pump outputs, for sampling this erasing voltage, exports sampling voltage;
Controllable duty ratio pulse-generating circuit, for generation of the pulse that dutycycle is controlled;
Reference voltage generating circuit, is connected to a supply voltage and this controllable duty ratio pulse-generating circuit, under controlling at this controllable duty ratio pulse-generating circuit, produce a reference voltage;
First electric capacity, is connected to and between this reference voltage generating circuit and ground; And
Comparator circuit, receives this sampling voltage and this reference voltage, to compare to produce a feedback signal to this charge pump to this sampling voltage and this reference voltage, to control this charge pump;
This reference voltage generating circuit comprises the first PMOS transistor and the second PMOS transistor that a resistance and source and drain be connected, this the first PMOS transistor source electrode connects this supply voltage, grid is connected with this controllable duty ratio pulse-generating circuit, the drain electrode of this second PMOS transistor is respectively by this resistance and this capacity earth, and the drain electrode of this second PMOS transistor is also connected to this comparator circuit.
2. the erasing voltage rise control circuit of flash memory as claimed in claim 1, is characterized in that: this second PMOS transistor grid is connected to a bandgap voltage reference.
3. the erasing voltage rise control circuit of flash memory as claimed in claim 2, it is characterized in that: this sample circuit comprises the second electric capacity and the 3rd electric capacity, this second electric capacity and the 3rd electric capacity are connected in series between this electric charge delivery side of pump and ground mutually, and the intermediate node of this second electric capacity and the 3rd electric capacity exports this sampling voltage to this comparator circuit.
4. the erasing voltage rise control circuit of flash memory as claimed in claim 3, it is characterized in that: this sample circuit exports the negative input end of this sampling voltage to this comparator circuit, this reference voltage generating circuit exports the positive input terminal of this reference voltage to this comparator circuit.
5. the erasing voltage rise control circuit of flash memory as claimed in claim 4, is characterized in that: between this resistance and ground, also arrange a pull-down control circuit to control this reference voltage generating circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110061741.7A CN102097129B (en) | 2011-03-15 | 2011-03-15 | The erasing voltage rise control circuit of flash memory |
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| CN201110061741.7A CN102097129B (en) | 2011-03-15 | 2011-03-15 | The erasing voltage rise control circuit of flash memory |
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| CN102097129B true CN102097129B (en) | 2015-08-19 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568576B (en) * | 2012-01-10 | 2014-12-24 | 清华大学 | Operation method of flash memory |
| WO2014033851A1 (en) * | 2012-08-29 | 2014-03-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| CN103236789B (en) * | 2013-04-24 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Charge pump output voltage regulating circuit and storage device |
| CN104485132B (en) * | 2014-12-30 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | Data erasing circuit |
| CN111865073B (en) * | 2019-04-30 | 2021-10-19 | 合肥格易集成电路有限公司 | Partial pressure feedback circuit of PUMP system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168174A (en) * | 1991-07-12 | 1992-12-01 | Texas Instruments Incorporated | Negative-voltage charge pump with feedback control |
| US6411069B1 (en) * | 1999-08-31 | 2002-06-25 | Advanced Micro Devices, Inc. | Continuous capacitor divider sampled regulation scheme |
| CN101964212A (en) * | 2010-08-11 | 2011-02-02 | 上海宏力半导体制造有限公司 | Negative voltage slope control circuit |
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2011
- 2011-03-15 CN CN201110061741.7A patent/CN102097129B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5168174A (en) * | 1991-07-12 | 1992-12-01 | Texas Instruments Incorporated | Negative-voltage charge pump with feedback control |
| US6411069B1 (en) * | 1999-08-31 | 2002-06-25 | Advanced Micro Devices, Inc. | Continuous capacitor divider sampled regulation scheme |
| CN101964212A (en) * | 2010-08-11 | 2011-02-02 | 上海宏力半导体制造有限公司 | Negative voltage slope control circuit |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140505 |
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