CN102087826B - Drive method of field-sequential flat-panel display - Google Patents
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Abstract
The invention discloses a drive method of a field-sequential flat-panel display, which is characterized in that scanning lines are divided into odd scanning lines and even scanning lines, and a storage space is spared by means of time-division multiplexing, wherein when the image information of the odd scanning lines are taken out from a frame memory and displayed on a display panel, the image information of the even scanning lines of the next picture are written into the frame memory; and when the image information of the even scanning lines are taken out the frame memory and displayed on the display panel, the image information of the odd scanning lines of the next picture are written into the frame memory. The drive method of a field-sequential flat-panel display provided by the invention has the advantage that the capacity requirement of the frame memory can be reduced by half.
Description
Technical Field
The present invention relates to a driving technique of a liquid crystal flat panel display, and more particularly, to a driving method of a field sequential flat panel display which reduces memory requirements.
Background
Fig. 1 is a schematic diagram of a Source Driver Circuit (Source Driver Circuit) and a display Panel (Panel) of a conventional Liquid Crystal Display (LCD), in which a Liquid Crystal Display (LCD) 10 includes a display Panel 11, even-numbered information lines 12 and a Source Driver Circuit 13, the display Panel 11 includes two-dimensional matrix pixels (pixels) 20, each pixel 20 includes a red sub-pixel 21, a green sub-pixel 22 and a blue sub-pixel 23, and the information lines 12 respectively control the operations of the red sub-pixel 21, the green sub-pixel 22 and the blue sub-pixel 23. In the conventional driving method of the liquid crystal display 10, the source driving circuit 13 of the driving device drives the red sub-pixel 21, the green sub-pixel 22 and the blue sub-pixel 23 on the display panel 11. However, the display panel 11 has as many columns of sub-pixels as there are information lines to drive, and the source driving circuit 13 provides corresponding driving signals. In addition, the liquid crystal display 10 must be configured with Color filters (not shown) for filtering red, green and blue, so the manufacturing cost of the liquid crystal display 10 is relatively high.
FIG. 2 is a schematic diagram of a source driver circuit and a display panel of another conventional display. As shown in the figure, the conventional display 10a includes a display panel 11a, even-numbered information lines 12a, and a source driving circuit 13 a. The display panel 11a includes a two-dimensional matrix of pixels 20a, each pixel 20a includes a red light emitting unit 21a, a green light emitting unit 22a, and a blue light emitting unit 23a, wherein the light emitting units may be Light Emitting Diodes (LEDs), for example. The source driver circuit 13a of the display 10a employs a time field sharing (time field sharing) technique to reduce the number of driving signal outputs of the information lines.
The time-domain division technique is to turn on red, blue and green lights in each frame (frame), for example, first turn on the red light-emitting unit 21a to turn the screen red, then turn on the green light-emitting unit 22a to turn the screen green, and then turn on the blue light-emitting unit 23a to turn the screen blue. The operation principle of the display device is mainly characterized in that the human eyes have Visual persistence (Visual persistence) so that a user can present a color picture when watching the display device. Because the field division technology is used in the display 10a, the number of the information lines needed is only 1/3, and no color filter is needed, so that the manufacturing cost can be greatly reduced.
FIG. 3 is a Timing diagram of signals used to drive the display of FIG. 2. As shown in fig. 3, the source driving circuit 13a is used for receiving a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync). During one frame T of the display screen, the output signal (Sout) of the source driving circuit 13a is divided into three sub-frames for respectively lighting the red light-emitting unit 21a, the green light-emitting unit 22a and the blue light-emitting unit 23 a. Since the red light-emitting unit 21a, the green light-emitting unit 22a and the blue light-emitting unit 23a are respectively lighted up, and each sub-frame requires the same number of trigger signals of the horizontal synchronization signal, the frequency of the horizontal synchronization signal is increased by 3 times.
Since the display time of the three primary colors of red, green, and blue is divided by time, the entire image information of the three primary colors must be stored in advance. Since the display is separated by red, green and blue, the memory space required for storing the image signal of the full frame must be twice the image resolution capacity, and the writing of the image information of odd scan lines in the next frame can be satisfied.
Fig. 4 is a schematic diagram of a frame memory required by a conventional field sequential liquid crystal display panel driving method. Referring to fig. 4, a frame memory 401 is used for storing frame information. The conventional field sequential liquid crystal display panel has two frame memories 401 therein. Fig. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method. Fig. 5B is an enlarged waveform diagram of the I-th frame of fig. 5A. Fig. 5C is an enlarged waveform diagram of the I +1 th frame of fig. 5A. Referring to fig. 5A, 5B and 5C, it can be seen from the access timing diagram that each horizontal synchronization (Hsync) time L1～LmInformation of the next picture to be displayed is written into the frame memory. In addition, the red color L in the frame memory must be read out separately every 1/3 frame times1(R1～Rn)～Lm(R1～Rn) Green color L1(G1～Gn)～Lm(G1～Gn) Or blue L1(B1～Bn)～Lm(B1～Bn) The display information of (1).
Therefore, the conventional field sequential liquid crystal display panel must have two frame memories 401 for storing the display information of the current frame (I frame) and the next frame (I +1 frame), respectively.
Disclosure of Invention
Accordingly, the present invention provides a driving method for a field sequential flat panel display to reduce the capacity requirement of the frame memory by half.
The invention provides a driving method of a field sequential flat panel display, the field sequential flat panel display comprises even number of frames, each frame comprises pixels respectively corresponding to a red light source, a blue light source and a green light source, the driving method comprises the following steps: a. storing the pixel information of odd scanning lines in an odd frame memory area and storing the pixel information of even scanning lines in an even frame memory area; b. writing the pixel information of the even scan lines of the I +1 th frame into the even frame memory area when the pixel information of the odd scan lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display during the I frame; and c, during the I +1 th frame, when the pixel information of the even scanning lines is taken out from the even frame memory area and displayed on the field sequential flat panel display, writing the pixel information of the odd scanning lines of the I +2 th frame into the odd frame memory area, wherein I is a natural number.
Therefore, according to the technical scheme provided by the invention, the scanning lines are divided into odd scanning lines and even scanning lines, and the same memory space is shared by utilizing a time division multiplexing mode. When the odd scanning lines are taken out from the frame memory and displayed on the display panel, the image information of the even scanning lines of the next picture is written. When the even scan lines are fetched from the frame memory and displayed on the display panel, the image information of the odd scan lines of the next frame is written. Therefore, the invention can reduce the capacity requirement of the frame memory needed by driving the field sequential flat panel display, and only needs half of the capacity of the traditional mode to realize the driving.
Further, as the demand for the frame memory built in the display driver is reduced, the dynamic power consumption of the display driver is also reduced.
Drawings
FIG. 1 is a schematic diagram of a source driver circuit and a display panel of a conventional LCD.
FIG. 2 is a schematic diagram of a source driver circuit and a display panel of another conventional display.
FIG. 3 is a conventional timing diagram of signals used to drive the display of FIG. 2.
FIG. 4 is a diagram of two sets of frame memories required by a conventional driving method for a field sequential LCD panel.
Fig. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method.
Fig. 5B is an enlarged waveform diagram of the I-th frame of fig. 5A.
Fig. 5C is an enlarged waveform diagram of the I +1 th frame of fig. 5A.
FIG. 6 is a schematic system diagram of a field sequential flat panel display according to the present invention.
Fig. 7 is a configuration diagram of the frame memory 605 of the present invention.
FIG. 8A is a timing waveform diagram of a driving method of a flat panel display according to a first embodiment of the present invention.
Fig. 8B is an enlarged waveform diagram of the I-th frame of fig. 8A.
Fig. 8C is an enlarged waveform diagram of the I +1 th frame of fig. 8A.
FIG. 9A is a clock waveform diagram of a driving method of a flat panel display according to a second embodiment of the present invention.
Fig. 9B is an enlarged waveform diagram of the I-th frame of fig. 9A.
Fig. 9C is an enlarged waveform diagram of the I +1 th frame of fig. 9A.
FIG. 10A is a clock waveform diagram of a driving method of a flat panel display according to a third embodiment of the present invention.
Fig. 10B is an enlarged waveform diagram of the I-th frame of fig. 10A.
Fig. 10C is an enlarged waveform diagram of the I +1 th frame of fig. 10A.
[ description of main element symbols ]
10: liquid crystal display device with a light guide plate
10 a: display device
11. 11 a: display panel
12. 12 a: information line
13. 13 a: source electrode driving circuit
20: pixel
21: red sub-pixel
21 a: red light emitting unit
22: green sub-pixel
22 a: green light emitting unit
23: blue sub-pixel
23 a: blue light emitting unit
401: frame memory
601: display panel
602: source driver
603: gate driver
604: time sequence controller
605: frame memory
701: odd frame memory area
702: even frame memory area
801. 901, 1001: write timing
802. 902, 1002: read timing
803. 903, 1003: red LED lightening signal (R-LED)
804. 904, 1004: green LED lighting signal (G-LED)
805. 905, 1005: blue LED lighting signal (B-LED)
G1-G5: gate drive Signal (Gate Driving Signal)
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 6 is a schematic system diagram of a field sequential flat panel display according to the present invention. Referring to fig. 6, the flat panel display includes a display panel 601, a source driver 602, a gate driver 603, and a timing controller 604, wherein the timing controller 604 includes a frame memory 605.
When a single pixel in the display panel 601 is to display color, one pin of the gate driver 603 is used to control the tft switches, and three pins of the source driver 602 are used to input R, G, B the three primary color signals. In addition, for convenience of description, the switches described hereinafter refer to thin film transistor switches unless otherwise specified. The gate driver 603 is responsible for switching signals of each column of the display, and when the display scans column by column, the gate driver 603 turns on a whole column of switches to allow the source driver 602 to input signals. The source driver 602 is responsible for inputting the pixel signals of each row of the display, and when the gate driver 603 turns on a row of switches, the source driver 602 outputs the row of pixel information voltages in real time to provide the signals required for displaying the image.
The timing controller 604 is used to adjust the operation of the entire display, and in accordance with the display timing of each frame, sets the activation of the horizontal scan lines on the one hand, and controls the gate driver 603 to output a proper voltage to a specific column of switches. On the other hand, the timing controller 604 receives an external input signal, converts the received video information into a digital signal required by the source driver 602, and sets a timing for driving the vertical scan lines in accordance with the turning-on of the horizontal scan lines, thereby controlling the source driver 602 to output a voltage of the pixel information.
Fig. 7 is a configuration diagram of the frame memory 605 of the present invention. Referring to fig. 7, the frame memory is divided into two parts, i.e., an odd frame memory area 701 and an even frame memory area 702, wherein the odd frame memory area 701 is used for storing red, green and blue pixel information in odd scan lines, and the even frame memory area 702 is used for storing red, green and blue pixel information in even scan lines.
The technical solution of the invention is described in detail by three embodiments below.
First embodiment
FIG. 8A is a timing waveform diagram of a driving method of a field sequential flat panel display according to a first embodiment of the present invention. Fig. 8B is an enlarged waveform diagram of the I-th frame of fig. 8A. Fig. 8C is an enlarged waveform diagram of the I +1 th frame of fig. 8A. Referring to fig. 8A, 8B and 8C, the timing waveform diagrams include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a write timing 801, a read timing 802, a red light emitting diode (R-LED)803, a green light emitting diode (G-LED)804, a blue light emitting diode (B-LED)805 and a Gate driving signal (Gate driving signal), such as G1-G5. The vertical synchronization signal and the horizontal synchronization signal are signals used by an external signal source as a display for synchronization. The vertical synchronization signal enable period is used for indicating the time when a frame can be displayed, and the horizontal synchronization signal enable period is used for indicating the time when the information of a horizontal scanning line can be output. The enable period of the write timing 801 indicates a period during which the timing controller 604 writes information into the odd frame memory area 701 or the even frame memory area 702. The enable period of the read timing sequence 802 indicates that the source driver 602 outputs the voltage of the corresponding column of pixel information in conjunction with the opened horizontal scan line. The red led lighting signal 803, the green led lighting signal 804, and the blue led lighting signal 805 enable periods respectively indicate periods in which the red, green, and blue backlights are lit. The gate driving signals G1-G5 are outputs of the gate driver 603 for turning on an array of corresponding switches in the liquid crystal matrix.
At the I-th frame time, as shown in the figure, every time the horizontal synchronization signal is enabled, i.e., every time the horizontal synchronization signal is at a logic high voltage, the write timing 801 is enabled, and the memory starts to be written with the display information of the next frame, i.e., the display information of the I + 1-th frame. More specifically, during the I-th frame, only the pixel information of the even scan lines in the next frame (I + 1-th frame) is written to the even frame memory area 702, wherein the odd frame memory area 701 is not updated. Next, please refer to the read timing 802, the red led lighting Signal 803, and the gate driving signals (GateDriving signals) G1-G5. When the red led lighting signal 803 is enabled, the red pixel information (R1 to Rn) of the odd scan lines L1, L3, and L5.. Lm-1 in the odd frame memory area 701 is read out, respectively. When the odd-column gate driving signals are enabled, the source driver 602 converts the read red pixel information into corresponding column pixel information voltages in cooperation with an entire column switch turned on by the odd-column gate driving signals, that is, in cooperation with the turn-on time of the horizontal scanning lines corresponding to the driving gates, the source driver 602 drives the vertical scanning lines to provide signals required for displaying the image.
In addition, during the enabling period of the red led lighting signal 803 in the same frame time (I-th frame period in the figure), when the even column gate driving signals of the gates G2, G4. are enabled, the red pixel information of the even scan lines L2, L4.. Lm of the even frame memory region 702 are read out respectively, and the source driver 602 converts and outputs the read red pixel information into the corresponding column pixel information voltage in cooperation with an alignment switch turned on by the even column gate driving signals, so as to provide the signals required for displaying the picture.
Similarly, when the green led lighting signal 804 is enabled, the green pixel information (G1 to Gn) of the odd scan lines L1, L3, L5.. Lm-1 in the odd frame memory area 701 is read out, respectively. When the odd-column gate driving signals of the gates are enabled, the source driver 602 converts the read green pixel information into corresponding column pixel information voltages in cooperation with an entire column switch turned on by the odd-column gate driving signals. In addition, during the enabling period of the green led lighting signal 804 in the same frame time (I-th frame period in the figure), when the even column gate driving signal is enabled, the green pixel information (G1-Gn) of the even scan lines L2, L4.. Lm of the even frame memory region 702 is read out, respectively, and the source driver 602 converts and outputs the read green pixel information to the corresponding column pixel information voltage in cooperation with one column switch turned on by the even column gate driving signal, so as to provide the signals required for displaying the picture.
Similarly, when the blue led lighting signal 805 is enabled, the blue pixel information (B1 to Bn) of the odd scan lines L1, L3, L5.. Lm-1 in the odd frame memory area 701 is read out. When the odd column gate driving signals are enabled, the source driver 602 converts and outputs the read blue pixel information into corresponding column pixel information voltages in cooperation with an entire column switch turned on by the odd column gate driving signals G1, G3, G5..
In addition, during the enabling period of the blue led lighting signal 805 in the same frame time (I-th frame period in the figure), when the even column gate driving signal is enabled, the blue pixel information (B1 to Bn) of the even scan lines L2, L4.. Lm of the even frame memory region 702 is read out, respectively, and the source driver 602 converts and outputs the read blue pixel information into the corresponding column pixel information voltage in cooperation with the one column switch turned on by the even column gate driving signals G2, G4... the read-out blue pixel information is read out.
As described above, when the even-numbered scanning lines of red, green, or blue are driven, the even-numbered frame memory area 702 is also being updated at the same time, and therefore, some of the fetched information may be updated information. However, since the difference between the current frame (I-th frame) and the next frame (I + 1-th frame) is 1/60 seconds, the difference between the pixels of the previous and next frames is not significant, and the image quality of the display is hardly adversely affected.
Next, at the I +1 th frame time, every time the horizontal synchronization signal Hsync is enabled, that is, every time the horizontal synchronization signal Hsync is at a logic high voltage, the write timing 801 is enabled, and the memory starts to be written with the display information of the next frame, that is, the display information of the I +2 th frame. More specifically, during the I +1 th frame, only the pixel information of the odd scan lines in the next frame (I +2 th frame) is written into the odd frame memory area 701, wherein the even frame memory area 702 is not updated. Next, please refer to the read timing 802, the red led lighting Signal 803, and the gate driving signals (GateDriving signals) G1-G5.
When the red led lighting signal 803 is enabled, the red pixel information (R1 to Rn) of the even scan lines L2, L4,. Lm in the even frame memory area 702 is read out, respectively. When the even column gate driving signals are enabled, the source driver 602 converts the read red pixel information into corresponding column pixel information voltages in cooperation with an array switch turned on by the even column gate driving signals G2, G4., that is, in cooperation with the turn-on time of the corresponding horizontal scanning lines of the driving gates G2, G4, G6., the source driver 602 drives the vertical scanning lines to provide signals required for displaying the image.
In addition, during the enabling period of the red led lighting signal 803 in the same frame time (I +1 th frame period in the figure), when the odd column gate driving signal is enabled, the red pixel information (R1 to Rn) of the odd scan lines L1, L3.. Lm-1 of the odd frame memory region 701 is read out, respectively, and the source driver 602 converts and outputs the read red pixel information into the corresponding column pixel information voltage in cooperation with an entire column switch turned on by the odd column gate driving signals G1, G3, G5... to provide the signals required for displaying the image.
Similarly, when the green led lighting signal 804 is enabled, the green pixel information of the even scan lines L2, L4, L6.. Lm in the even frame memory area 702 is read out. When the even column gate driving signals of the gates G2 and G4. are enabled, the source driver 602 converts and outputs the read green pixel information into the corresponding column pixel information voltage in cooperation with an entire column switch turned on by the even column gate driving signals G2 and G4..
In addition, during the enabling period of the green led lighting signal 804 in the same frame time (I +1 th frame period in the figure), when the odd column gate driving signals of the gates G1, G3, G5. are enabled, the green pixel information (G1-Gn) of the odd scan lines L1, L3.. Lm-1 of the odd frame memory region 701 is read out respectively, and the source driver 602 converts and outputs the read-out green pixel information into the corresponding column pixel information voltage in cooperation with one column switch turned on by the odd column gate driving signals G1, G3, G5., so as to provide the signals required for displaying the picture.
Similarly, when the blue led lighting signal 805 is enabled, the blue pixel information (B1 to Bn) of the even scan lines L2, L4, and L6.. Lm in the even frame memory area 702 is read out. When the even column gate driving signals of the gates G2, G4. are enabled, the source driver 602 converts and outputs the read blue pixel information into the corresponding column pixel information voltage in cooperation with an entire column switch turned on by the even column gate driving signals G2, G4..
In addition, in the enabling period of the blue led lighting signal 805 in the same frame time (I +1 th frame period in the figure), when the odd column gate driving signals of the gates G1, G3, G5. are enabled, the blue pixel information (B1 to Bn) of the odd scan lines L1, L3, L5 · are read out respectively from the odd frame memory area 701, and the source driver 602 converts and outputs the read-out blue pixel information into the corresponding column pixel information voltage in cooperation with one column switch turned on by the odd column gate driving signals G1, G3, G5.°.
Further, in the I +1 th frame time, when the driving action of the odd-numbered scanning lines of red, green, or blue is performed, the odd-numbered frame memory area 701 is also being updated, and therefore, a certain part of the fetched information may be updated information. However, since the difference between the current frame (I +2 th frame) and the next frame (I +2 th frame) is 1/60 seconds, the difference between the pixels of the previous and next frames is not significant, and the image quality of the display is hardly adversely affected.
In summary, only the even frame memory area 702 is updated during the I-th frame time, so that when the odd scan lines corresponding to the gates are turned on, the source driver 603 uses the un-updated current frame stored in the odd frame memory area 701 as the display information. In the I +1 th frame time, only the odd frame memory area 701 is updated, so that when the even scan lines corresponding to the gates are turned on, the source driver 603 uses the current frame stored in the even frame memory area 502 and not updated as the display information. Since the time difference between the previous and next frames is only 1/60 seconds, the difference between the pixels of the previous and next frames is not obvious. Therefore, the influence on the image quality of the display is negligible.
Therefore, the invention can reduce the capacity requirement of the frame memory required by driving the field sequential flat panel display, namely, the field sequential flat panel display can be driven by only using a half frame memory in the traditional mode, wherein, in each frame time, only half pixel information needs to be written into the frame memory, thereby achieving the effect of saving electricity.
Second embodiment
FIG. 9A is a timing waveform diagram of a driving method of a field sequential flat panel display according to a second embodiment of the present invention, wherein FIG. 9B is an enlarged waveform diagram of frame I of FIG. 9A, and FIG. 9C is an enlarged waveform diagram of frame I +1 of FIG. 9A. Referring to fig. 9A, 9B and 9C, similarly, the pulse diagram includes a vertical synchronization Signal (Vsync), a horizontal synchronization Signal (Hsync), a write timing 901, a read timing 902, a red LED on Signal (R-LED on)903, a green LED on Signal (G-LED on)904, a blue LED on Signal (B-LED on)905 and a Gate Driving Signal (Gate Driving Signal), for example, G1 to G5.
At the I-th frame time (I-th frame period in the figure), when the horizontal synchronization signal is enabled, that is, when the horizontal synchronization signal is at a logic high voltage, the write timing 901 is enabled, and the memory starts to be written with the display information of the next frame (I + 1-th frame). The same as the first embodiment described above is that, during the I-th frame, only the pixel information of the even-numbered scan lines in the next frame (I + 1-th frame) is written to the even frame memory area 702. In addition, the odd frame memory area 701 is not updated.
Next, please refer to the read timing 902, the red LED lighting signal 903, and the gate driving signals G1-G5. When the red led lighting signal 903 is enabled, the red pixel information (R1 to Rn) of the odd scan lines in the odd frame memory area 701 is read out. When the gate driving signals of the gates G1 and G2 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the scan line L1 into corresponding column pixel information voltages in cooperation with the two column switches turned on by the gate driving signals G1 and G2; when the gate driving signals of the gates G3 and G4 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the scan line L3 into corresponding column pixel information voltages in accordance with the two column switches turned on by the gate driving signals G3 and G4, and so on.
Next, the enabling periods of the green led and the blue led are the same as the red led, and are not described herein again.
In the I +1 th frame time (I +1 th frame period in the figure), when the horizontal synchronization signal is enabled and the horizontal synchronization signal is at a logic high voltage, the write timing 901 is enabled, and the memory starts to be written with the pixel information of the next frame, i.e., the pixel information of the I +2 th frame. More specifically, during the I +1 th frame, only the pixel information of the odd scan lines of the I +2 th frame is written to the odd frame memory area 701, and the even frame memory area 702 is not updated.
Next, please refer to the read timing 902, the red led lighting Signal 903, and the Gate Driving signals (Gate Driving signals) G1-G5. When the red led lighting signal 903 is enabled, the red pixel information (R1 to Rn) of the even scan lines L2, L4, and L6.. Lm in the even frame memory region 702 is read out, and the L1 of the odd scan lines is read out. When the gate driving signal of the gate G1 is enabled, the red pixel information (R1 to Rn) of the first scan line L1 of the odd frame memory region 701 is read out respectively, and the source driver 602 converts and outputs the read red pixel information (R1 to Rn) of the scan line L1 into the corresponding column pixel information voltage in cooperation with an entire column switch turned on by the gate driving signal G1; when the gate driving signals of the gates G2 and G3 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the scan line L2 into corresponding column pixel information voltages in cooperation with the two column switches turned on by the gate driving signals G2 and G3; when the gate driving signals of the gates G4 and G5 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the scan line L4 into corresponding column pixel information voltages in cooperation with the two column switches turned on by the gate driving signals G4 and G5; .., and so on below.
Next, during the enabled period of the green led lighting signal 904 and the blue led lighting signal 905, the actions thereof are the same as those of the red led lighting signal, and are not described herein again.
In the I +1 th frame of the above embodiment, the pixel information in the first scanning line L1 stored in the odd frame memory area 701 is used as the display information of the gate G1, and the other gates G2, G3, and G4. use the pixel information of the even scanning lines L2, L4, and L6.. Lm in the even frame memory area 702.
Third embodiment
FIG. 10A is a timing waveform diagram of a driving method of a field sequential flat panel display according to a third embodiment of the present invention. Fig. 10B is an enlarged waveform diagram of the I-th frame of fig. 10A. Fig. 10C is an enlarged waveform diagram of the I +1 th frame of fig. 10A. Referring to fig. 10A, 10B and 10C, similarly, the pulse diagram includes a vertical synchronization Signal (Vsync), a horizontal synchronization Signal (Hsync), a write timing 1001, a read timing 1002, a red LED on Signal (R-LED on)1003, a green LED on Signal (G-LED on)1004, a blue LED on Signal (B-LED on)1005 and partial Gate Driving signals (Gate Driving signals) G1-G5. In addition, in this embodiment, since the driving manner of the I-th frame time is the same as that in the second embodiment, the driving manner of the I-th frame time in the following embodiments is not repeated, and the description starts directly from the driving manner of the I + 1-th frame time.
In the I +1 th frame time, when the horizontal synchronization signal is enabled, i.e. when the horizontal synchronization signal is at a logic high voltage, the write timing 1001 is enabled, and the memory starts to be written with the display information of the next frame, i.e. the display information of the I +2 th frame, wherein during the I +1 th frame, only the pixel information in the odd scan lines of the I +2 th frame is written into the odd frame memory region 701, and the even frame memory region 702 does not perform the refresh operation.
Next, please refer to the read timing 1002, the red led lighting signal 1003, and the gate driving signals G1-G5. When the red led lighting signal 1003 is enabled, the red pixel information (R1 to Rn) of the even scan lines L2, L4, and L6.. Lm in the even frame memory region 702 is read out, respectively. When the gate driving signal of the gate G1 is enabled, the source driver 602 converts the read red pixel information (R1-Rn) of the second scan line L2 into the corresponding column pixel information voltage in cooperation with an entire column switch turned on by the gate driving signal G1; when the gate driving signals of the gates G2 and G3 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the fourth scan line L4 into corresponding column pixel information voltages in cooperation with the two column switches turned on by the gate driving signals G2 and G3; when the gate driving signals of the gates G4 and G5 are enabled simultaneously, the source driver 602 converts the read red pixel information (R1 to Rn) of the sixth scan line L6 into corresponding column pixel information voltages in cooperation with the two column switches turned on by the gate driving signals G4 and G5; .., and so on below.
Next, during the enabling period of the green led lighting signal 1004 or the blue led lighting signal 1005, the green pixel information (G1 to Gn) or the blue pixel information (B1 to Bn) of the even scan lines L2, L4, L6.. Lm in the even frame memory region 702 are read out respectively, and the subsequent operations are the same as the red led lighting signal, which is not described herein again.
In summary, the scan lines are divided into odd scan lines and even scan lines, and the same memory space is shared by time division multiplexing. When the image information of the odd scanning lines is taken out from the frame memory and displayed on the display panel, the image information of the even scanning lines in the next picture is written. When the image information of the even scanning lines is taken out from the frame memory and displayed on the display panel, the image information of the odd scanning lines in the next picture is written. Therefore, the invention can reduce the capacity requirement of the frame memory needed by driving the field sequential flat panel display, and only needs half of the capacity of the traditional mode to realize the driving.
In addition, as the demand for the frame memory built in the display driver is reduced, the dynamic power consumption of the display driver is also reduced.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (14)
1. A driving method of a field sequential flat panel display, the field sequential flat panel display comprising an even number of frames, each frame consisting of pixels corresponding to a red light source, a blue light source and a green light source, the driving method comprising:
a. storing the pixel information of odd scanning lines in an odd frame memory area and storing the pixel information of even scanning lines in an even frame memory area;
b. during the I frame, when the pixel information of the odd scanning lines is taken out from the odd frame memory area and displayed on the field sequential flat panel display, the pixel information of the even scanning lines in the I +1 frame is written into the even frame memory area; and
c. during the I +1 th frame, when the pixel information of the even scanning lines is taken out from the even frame memory area and displayed on the field sequential flat panel display, writing the pixel information of the odd scanning lines in the I +2 th frame into the odd frame memory area, wherein I is a natural number;
in step b, the odd frame memory area is not updated, and in step c, the even frame memory area is not updated.
2. The driving method according to claim 1, characterized in that the method further comprises: during the I frame, the updated pixel information of the even number scanning lines is taken out from the even number frame memory area and displayed on the field sequential flat panel display; and
and during the I +1 th frame, the updated pixel information of the odd scanning lines is taken out from the odd frame memory area and displayed on the field sequential flat panel display.
3. The driving method according to claim 2, wherein during the I-th frame, the pixel information of the odd scan lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display, wherein when one of the red, blue or green light source is enabled, the pixel information of the corresponding color in the odd scan lines is fetched from the odd frame memory area, and when the gate is enabled, the fetched pixel information of the corresponding odd scan lines is converted into the corresponding column pixel information voltage according to an odd column gate driving signal; and
during the I frame, taking out the updated pixel information of the even scanning lines from the even frame memory area and displaying the pixel information on the field sequential flat panel display, wherein when one of the red light source, the blue light source or the green light source is enabled, the pixel information of the corresponding color of the even scanning lines is taken out from the even frame memory area, and when the grid is enabled, the read out pixel information of the corresponding even scanning lines is converted into the corresponding column pixel information voltage according to an even column grid driving signal;
during the I +1 th frame, taking out the updated pixel information of the even scan lines from the even frame memory area and displaying the pixel information on the field sequential flat panel display, wherein when one of the red light source, the blue light source or the green light source is enabled, the pixel information of the corresponding color of the even scan lines in the even frame memory area is read out, and when the grid is enabled, the read out pixel information of the corresponding even scan lines is converted and output to the corresponding column pixel information voltage according to an even column grid driving signal; and
and during the I +1 th frame, taking out the updated pixel information of the odd scan lines from the odd frame memory area and displaying the pixel information on the field sequential flat panel display, wherein when one of the red light source, the blue light source or the green light source is enabled, the pixel information of the corresponding color of the odd scan lines in the odd frame memory area is read out, and when the gate is enabled, the read out pixel information of the corresponding odd scan lines is converted and output as the corresponding column pixel information voltage according to the odd column gate driving signal.
4. The driving method as claimed in claim 1, wherein the field sequential flat panel display comprises an even number of gate lines, and when one of the red light source, the blue light source or the green light source is enabled, pixel information in the odd frame memory area and the even frame memory area is fetched in accordance with a sequence of gate line driving to drive the field sequential flat panel display.
5. The driving method according to claim 4, wherein the step b includes:
sequentially enabling the gate driving signals when the red light source is enabled; wherein,
when the grid driving signal of the 2n +1 grid line is enabled, taking out the 2n +1 red information from the odd frame memory area to drive the 2n +1 scanning line of the field sequential flat panel display;
when the grid drive signal of the 2n +2 grid lines is enabled, taking out the 2n +2 red information from the even frame memory area to drive the 2n +2 scanning lines of the field sequential flat panel display;
sequentially enabling the gate driving signals when the green light source is enabled; wherein,
when the grid drive signal of the 2n +1 grid line is enabled, the 2n +1 green information is taken out from the odd frame memory area so as to drive the 2n +1 scanning line of the field sequential flat panel display;
when the grid drive signal of the 2n +2 grid lines is enabled, the 2n +2 green information is taken out from the even frame memory area so as to drive the 2n +2 scanning lines of the field sequential flat panel display;
sequentially enabling the gate driving signals when the blue light source is enabled; wherein,
when the grid driving signal of the 2n +1 grid line is enabled, the 2n +1 blue information is taken out from the odd frame memory area so as to drive the 2n +1 scanning line of the field sequential flat panel display; and
when the grid drive signal of the 2n +2 grid lines is enabled, the 2n +2 blue information is taken out from the even frame memory area to drive the 2n +2 scanning lines of the field sequential flat panel display, wherein n is a natural number;
the step c comprises the following steps:
sequentially enabling the gate driving signals when the red light source is enabled; wherein,
when the grid drive signal of the 2n +1 grid line is enabled, the 2n +1 red information is taken out from the odd frame memory area so as to drive the 2n +1 scanning line of the field sequential flat panel display;
when the grid drive signal of the 2n +2 grid lines is enabled, the 2n +2 red information is taken out from the even frame memory area so as to drive the 2n +2 scanning lines of the field sequential flat panel display;
sequentially enabling the gate driving signals when the green light source is enabled; wherein,
when the grid drive signal of the 2n +1 grid line is enabled, the 2n +1 green information is taken out from the odd frame memory area so as to drive the 2n +1 scanning line of the field sequential flat panel display;
when the grid drive signal of the 2n +2 grid lines is enabled, the 2n +2 green information is taken out from the even frame memory area so as to drive the 2n +2 scanning lines of the field sequential flat panel display;
sequentially enabling the gate driving signals when the blue light source is enabled; wherein,
when the grid driving signal of the 2n +1 grid line is enabled, the 2n +1 blue information is taken out from the odd frame memory area so as to drive the 2n +1 scanning line of the field sequential flat panel display; and
when the grid drive signal of the 2n +2 grid lines is enabled, the 2n +2 blue information is taken out from the even frame memory area to drive the 2n +2 scanning lines of the field sequential flat panel display, wherein n is a natural number.
6. The driving method according to claim 1, wherein the step b comprises:
when one of the red light source, the blue light source or the green light source is enabled, the pixel information of the odd scanning lines is read out from the odd frame memory area, and is converted into corresponding row pixel information voltage according to two sequential grid driving signals.
7. The driving method as claimed in claim 6, wherein during the I +1 th frame, when the pixel information of the even scan lines is fetched from the even frame memory area and displayed on the field sequential flat panel display, if one of the red light source, the blue light source or the green light source is enabled, the pixel information of the corresponding color in the even scan lines in the even frame memory area and the first scan lines in the odd frame memory area are read out, and the pixel information of the first scan lines read out in the odd frame memory area is converted and outputted as the corresponding column pixel information voltages according to a first gate driving signal, and the pixel information of the corresponding even scan lines read out in the even frame memory area is converted and outputted as the corresponding column pixel information voltages according to two sequential gate driving signals except the first gate driving signal And (4) information voltage.
8. The driving method according to claim 6, wherein during the I-th frame, when pixel information of the odd scan lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display,
sequentially enabling the gate driving signals during the red light source enabling period, wherein the gate driving signal of the 2n +1 th gate line and the gate driving signal of the 2n +2 th gate line are enabled simultaneously;
when the gate drive signals of the 2n +1 th gate line and the 2n +2 th gate line are enabled, the red pixel information of the 2n +1 th scanning line is taken out from the odd frame memory area so as to drive the 2n +1 th scanning line and the 2n +2 th scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the green light source enabling period, wherein the gate driving signal of the 2n +1 th gate line and the gate driving signal of the 2n +2 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +1 th gate line and the 2n +2 th gate line are enabled, taking out green pixel information of the 2n +1 th scanning line from the odd frame memory region to drive the 2n +1 th scanning line and the 2n +2 th scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the enabling period of the blue light source, wherein the gate driving signal of the 2n +1 th gate line and the gate driving signal of the 2n +2 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +1 th gate line and the 2n +2 th gate line are enabled, the 2n +1 th blue pixel information is fetched out from the odd frame memory region to drive the 2n +1 th scan line and the 2n +2 th scan line of the field sequential flat panel display, wherein n is a natural number.
9. The driving method according to claim 6, wherein during the I +1 th frame, when the pixel information of the even scan lines is fetched from the even frame memory area and displayed on the field sequential flat panel display,
sequentially enabling the gate driving signals during the red light source enabling period, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, red pixel information of the 2n +2 th scanning line is taken out from the even frame memory area to drive the 2n +2 th scanning line and the 2n +3 th scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the green light source enabling period, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, taking out green pixel information of the 2n +2 th scanning line from the even frame memory area to drive the 2n +2 th scanning line and the 2n +3 th scanning line of the field sequential flat panel display;
sequentially enabling gate driving signals of gate lines during a blue light source enabling period, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously; and
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, the blue pixel information of the 2n +2 th scan line is fetched out from the even frame memory region to drive the 2n +2 th scan line and the 2n +3 th scan line of the field sequential flat panel display, wherein n is a natural number.
10. The driving method according to claim 9, wherein the gate driving signals are sequentially enabled during the red, green or blue light source enabling period, wherein when the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are simultaneously enabled,
enabling a gate driving signal of a first scanning line to extract corresponding red pixel information, green pixel information or blue pixel information in the first scanning line from the odd frame memory region, and driving the first scanning line of the field sequential flat panel display.
11. The driving method according to claim 6, wherein, during the I +1 th frame, when the pixel information of the even number scanning lines is taken out from the even number frame memory area and displayed on the field sequential flat panel display, if one of the red light source, the blue light source or the green light source is enabled, the pixel information corresponding to the even number of scanning lines in the even frame memory area is read out, and when the grid is enabled, converting and outputting pixel information corresponding to a first scanning line in the even frame memory region into a corresponding column pixel information voltage according to a first gate driving signal, and converting and outputting the pixel information corresponding to the even scanning lines in the even frame memory region into corresponding column pixel information voltages according to other two sequential gate driving signals except the first gate driving signal.
12. The driving method as claimed in claim 6, wherein during the I +1 th frame, when the pixel information of the even scan lines is fetched from the even frame memory area and displayed on the field sequential flat panel display,
sequentially enabling the gate driving signals during the red light source enabling period, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, red pixel information of the 2n +4 th scanning line is taken out from the even frame memory area to drive the 2n +2 th scanning line and the 2n +3 th scanning line of the field sequential flat panel display;
sequentially enabling gate driving signals of the gate lines during the green light source enabling period, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously;
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, the green pixel information of the 2n +4 th scanning line is taken out from the even frame memory area to drive the 2n +2 th scanning line and the 2n +3 th scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the enabling period of the blue light source, wherein the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously; and
when the gate driving signals of the 2n +2 th gate line and the 2n +3 th gate line are enabled, the blue pixel information of the 2n +4 th scan line is fetched out from the even frame memory region to drive the 2n +2 th scan line and the 2n +3 th scan line of the field sequential flat panel display, wherein n is a natural number.
13. The driving method according to claim 12, wherein the gate driving signals are sequentially enabled during the red light source enabling period, wherein when the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are simultaneously enabled,
enabling a grid driving signal of a first scanning line, and taking out red pixel information of a second scanning line from the even frame memory region when the grid driving signal of the first scanning line is enabled so as to drive the first scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the green light source enabling period, wherein when the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are simultaneously enabled,
enabling a grid driving signal of a first scanning line, and taking out green pixel information of a second scanning line from the even frame memory region when the grid driving signal of the first scanning line is enabled so as to drive the first scanning line of the field sequential flat panel display;
sequentially enabling the gate driving signals during the enabling period of the blue light source, wherein when the gate driving signal of the 2n +2 th gate line and the gate driving signal of the 2n +3 th gate line are enabled simultaneously,
enabling the grid driving signal of the first scanning line, and taking out the blue pixel information of the second scanning line from the even frame memory region when the grid driving signal of the first scanning line is enabled so as to drive the first scanning line of the field sequential flat panel display.
14. The driving method according to claim 1, wherein the field sequential flat panel display includes a horizontal synchronization signal, and the pixel information in the even frame memory area is updated during the I-th frame when the horizontal synchronization signal is enabled; and
updating pixel information in the odd frame memory area when the horizontal synchronization signal is enabled during the I +1 th frame.
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| CN103247278B (en) * | 2013-04-28 | 2015-08-19 | 京东方科技集团股份有限公司 | Frame scan pixel display driver unit and driving method, display device |
| CN105118448A (en) * | 2015-07-01 | 2015-12-02 | 深圳市华星光电技术有限公司 | Display panel and driving method |
| CN113611253B (en) * | 2020-07-29 | 2022-11-01 | 义隆电子股份有限公司 | Driving device and control method of display |
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