CN102087826B - Driving method of field sequential flat panel display - Google Patents

Abstract

The invention discloses a driving method of a field sequential flat panel display, dividing scanning lines into odd scanning lines and even scanning lines, sharing the same memory space by utilizing a time division multiplexing mode, wherein when image information of the odd scanning lines is taken out from a frame memory and displayed on a display panel, the image information of the even scanning lines in the next frame is written in, and when the image information of the even scanning lines is taken out from the frame memory and displayed on the display panel, the image information of the odd scanning lines in the next frame is written in. The method disclosed by the invention can reduce the capacity requirement of the frame memory by half.

Description

Driving method of field sequential flat panel display

technical field

The invention relates to a driving technology of a liquid crystal flat panel display, and more specifically, the invention relates to a driving method of a field sequential flat panel display which reduces memory requirements.

Background technique

Fig. 1 is the schematic diagram of the connection of source driver circuit (Source Driver Circuit) and display panel (Panel) of existing liquid crystal display (LCD), wherein, liquid crystal display 10 comprises a display panel 11, even information lines 12 and a source The pole driving circuit 13, and the display panel 11 include two-dimensional matrix pixels (pixel) 20, each pixel 20 includes a red sub-pixel (sub-pixel) 21, a green sub-pixel 22 and a blue sub-pixel 23, these The information lines 12 respectively control the actions of the red sub-pixel 21 , the green sub-pixel 22 and the blue sub-pixel 23 . The current driving method of the liquid crystal display 10 is to drive the red sub-pixel 21 , the green sub-pixel 22 and the blue sub-pixel 23 on the display panel 11 respectively by the source driving circuit 13 of the driving device. However, as many columns of sub-pixels as the display panel 11 has, there must be as many information lines to drive, and the source driving circuit 13 provides corresponding driving signals. In addition, the liquid crystal display 10 must be equipped with a color filter (Color Filter) (not shown) as red, green, blue light filtering, so the manufacturing cost of the liquid crystal display 10 is quite high.

FIG. 2 is a schematic diagram of the connection between the source driving circuit and the display panel of another conventional display. As shown in the figure, the conventional display 10a includes a display panel 11a, an even number of information lines 12a, and a source driving circuit 13a. The display panel 11a includes pixels 20a in a two-dimensional matrix, and each pixel 20a includes a red light emitting unit 21a, a green light emitting unit 22a, and a blue light emitting unit 23a, wherein the light emitting unit can be, for example, a light emitting diode (LED). The source driving circuit 13a of the display 10a adopts time field sharing technology to reduce the number of output driving signals of the information lines.

The so-called time-field segmentation technology refers to lighting red, blue and green respectively in each frame (frame), for example, first lighting the red light emitting unit 21a to turn the screen red, and then turning on the green light emitting unit 22a to make the screen turn red. The screen turns green, and then the blue light-emitting unit 23a is turned on to make the screen turn blue. Its operating principle is mainly based on the characteristics of the human eye's visual persistence (Visual staying phenomenon), which makes the user feel like a color picture when viewing the display. Since the display 10a uses the time-field division technology, the number of information lines required is only 1/3 of the number of information lines of the display 10a, and there is no need to match color filters, which can greatly reduce the manufacturing cost.

FIG. 3 is a timing diagram (Timing Chart) of signals used to drive the display in FIG. 2 . As shown in FIG. 3 , the source driving circuit 13 a is used for receiving a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync). During one frame T of the display screen, the output signal (Sout) of the source driving circuit 13a is divided into three subframes for respectively lighting the red light emitting unit 21a, the green light emitting unit 22a and the blue light emitting unit 23a. Since the red light emitting unit 21a, the green light emitting unit 22a and the blue light emitting unit 23a are respectively turned on, and each subframe needs the same number of trigger signals of the horizontal synchronization signal, the frequency of the horizontal synchronization signal is increased by 3 times.

Since the display time of the three primary colors of red, green, and blue is time-divided, the entire image information of the three primary colors must be stored in advance. And because the display is separated by red, green, and blue, the memory space required to store the image signal of the full screen must be twice the image resolution capacity to be able to write the image of an odd number of scanning lines in the next screen. information.

FIG. 4 is a schematic diagram of a frame memory required by a conventional method for driving a field sequential liquid crystal display panel. Please refer to FIG. 4 , the frame memory 401 is used to store frame information. Wherein, there are two frame memories 401 in the conventional field sequential liquid crystal display panel. FIG. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method. FIG. 5B is an enlarged waveform diagram of frame I of FIG. 5A. FIG. 5C is an enlarged waveform diagram of frame I+1 in FIG. 5A . Please refer to FIG. 5A , FIG. 5B and FIG. 5C . It can be seen from the above access sequence diagrams that the information of the next frame to be displayed is written into the frame memory at each horizontal synchronization (Hsync) time L ₁ -L _m . In addition, red L ₁ (R ₁ ～R _n )～L _m (R ₁ ～R _n ), green L ₁ (G ₁ ～G _n )～L _m (G ₁ ～G _n ) or blue L ₁ (B ₁ ～B _n )～L _m (B ₁ ～B _n ) display information.

Therefore, there must be two frame memories 401 in the traditional field sequential liquid crystal display panel, which are respectively used to store the display information in the current frame (frame I) and the adjacent next frame (frame I+1). , the capacity requirement of the frame memory in the prior art is relatively large.

Contents of the invention

In view of this, the present invention provides a method for driving a field sequential flat panel display, so as to reduce the capacity requirement of the frame memory by half.

The present invention provides a driving method of a field sequential flat display. The field sequential flat display includes an even number of frames, and each frame includes pixels corresponding to a red light source, a blue light source and a green light source respectively. The driving method includes the following steps : a. store the pixel information of odd scanning lines in an odd frame memory area, store the pixel information of even scanning lines in an even frame memory area; b. during the I frame period, when the pixel information of odd scanning lines is stored When taken out from the above-mentioned odd-numbered frame memory area and displayed on the above-mentioned field sequential flat display, write the pixel information of the even-numbered scanning lines of the I+1th frame into the above-mentioned even-numbered frame memory area; and c. at the I+1th During the frame period, when the pixel information of the above-mentioned even-numbered scanning lines is taken out from the above-mentioned even-numbered frame memory area and displayed on the above-mentioned field sequential flat panel display, the pixel information of the odd-numbered scanning lines of the I+2 frame is written into the above-mentioned odd-numbered frames Memory area, wherein, I is a natural number.

It can be seen that, according to the technical solution provided by the present invention, the scanning lines are divided into odd scanning lines and even scanning lines, and the same memory space is shared by means of time division multiplexing. When the odd scan lines are fetched from the frame memory and displayed on the display panel, the image information of the even scan lines of the next frame is written. When the even scanning lines are fetched from the frame memory and displayed on the display panel, the image information of the odd scanning lines of the next frame is written. Therefore, the present invention can reduce the capacity requirement of the frame memory required to drive the field sequential flat panel display, and only need half the capacity of the traditional method to realize the driving.

Furthermore, since the built-in frame memory of the display driver is less required, the dynamic power consumption of the display driver is relatively reduced.

Description of drawings

FIG. 1 is a schematic diagram of a connection between a source driving circuit of a conventional liquid crystal display and a display panel.

FIG. 2 is a schematic diagram of the connection between the source driving circuit and the display panel of another conventional display.

FIG. 3 is a conventional timing diagram of signals used to drive the display of FIG. 2 .

FIG. 4 is a schematic diagram of two sets of frame memories required by a conventional method for driving a field sequential liquid crystal display panel.

FIG. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method.

FIG. 5B is an enlarged waveform diagram of frame I of FIG. 5A.

FIG. 5C is an enlarged waveform diagram of frame I+1 in FIG. 5A .

FIG. 6 is a schematic diagram of the system structure of the field sequential flat panel display of the present invention.

FIG. 7 is a configuration diagram of the frame memory 605 of the present invention.

FIG. 8A is a clock waveform diagram of the driving method of the flat panel display according to the first embodiment of the present invention.

FIG. 8B is an enlarged waveform diagram of frame I of FIG. 8A.

Figure 8C is an enlarged waveform diagram of the I+1th frame of Figure 8A.

FIG. 9A is a clock waveform diagram of the driving method of the flat panel display according to the second embodiment of the present invention.

FIG. 9B is an enlarged waveform diagram of frame I of FIG. 9A.

FIG. 9C is an enlarged waveform diagram of frame I+1 in FIG. 9A .

FIG. 10A is a clock waveform diagram of a driving method of a flat panel display according to a third embodiment of the present invention.

FIG. 10B is an enlarged waveform diagram of frame I of FIG. 10A.

FIG. 10C is an enlarged waveform diagram of frame I+1 in FIG. 10A .

[Description of main component symbols]

10: LCD display

10a: Display

11, 11a: display panel

12, 12a: Information line

13, 13a: Source drive circuit

20: Pixels

21: Red sub-pixel

21a: Red light emitting unit

22: Green sub-pixel

22a: Green light emitting unit

23: blue sub-pixel

23a: blue light-emitting unit

401: frame memory

601: display panel

602: Source driver

603: Gate Driver

604: timing controller

605: frame memory

701: Odd frame memory area

702: Even frame memory area

801, 901, 1001: Write timing

802, 902, 1002: read timing

803, 903, 1003: red light-emitting diode lighting signal (R-LED)

804, 904, 1004: Green light-emitting diode lighting signal (G-LED)

805, 905, 1005: blue light-emitting diode lighting signal (B-LED)

G1～G5: Gate Driving Signal

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the solutions of the present invention will be further described in detail below with reference to the accompanying drawings and examples.

FIG. 6 is a schematic diagram of the system structure of the field sequential flat panel display of the present invention. Please refer to FIG. 6 , the flat panel display includes a display panel 601 , a source driver 602 , a gate driver 603 and a timing controller 604 , wherein the timing controller 604 includes a frame memory 605 .

When a single pixel in the display panel 601 wants to display color, one pin of the gate driver 603 needs to be used to control the thin film transistor switch, and three pins of the source driver 602 are used to input three primary color signals of R, G, and B. In addition, for the convenience of description, unless otherwise specified, the switches described below refer to thin film transistor switches. The gate driver 603 is responsible for switching the signals of each column of the display. When the display is scanning one column at a time and column by column, the gate driver 603 cooperates to open a whole column of switches, allowing the source driver 602 to perform signal input operations. The source driver 602 is responsible for the input of pixel signals in each row of the display. When the gate driver 603 turns on a whole column of switches, the source driver 602 immediately cooperates to output the pixel information voltage of the column to provide the required signal for the display screen.

The timing controller 604 is used to coordinate the actions of the entire display, to match the display timing of each frame, on the one hand, to set the activation of the horizontal scanning lines, and to control the gate driver 603 to output an appropriate voltage for a specific row of switches. On the other hand, the timing controller 604 receives an external input signal, converts the received video information into a digital signal required by the source driver 602, and cooperates with the opening of the horizontal scanning line to set the timing of driving the vertical scanning line, and then The source driver 602 is controlled to output the voltage of the pixel information.

FIG. 7 is a configuration diagram of the frame memory 605 of the present invention. Please refer to FIG. 7, the frame memory is divided into two parts, the odd frame memory area 701 and the even frame memory area 702, wherein the above odd frame memory area 701 is used to store red, green and blue colors in the odd scan lines Pixel information, and the even frame memory area 702 are used to store red, green and blue pixel information in even scan lines.

In the following, the technical solution of the invention will be introduced in detail through three embodiments.

first embodiment

FIG. 8A is a clock waveform diagram of the driving method of the field sequential flat panel display according to the first embodiment of the present invention. FIG. 8B is an enlarged waveform diagram of frame I of FIG. 8A. FIG. 8C is an enlarged waveform diagram of frame I+1 in FIG. 8A . Please refer to FIG. 8A, FIG. 8B and FIG. 8C, this pulse waveform diagram includes vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), write timing 801, read timing 802, red LED lighting signal (R- LED) 803, a green LED lighting signal (G-LED) 804, a blue LED lighting signal (B-LED) 805, and a gate driving signal (Gate Driving Signal), such as G1-G5 as an example. Wherein, the vertical synchronous signal and the horizontal synchronous signal are signals used by an external signal source for synchronizing the display. The enabling period of the vertical synchronizing signal is used to indicate the time during which a frame can be displayed, and the period during which the horizontal synchronizing signal is enabled indicates the time during which the information of one horizontal scanning line can be output. The enabled period of the write timing 801 indicates a period during which the timing controller 604 writes information into the odd frame memory area 701 or the even frame memory area 702 . The enable period of the read sequence 802 indicates that the source driver 602 cooperates with the turned-on horizontal scanning line to output the voltage of the corresponding column pixel information. The enabled periods of the red LED lighting signal 803 , the green LED lighting signal 804 , and the blue LED lighting signal 805 indicate the periods when the red, green and blue backlight sources are turned on, respectively. The gate driving signals G1 - G5 are the outputs of the gate driver 603 , and are used to respectively turn on a corresponding row of switches in the liquid crystal matrix.

At the time of the I frame, as shown in the figure, during the I frame, every time the horizontal synchronization signal is enabled, that is, when the horizontal synchronization signal is a logic high voltage, the write sequence 801 is enabled, and the memory starts to be written into the next The display information of one frame, that is, the display information written in the I+1th frame. More specifically, during the I frame period, only the pixel information of the even scan lines in the next frame (frame I+1) is written to the even frame memory area 702, wherein the odd frame memory area 701 is not renew. Next, please refer to the reading sequence 802, the red LED lighting signal 803, and the gate driving signals (Gate Driving Signal) G1-G5. When the red light emitting diode lighting signal 803 is enabled, the red pixel information ( R1 ˜ Rn ) of the odd scanning lines L1 , L3 , L5 . . . Lm−1 in the odd frame memory area 701 is read out. Moreover, when the odd-numbered column gate drive signals are enabled, the source driver 602 cooperates with a whole column of switches opened by the odd-numbered column gate drive signals to convert and output the read red pixel information into corresponding column pixel information The source driver 602 drives the vertical scanning lines in accordance with the opening time of the horizontal scanning lines corresponding to the driving gates, thereby providing the required signals for displaying images.

In addition, during the enabling period of the red light-emitting diode lighting signal 803 in the same frame time (I frame period in the figure), when the even-numbered column gate driving signals of the gates G2, G4... are enabled , then the red pixel information of even-numbered scan lines L2, L4...Lm in the even-numbered frame memory area 702 is read out respectively, and the source driver 602 cooperates with a whole column of switches opened by the even-numbered column gate drive signal to The read red pixel information is converted and outputted as a corresponding column pixel information voltage, so as to provide signals required for displaying images.

Similarly, when the green light-emitting diode lighting signal 804 is enabled, the green pixel information (G1-Gn) of the odd-numbered scanning lines L1, L3, L5...Lm-1 in the odd-numbered frame memory area 701 are read respectively. take out. Moreover, when the odd-numbered column gate drive signals of the gate are enabled, the source driver 602 cooperates with a whole column of switches opened by the odd-numbered column gate drive signals to convert and output the read green pixel information into corresponding Column pixel information voltage. In addition, during the enabling period of the green light-emitting diode lighting signal 804 in the same frame time (the I frame period in the figure), when the even-numbered column gate driving signal is enabled, the even-numbered frames of the even-numbered frame memory area 702 The green pixel information (G1-Gn) of the scanning lines L2, L4...Lm are respectively read out, and the source driver 602 cooperates with a whole column of switches turned on by the even-numbered column gate driving signals to read the information The green pixel information is converted and output to the corresponding column pixel information voltage to provide the required signal for displaying the picture.

In the same way, when the blue light-emitting diode lighting signal 805 is enabled, the blue pixel information (B1～Bn) of the odd scanning lines L1, L3, L5...Lm-1 in the odd frame memory area 701 respectively is read out. Moreover, when the odd-numbered column gate driving signals are enabled, the source driver 602 cooperates with a whole column of switches opened by the odd-numbered column gate driving signals G1, G3, G5... to read out the blue pixel information Convert and output to the corresponding column pixel information voltage.

In addition, during the enabling period of the blue light-emitting diode lighting signal 805 in the same frame time (the I frame period in the figure), when the even-numbered column gate driving signal is enabled, the even-numbered frame memory area 702 The blue pixel information (B1-Bn) of the even-numbered scanning lines L2, L4...Lm are respectively read out, and the source driver 602 cooperates with one of the even-numbered column gate drive signals G2, G4... The entire column switch converts the read blue pixel information and outputs it as a corresponding column pixel information voltage.

To sum up, when the red, green or blue even-numbered scanning lines are driven, the even-numbered frame memory area 702 is also being updated at the same time, therefore, a certain part of the information taken out may be the updated information . However, since the difference between the current frame (frame I) and the next frame (frame I+1) is only 1/60 second, the difference between the pixels of the two frames before and after will not be obvious, and will hardly affect the display. image quality will be adversely affected.

Next, at the I+1th frame time, each time the horizontal synchronization signal Hsync is enabled, that is, when the horizontal synchronization signal Hsync is a logic high voltage, the write sequence 801 is enabled, and the memory will start to be written into the next The display information of the frame, that is, the display information of the I+2th frame. More specifically, during the I+1 frame period, only the pixel information of the odd scan lines in the next frame (I+2 frame) is written to the odd frame memory area 701, wherein the even frame memory area 702 does not Updated. Next, please refer to the reading sequence 802, the red LED lighting signal 803, and the gate driving signals (Gate Driving Signal) G1-G5.

When the red light emitting diode lighting signal 803 is enabled, the red pixel information ( R1 ˜ Rn ) of the even scan lines L2 , L4 , . . . Lm in the even frame memory area 702 is read out respectively. Moreover, when the gate driving signals of the even columns are enabled, the source driver 602 cooperates with a whole column of switches opened by the gate driving signals of the even columns G2, G4, ..., to convert and output the read red pixel information The source driver 602 drives the vertical scanning lines for the corresponding column pixel information voltages, that is, in conjunction with the turn-on time of the horizontal scanning lines corresponding to the driving gates G2 , G4 , G6 .

In addition, during the enabling period of the red light-emitting diode lighting signal 803 in the same frame time (the I+1th frame period in the figure), when the odd-numbered column gate drive signal is enabled, the odd-numbered frame memory area 701 The red pixel information (R1~Rn) of the odd-numbered scanning lines L1, L3...Lm-1 are read out respectively, and the source driver 602 cooperates with the odd-numbered column gate drive signals G1, G3, G5... A whole column of switches that is turned on converts the read red pixel information and outputs it as a corresponding column pixel information voltage, so as to provide the required signal for displaying the picture.

Similarly, when the green light emitting diode lighting signal 804 is enabled, the green pixel information of the even scan lines L2 , L4 , L6 . . . Lm in the even frame memory area 702 are read out respectively. Moreover, when the even-numbered column gate driving signals of gates G2, G4... are enabled, the source driver 602 cooperates with a whole column of switches opened by the even-numbered column gate driving signals G2, G4... The fetched green pixel information is converted and outputted as the corresponding column pixel information voltage.

In addition, during the enabling period of the green light-emitting diode lighting signal 804 in the same frame time (the I+1th frame period in the figure), when the odd-numbered column gate drive signals of the gates G1, G3, G5... When enabled, the green pixel information (G1~Gn) of the odd scan lines L1, L3...Lm-1 in the odd frame memory area 701 are read out respectively, and the source driver 602 cooperates with the odd column gate A whole column of switches turned on by the driving signals G1, G3, G5... converts the read green pixel information and outputs it as a corresponding column pixel information voltage, so as to provide the required signal for displaying the picture.

In the same way, when the blue light-emitting diode lighting signal 805 is enabled, the blue pixel information (B1-Bn) of the even-numbered scanning lines L2, L4, L6...Lm in the even-numbered frame memory area 702 are respectively read out. Moreover, when the even-numbered column gate driving signals of gates G2, G4... are enabled, the source driver 602 cooperates with a whole column of switches opened by the even-numbered column gate driving signals G2, G4... The extracted blue pixel information is converted and output as a corresponding column pixel information voltage.

In addition, during the enabling period of the blue light-emitting diode lighting signal 805 in the same frame time (the I+1th frame period in the figure), when the odd-numbered columns of gates G1, G3, G5... are driven When the signal is enabled, the blue pixel information (B1~Bn) of the odd scanning lines L1, L3, L5... A whole column of switches turned on by the gate driving signals G1, G3, G5... converts the read blue pixel information and outputs it as a corresponding column pixel information voltage.

To further illustrate, in the I+1 frame time, when the driving behavior of the odd-numbered scanning lines of red, green or blue is being performed, the odd-numbered frame memory area 701 is also being updated, so a certain part of the fetched information , possibly updated information. However, since the difference between the current frame (frame I+2) and the next frame (frame I+2) is only 1/60 second, the difference between the pixels of the two frames before and after will not be obvious, and will hardly affect the display. image quality will be adversely affected.

To sum up, in the first frame time, only the even-numbered frame memory area 702 is updated, so that when the odd-numbered scanning lines corresponding to the gate are turned on, the source driver 603 will use the data stored in the odd-numbered frame memory area 701. The updated current frame is used as display information for . In the I+1th frame time, only the odd-numbered frame memory area 701 is updated, so that when the even-numbered scanning lines corresponding to the gate are turned on, the source driver 603 will use the unupdated data stored in the even-numbered frame memory area 502. The current frame of is used as display information. Since the time difference between the two frames is only 1/60 second, the difference between the pixels of the two frames will not be obvious. Therefore, the impact on the image quality of the display is negligible.

It can be seen that the present invention can reduce the capacity requirement of the frame memory required to drive the field sequential flat panel display, that is, only half of the frame memory used in the traditional method can be driven, wherein, in each frame time, only need to write Half of the pixel information is sent to the frame memory, thereby saving power.

second embodiment

9A is a clock waveform diagram of the driving method of the field sequential flat panel display in the second embodiment of the present invention, wherein FIG. 9B is an enlarged waveform diagram of the Ith frame of FIG. 9A, and FIG. 9C is the I+th frame of FIG. 9A Zoomed-in waveform diagram of 1 frame. Please refer to FIG. 9A, FIG. 9B and FIG. 9C. Similarly, this pulse waveform diagram includes vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), write sequence 901, read sequence 902, red LED lighting signal (R-LED on) 903, green light-emitting diode lighting signal (G-LED on) 904, blue light-emitting diode lighting signal (B-LED on) 905 and gate driving signal (Gate Driving Signal), such as G1～ G5.

During the I frame time (the I frame period in the figure), when the horizontal synchronization signal is enabled, that is, when the horizontal synchronization signal is a logic high voltage, the write sequence 901 is enabled, and the memory starts to be written into the next The display information of the frame (frame I+1). The same as the above-mentioned first embodiment, during the I frame period, only the pixel information of the even scan lines in the next frame (frame I+1) is written into the even frame memory area 702 . In addition, the odd frame memory area 701 is not updated.

Next, please refer to the reading sequence 902 , the red LED lighting signal 903 and the gate driving signals G1 - G5 . When the red light emitting diode lighting signal 903 is enabled, the red pixel information ( R1 ˜ Rn ) of the odd scan lines in the odd frame memory area 701 is read out respectively. When the gate driving signals of the gates G1 and G2 are enabled at the same time, the source driver 602 cooperates with the two columns of switches opened by the gate driving signals G1 and G2 to read the red pixel information ( R1～Rn) are converted and output as the corresponding column pixel information voltage; when the gate drive signals of the gates G3 and G4 are enabled at the same time, the source driver 602 cooperates with the two columns opened by the gate drive signals G3 and G4 The switch converts the read red pixel information (R1-Rn) of the scanning line L3 and outputs it as a corresponding column pixel information voltage, and the following operations are analogized like this.

Next, the actions of the green light-emitting diode and the blue light-emitting diode during the enable period are the same as those of the red light-emitting diode, which will not be repeated here.

At the I+1 frame time (the I+1 frame period in the figure), when the horizontal synchronization signal is enabled and the horizontal synchronization signal is a logic high voltage, the write sequence 901 is enabled, and the memory will The pixel information of the next frame starts to be written, that is, the pixel information of the I+2th frame. More specifically, during the I+1 frame period, only the pixel information of the odd scan lines in the I+2 frame is written into the odd frame memory area 701, and the even frame memory area 702 is not updated.

Next, please refer to the reading sequence 902, the red LED lighting signal 903, and the gate driving signals (Gate Driving Signal) G1-G5. When the red light-emitting diode lighting signal 903 is enabled, the red pixel information (R1-Rn) of the even-numbered scanning lines L2, L4, L6...Lm in the even-numbered frame memory area 702 are read out respectively, and read Take out the L1 of odd-numbered frame scan lines. When the gate drive signal of the gate G1 is enabled, the red pixel information (R1~Rn) of the first scan line L1 of the odd-numbered frame memory area 701 is read out respectively, and the source driver 602 cooperates with the gate A whole column of switches opened by the driving signal G1 converts the read red pixel information (R1~Rn) of the scanning line L1 and outputs it as the corresponding column pixel information voltage; when the gate driving signals of the gates G2 and G3 are simultaneously When enabled, the source driver 602 cooperates with the two column switches turned on by the gate drive signals G2 and G3 to convert and output the red pixel information (R1-Rn) of the scanning line L2 read out to the corresponding column Pixel information voltage; when the gate drive signals of gates G4 and G5 are enabled at the same time, the source driver 602 cooperates with the two columns of switches opened by the gate drive signals G4 and G5 to convert the read-out scan line L4 The red pixel information (R1-Rn) of the red pixel is converted and output as the corresponding column pixel information voltage; ... and so on.

Next, when the green LED lighting signal 904 and the blue LED lighting signal 905 are enabled, their actions are the same as those of the red LED lighting signal, and will not be repeated here.

In the first frame I+1 of the above embodiment, the pixel information in the first scanning line L1 stored in the odd-numbered frame memory area 701 is used as the display information of the gate G1, and the other gates G2, G3, G4.. . is to use the pixel information of the even scan lines L2, L4, L6...Lm in the even frame memory area 702.

third embodiment

FIG. 10A is a clock waveform diagram of the driving method of the field sequential flat panel display according to the third embodiment of the present invention. FIG. 10B is an enlarged waveform diagram of frame I of FIG. 10A. FIG. 10C is an enlarged waveform diagram of frame I+1 in FIG. 10A . Please refer to Figure 10A, Figure 10B and Figure 10C, similarly, this pulse waveform diagram includes vertical synchronization signal (Vsync), horizontal synchronization signal (Hsync), write timing 1001, read timing 1002, red LED lighting signal (R-LED on) 1003, green light-emitting diode lighting signal (G-LED on) 1004, blue light-emitting diode lighting signal (B-LED on) 1005 and part of gate driving signal (Gate Driving Signal) G1 ~G5. In addition, in this embodiment, since the driving method of the I-th frame time is the same as that of the second embodiment, in the following embodiments, the driving method of the I-th frame time will not be described in detail, and directly from the I+1th frame The drive of time begins the narrative.

At the I+1th frame time, when the horizontal synchronization signal is enabled, that is, when the horizontal synchronization signal is a logic high voltage, the write sequence 1001 is enabled, and the memory will start to be written into the display information of the next frame. That is, the display information of the I+2 frame, wherein, during the I+1 frame period, only write the pixel information in the odd scan lines of the I+2 frame to the odd frame memory area 701, and the even frame memory area 702 No update operation is performed.

Next, please refer to the reading sequence 1002 , the red LED lighting signal 1003 and the gate driving signals G1 - G5 . When the red light emitting diode lighting signal 1003 is enabled, the red pixel information ( R1 ˜ Rn ) of the even scan lines L2 , L4 , L6 . . . Lm in the even frame memory area 702 is read out. When the gate drive signal of the gate G1 is enabled, the source driver 602 cooperates with a whole column of switches opened by the gate drive signal G1 to read the red pixel information (R1 ~Rn) is converted and output as the corresponding column pixel information voltage; when the gate drive signals of the gates G2 and G3 are enabled at the same time, the source driver 602 cooperates with the two column switches opened by the gate drive signals G2 and G3 , convert and output the red pixel information (R1-Rn) of the fourth scanning line L4 read out above into the corresponding column pixel information voltage; when the gate drive signals of the gates G4 and G5 are enabled at the same time, The source driver 602 cooperates with the two column switches turned on by the gate drive signals G4 and G5 to convert and output the red pixel information (R1-Rn) of the sixth scanning line L6 read out into corresponding column pixel information Voltage; ... and so on.

Next, when the green light-emitting diode lighting signal 1004 or the blue light-emitting diode lighting signal 1005 are enabled, the green pixel information ( G1-Gn) or blue pixel information (B1-Bn) are read out respectively, and the subsequent actions are the same as the lighting signal of the red light-emitting diode, which will not be repeated here.

To sum up, the present invention divides the scan lines into odd scan lines and even scan lines, and uses time-division multiplexing to share the same memory space. When the image information of the odd scanning lines is fetched from the frame memory and displayed on the display panel, the image information of the even scanning lines in the next frame is written. When the image information of the even scanning lines is fetched from the frame memory and displayed on the display panel, the image information of the odd scanning lines in the next frame is written. Therefore, the present invention can reduce the capacity requirement of the frame memory required to drive the field sequential flat panel display, and only need half the capacity of the traditional method to realize the driving.

In addition, since the built-in frame memory of the display driver is less required, the dynamic power consumption of the display driver is relatively reduced.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (14)

1. A driving method of a field sequential flat display, wherein the field sequential flat display includes an even number of frames, and each frame is formed of pixels corresponding to a red light source, a blue light source and a green light source respectively, and it is characterized in that the The driving methods described above include: a. storing pixel information of odd scan lines in an odd frame memory area, and storing pixel information of even scan lines in an even frame memory area; b. During the I frame period, when the pixel information of the odd scan lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display, the even number in the I+1 frame is The pixel information of the scan lines is written into the even frame memory area; and c. During the I+1th frame period, when the pixel information of the even-numbered scanning lines is taken out from the even-numbered frame memory area and displayed on the field sequential flat-panel display, the information in the I+2th frame is The pixel information of the odd scan lines is written into the odd frame memory area, wherein, I is a natural number; In step b, the odd frame memory area will not be updated, and in step c, the even frame memory area will not be updated. 2. The driving method according to claim 1, characterized in that, the method further comprises: during the 1st frame, fetching the updated pixel information of the even scanning lines from the even frame memory area and displayed on said field sequential flat panel display; and During the I+1th frame period, the updated pixel information of the odd scanning lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display. 3. The driving method according to claim 2, wherein, during the first frame period, the pixel information of the odd scanning lines is taken out from the odd frame memory area and displayed in the field sequence type flat panel display, wherein, when one of the red light source, blue light source or green light source is enabled, the pixel information of the corresponding color in the odd numbered scan lines is fetched from the odd numbered frame memory area, and when When the gate is enabled, according to the odd-numbered column gate driving signal, the read pixel information of the corresponding odd-numbered scanning lines is converted into a corresponding column pixel information voltage; and During the first frame period, the updated pixel information of the even scanning lines is fetched from the even frame memory area and displayed on the field sequential flat panel display, wherein when the red light source, blue light source or When one of the green light sources is enabled, the pixel information of the corresponding color of the even-numbered scanning lines is taken out from the even-numbered frame memory area, and when the gate is enabled, according to the even-numbered column gate drive signal, the Converting the read pixel information of the corresponding even-numbered scanning lines into corresponding column pixel information voltages; During the I+1th frame period, the pixel information of the updated even scanning lines is fetched from the even frame memory area and displayed on the field sequential flat panel display, wherein when the red light source , when one of the blue light source or the green light source is enabled, the pixel information of the corresponding color of the even-numbered scanning lines in the even-numbered frame memory area is read out, and when the gate is enabled, according to the even A column gate drive signal, and then convert and output the read pixel information of the corresponding even-numbered scanning lines into a corresponding column pixel information voltage; and During the I+1th frame period, the updated pixel information of the odd scanning lines is fetched from the odd frame memory area and displayed on the field sequential flat panel display, wherein when the red light source When one of the blue light source or the green light source is enabled, the pixel information of the corresponding color of the odd scan lines in the odd frame memory area is read out, and when the gate is enabled, according to the The odd-numbered column gate driving signal, and then the read pixel information of the corresponding odd-numbered scanning lines is converted and output to the corresponding pixel information voltage of the column. 4. The driving method according to claim 1, wherein the field sequential flat panel display includes an even number of gate lines, and when one of the red light source, blue light source or green light source is enabled, according to In the sequence of gate line driving, the pixel information in the odd frame memory area and the even frame memory area is fetched to drive the field sequential flat panel display. 5. driving method according to claim 4, is characterized in that, above-mentioned b step comprises: When the red light source is enabled, the gate drive signals are enabled sequentially; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th red information is taken out from the odd frame memory area to drive the 2n+1th field sequential flat panel display scan lines; When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th red information is taken out from the even frame memory area to drive the 2n+2th field sequential flat panel display scan lines; When the green light source is enabled, the aforementioned gate drive signals are sequentially enabled; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th green information is taken out from the odd frame memory area to drive the 2n+1th green information of the field sequential flat panel display scan line; When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th green information is taken out from the even frame memory area to drive the 2n+2th green information of the field sequential flat panel display scan line; When the blue light source is enabled, the aforementioned gate drive signals are sequentially enabled; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th blue information is taken out from the odd frame memory area to drive the 2n+1th field sequential flat panel display scan lines; and When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th piece of blue information is taken out from the even frame memory area to drive the 2n+2th piece of the field sequential flat panel display Scanning lines, where n is a natural number; The above c steps include: When the red light source is enabled, the aforementioned gate drive signals are sequentially enabled; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th red information is taken out from the odd frame memory area to drive the 2n+1th piece of the field sequential flat panel display scan line; When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th red information is taken out from the even frame memory area to drive the 2n+2th piece of the field sequential flat panel display scan line; When the green light source is enabled, the aforementioned gate drive signals are sequentially enabled; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th green information is taken out from the odd frame memory area to drive the 2n+1th green information of the field sequential flat panel display scan line; When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th green information is taken out from the even frame memory area to drive the 2n+2th green information of the field sequential flat panel display scan line; When the blue light source is enabled, the aforementioned gate drive signals are sequentially enabled; wherein, When the gate driving signal of the 2n+1th gate line is enabled, the 2n+1th blue information is taken out from the odd frame memory area to drive the 2n+1th field sequential flat panel display scan lines; and When the gate driving signal of the 2n+2th gate line is enabled, the 2n+2th piece of blue information is taken out from the even frame memory area to drive the 2n+2th piece of the field sequential flat panel display scan lines, where n is a natural number. 6. driving method according to claim 1, is characterized in that, b step comprises: When one of the red light source, blue light source or green color light source is enabled, the pixel information of the odd scan lines is read out from the odd frame memory area, according to the sequence of two gate drive The signal is converted into the corresponding column pixel information voltage. 7. The driving method according to claim 6, characterized in that, during the I+1th frame period, when the pixel information of the even-numbered scanning lines is fetched from the even-numbered frame memory area and displayed on the When on a field sequential flat panel display, if one of the red light source, blue light source or green light source is enabled, the even scan lines in the even frame memory area and the first scan line in the odd frame memory area The pixel information of the corresponding color in the scanning lines is read out, and according to the first gate drive signal, the pixel information of the first scanning line read in the odd frame memory area is converted and output as The pixel information voltage of the corresponding column, and according to the other two sequential gate drive signals except the first gate drive signal, the pixels of the corresponding even scan lines read in the even frame memory area The information is converted and output as a corresponding column pixel information voltage. 8. The driving method according to claim 6, wherein, during the first frame, when fetching the pixel information of the odd scanning lines from the odd frame memory area and displaying them in the field sequence on a flat-panel display, During the enabling period of the red light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+1 gate line and the gate driving signal of the 2n+2 gate line are simultaneously controlled Enable; When the 2n+1th gate line and the gate drive signal of the 2n+2th gate line are enabled, the red pixel information of the 2n+1th scanning line is fetched from the odd frame memory area , to drive the 2n+1 scan line and the 2n+2 scan line of the field sequential flat panel display; During the enabling period of the green light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+1th gate line and the gate of the 2n+2th gate line The driving signal is enabled at the same time; When the gate drive signal of the 2n+1th gate line and the 2n+2th gate line is enabled, the green pixel of the 2n+1th scanning line is taken out from the odd frame memory area information, to drive the 2n+1 scan line and the 2n+2 scan line of the field sequential flat panel display; During the enabling period of the blue light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+1 gate line and the gate driving signal of the 2n+2 gate line are simultaneously activated Enable; When the gate drive signal of the 2n+1th gate line and the 2n+2th gate line is enabled, the blue pixel information of the 2n+1th gate line is fetched from the odd frame memory area , to drive the 2n+1th scanning lines and the 2n+2th scanning lines of the field sequential flat panel display, wherein n is a natural number. 9. The driving method according to claim 6, wherein during the I+1th frame period, when the pixel information of the even scanning lines is taken out from the even frame memory area and displayed on the When on a field sequential flat panel display, During the enabling period of the red light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2 gate line and the gate driving signal of the 2n+3 gate line are simultaneously controlled Enable; When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the red pixel of the 2n+2th scanning line is taken out from the even frame memory area information to drive the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display; During the enabling period of the green light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2th gate line and the gate of the 2n+3th gate line The driving signal is enabled at the same time; When the gate drive signals of the 2n+2 gate lines and the 2n+3 gate lines are enabled, the green pixels of the 2n+2 scan lines are taken out from the even frame memory area information to drive the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display; During the period when the blue light source is enabled, the gate driving signals of the gate lines are sequentially enabled, wherein the gate driving signal of the 2n+2 gate lines is the same as the gate driving signal of the 2n+3 gate lines pole drive signal is enabled at the same time; and When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the blue color of the 2n+2th scanning line is taken out from the even frame memory area Pixel information for driving the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display, wherein n is a natural number. 10. The driving method according to claim 9, characterized in that, during the enabling period of the red light source, green light source or blue light source, the aforementioned gate drive signals are sequentially enabled, wherein the 2n+2th When the gate driving signal of the gate line and the gate driving signal of the 2n+3th gate line are enabled at the same time, First enable the gate drive signal of the first scanning line to take out the corresponding red pixel information, green pixel information or blue pixel information in the first scanning line from the odd frame memory area, and then drive all The first scan line of the field sequential flat panel display. 11. The driving method according to claim 6, characterized in that, during the I+1th frame period, the pixel information of the even-numbered scanning lines is fetched from the memory area of the even-numbered frame and displayed in the field sequence When on a type flat-panel display, if one of the red light source, blue light source or green light source is enabled, the pixel information corresponding to the even-numbered scanning lines in the even-numbered frame memory area is read out, and when When the gate is enabled, according to the first gate driving signal, the pixel information corresponding to the first scan line in the even-numbered frame memory area is converted and output to the corresponding column pixel information voltage, and according to the division of the first The other two gate driving signals in sequence other than the gate driving signal convert and output the pixel information corresponding to the even scanning lines in the even frame memory area into corresponding column pixel information voltages. 12. The driving method according to claim 6, wherein during the I+1th frame period, when the pixel information of the even-numbered scanning lines is fetched from the even-numbered frame memory area and displayed on the field When on a sequential flat panel display, During the enabling period of the red light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2 gate line and the gate driving signal of the 2n+3 gate line are simultaneously controlled Enable; When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the red pixel of the 2n+4th scanning line is taken out from the even frame memory area information to drive the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display; During the enabling period of the green light source, the gate driving signals of the gate lines are sequentially enabled, wherein the gate driving signal of the 2n+2th gate line is the same as the gate driving signal of the 2n+3th gate line The signal is enabled at the same time; When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the green pixels of the 2n+4th scanning line are taken out from the even frame memory area information to drive the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display; During the enabling period of the blue light source, the aforementioned gate drive signals are sequentially enabled, wherein the gate drive signal of the 2n+2th gate line is the same as the gate of the 2n+3th gate line the drive signal is simultaneously enabled; and When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the blue color of the 2n+4th scanning line is taken out from the even frame memory area Pixel information for driving the 2n+2 scan lines and the 2n+3 scan lines of the field sequential flat panel display, wherein n is a natural number. 13. The driving method according to claim 12, characterized in that, during the enabling period of the red light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2th gate line When the gate drive signal of the 2n+3th gate line is enabled at the same time, First enable the gate drive signal of the first scan line, and when the gate drive signal of the first scan line is enabled, the red pixel information of the second scan line is taken out from the even frame memory area to drive the first scan line of the field sequential flat panel display; During the enabling period of the green light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2th gate line and the gate of the 2n+3th gate line When the drive signal is enabled simultaneously, the First enable the gate drive signal of the first scan line, and when the gate drive signal of the first scan line is enabled, the green pixel information of the second scan line is taken out from the even frame memory area to drive the first scan line of the field sequential flat panel display; During the enabling period of the blue light source, the aforementioned gate driving signals are sequentially enabled, wherein the gate driving signal of the 2n+2th gate line and the gate driving signal of the 2n+3th gate line are simultaneously activated When enabled, First enable the gate drive signal of the first scan line, and when the gate drive signal of the first scan line is enabled, the blue pixel information of the second scan line is taken out from the even frame memory area to and driving the first scan line of the field sequential flat panel display. 14. The driving method according to claim 1, wherein the field sequential flat panel display includes a horizontal synchronous signal, during the first frame, when the horizontal synchronous signal is enabled, update the pixel information in even frame memory regions; and During the I+1th frame period, when the horizontal synchronization signal is enabled, the pixel information in the memory area of the odd frame is updated.

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