TWI436326B - Driving method for field sequential flat panel display - Google Patents

Description

Field sequential flat panel display driving method

The present invention relates to a driving technique of a liquid crystal flat panel display. Further, the present invention relates to a driving method of a field sequential liquid crystal flat panel display which reduces memory requirements.

1 shows a schematic diagram of a connection between a source driver circuit and a display panel of a conventional liquid crystal display (LCD), wherein the liquid crystal display 10 includes a display panel 11, a plurality of data lines 12, and a The source driving circuit 13 and the display panel 11 include a pixel 20 of a two-dimensional matrix, each pixel 20 including a red sub-pixel 21, a green sub-pixel 22, and a blue sub-pixel 23. The data lines 12 control the operations of the red sub-pixel 21, the green sub-pixel 22, and the blue sub-pixel 23, respectively. The conventional liquid crystal display 10 is driven by the source driving circuit 13 of the driving device to respectively drive the red sub-pixel 21, the green sub-pixel 22, and the blue sub-pixel 23 on the display panel 11. However, how many rows of sub-pixels the display panel 11 has, how many data lines are required to be driven, and the source driving circuit 13 supplies the corresponding driving signals. In addition, the liquid crystal display 10 must be configured with a color filter as a filter of red, green, and blue, so that the manufacturing cost of the liquid crystal display 10 is relatively high.

FIG. 2 is a schematic diagram showing the connection of a source driving circuit of another conventional display and a display panel. As shown in the figure, the conventional display 10a includes a display panel 11a, a plurality of data lines 12a, and a source driving circuit 13a. The display panel 11a includes a two-dimensional matrix of pixels 20a. Each of the pixels 20a includes a red light emitting unit 21a, a green light emitting unit 22a, and a blue light emitting unit 23a. The light emitting unit may be, for example, a light emitting diode (LED). The source driving circuit 13a of the display 10a employs a time field sharing technique for reducing the number of driving signal outputs of the data lines.

The so-called time-field segmentation technique means that red, blue, and green lights are respectively illuminated for each frame, for example, the red light-emitting unit 21a is first turned on, the screen is turned red, and the green light-emitting unit 22a is turned on. The screen turns green, and then the blue light unit 23a is lit again to make the screen blue. The operation principle mainly relies on the characteristics of the visual staying phenomenon of the human eye, so that the user feels a color picture when viewing the display. Since the display 10a uses the time field segmentation technology, the total number of data lines required only needs 1/3 of the number of data lines of the display 10a, and the color filter is not required, which can greatly reduce the manufacturing cost.

Figure 3 shows a Timing Chart for driving the signal of the display of Figure 2. As shown in FIG. 3, the source driving circuit 13a is configured to receive a vertical sync signal (Vsync) and a horizontal sync signal (Hsync). During a frame T of the display screen, the output signal (Sout) of the source driving circuit 13a is divided into three sub-frames for respectively illuminating the red light-emitting unit 21a, the green light-emitting unit 22a, and the blue light-emitting unit 23a. Since the red light-emitting unit 21a, the green light-emitting unit 22a, and the blue light-emitting unit 23a are respectively illuminated, and each sub-frame requires the same number of horizontal sync signal trigger signals, the frequency of the horizontal sync signal is increased by three times. .

Since the display times of the three primary colors of red, green and blue are time-divided, the entire image data of the three primary colors must be stored in advance, and the odd-numbered scanning lines and the even-numbered scanning lines are shared by time-multiplexing. The same memory field, where, when the odd-numbered scan lines are imaged

When writing, the image data of an odd number of scan lines in the next picture is written.

Fig. 4 is a schematic view showing the frame memory used in the conventional field sequential liquid crystal display panel driving method. Please refer to FIG. 4, the frame memory 401 is used to store the data of the screen. Among them, the conventional field sequential liquid crystal display panel has two frame memories 401. Fig. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method. Fig. 5B is an enlarged waveform diagram of the first frame of Fig. 5A. Fig. 5C is an enlarged waveform diagram of the first +1 frame of Fig. 5A. Please refer to FIG. 5A, FIG. 5B and FIG. 5C. It can be seen from the above access timing chart that each horizontal synchronization (Hsync) time L ₁ ～ L _m is written to the next picture to be displayed. Enter the frame memory. In addition, the red L ₁ (R ₁ to R _n ) to L _m (R ₁ to R _n ) and the green L ₁ (G ₁ ) in the frame memory must be read out every 1/3 of the frame time. Display data of ~G _n ) to L _m (G ₁ to G _n ) or blue L ₁ (B ₁ to B _n ) to L _m (B ₁ to B _n ). Therefore, the conventional field sequential liquid crystal display panel has two frame memories 401 for respectively storing the display materials in the current frame I ^th and the adjacent next frame (I+1) ^th .

It is an object of the present invention to provide a driving method suitable for a field sequential flat panel display to reduce the memory requirement by half.

The invention provides a driving method suitable for a field sequential flat display. The field sequential flat display comprises a plurality of frames, each frame comprising a field corresponding to a red light source, a blue light source and a green light source, respectively. The method comprises the steps of: a. storing pixel data of an odd number of scan lines in an odd-numbered frame memory block, storing pixel data of an even number of scan lines in an even-numbered frame memory block; b. at the first block During the frame, when the pixel data of the odd scan lines is taken out from the odd frame memory block and displayed on the field sequential flat display, the pixels of the even scan lines of the I+1 frame are Data is written into the even-numbered frame memory block; and c. during the I+1 frame, when the pixel data of the even-numbered scan lines is taken out from the even-numbered frame memory block and displayed in the field sequence In the case of a flat panel display, the pixel data of the odd-numbered scan lines of the I+2 frame is written into the odd-numbered frame memory block, where I is a natural number.

The spirit of the present invention is to share the same memory field by using odd-numbered scan lines and even-numbered scan lines in a time division multiplexing manner. When an odd number of scanning lines are taken out from the frame memory and displayed on the display panel, the image data of the even-numbered scanning lines of the next picture is written. When an even number of scanning lines are taken out from the frame memory and displayed on the display panel, the image data of the odd-numbered scanning lines of the next picture is written. Therefore, the present invention can reduce the capacity requirement of the frame memory required to drive the field sequential flat display, and can be driven by only half the capacity of the conventional method.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Figure 6 is a block diagram of the system of the field sequential flat panel display of the present invention. Referring to FIG. 6, the flat panel display includes a display panel 601, a source driver 602, a gate driver 603, and a timing controller 604. The timing controller 604 includes a frame memory 605.

When a single pixel in the display panel 601 is to be colored, it is necessary to control the thin film transistor switch by using one pin of the gate driver 603, and input three primary color signals of R, G, and B by using three pins of the source driver 602. . The gate driver 603 is responsible for the switching operation of each column of the display. When the display performs a column and column-by-column scanning operation, the gate driver 603 cooperates to open an entire column of switches to cause the source driver 602 to perform a signal input operation. The source driver 602 is responsible for the input action of each pixel of the display. When the gate driver 603 opens an entire column of switches, the source driver 602 immediately outputs the column pixel data voltage to provide a signal required for displaying the screen.

The timing controller 604 is configured to adjust the action of the entire display. In conjunction with the display timing of each screen, on the one hand, the activation of the horizontal scanning line is set to control the gate driver 603 to output an appropriate voltage to a specific one column switch. On the other hand, the timing controller 604 receives an external input signal, converts the received video data into a digital signal required by the source driver 602, and cooperates with the opening of the horizontal scanning line to set a timing for driving the vertical scanning line, thereby controlling The source driver 602 outputs the voltage of the pixel data.

Fig. 7 is a view showing the arrangement of the frame memory 605 of the present invention. Referring to FIG. 7, the frame memory is divided into two parts, namely an odd frame memory block 701 and an even frame memory block 702, wherein the odd frame memory block 701 The red, green, and blue pixel data in the odd-numbered scan lines are stored, and the even-numbered frame memory block 702 is used to store red, green, and blue pixel data in the even-numbered scan lines. Fig. 8A is a clock waveform diagram of a driving method of the field sequential flat display according to the first embodiment of the present invention. Fig. 8B is an enlarged waveform diagram of the first frame of Fig. 8A. Fig. 8C is an enlarged waveform diagram of the first +1 frame of Fig. 8A. Please refer to FIG. 8A, FIG. 8B and FIG. 8C. The waveform waveform diagram includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a write timing 801, a read timing 802, and a red light-emitting diode point. a bright signal (R-LED) 803, a green light emitting diode lighting signal (G-LED) 804, a blue light emitting diode lighting signal (B-LED) 805, and a gate driving signal (Gate Driving Signal), For example, G1 to G5 are taken as an example. The vertical sync signal and the horizontal sync signal are signals used by the external signal source to synchronize as a display. The period during which the vertical sync signal is enabled is used to indicate the time that a frame can be displayed, and the period during which the horizontal sync signal is enabled indicates the time at which data of a horizontal scan line can be output. The enable period of the write sequence 801 indicates the period during which the timing controller 604 writes the data into the odd frame memory block 701 or the even frame memory block 702. The enable period of the read sequence 802 indicates that the source driver 602 outputs the voltage of the corresponding column pixel data in conjunction with the turned horizontal scan line. The red light-emitting diode lighting signal 803, the green light-emitting diode lighting signal 804, and the blue light-emitting diode lighting signal 805 enable period respectively indicate periods in which the red, green, and blue backlights are lit. The gate drive signals G1 G G5 are outputs of the gate driver 603 for respectively opening a corresponding column switch in the liquid crystal matrix.

At the first frame time, as in the (I) ^th frame period shown in the figure, each time the horizontal synchronizing signal is enabled, that is, when the horizontal synchronizing signal is a logic high voltage, the writing timing 801 is enabled, and the memory is The display data of the next frame is written, that is, the display data of (I+1) ^th frame is written. More specifically, during the (I) ^th frame, only the pixel data of the even scan lines in the next frame ((I+1) ^th frame) is written to the even frame memory block 702, wherein The odd frame memory block 701 is not updated. Next, please refer to the read timing 802, the red LED lighting signal 803, and the Gate Driving Signals G1 to G5. The red pixel data of the odd-numbered scan lines L ₁ , L ₃ , L ₅ ... L _m-1 in the odd-frame memory block 701 during the enable of the red light-emitting diode lighting signal 803 ₁ to Rn) are read out respectively. Moreover, when the odd column gate drive signal is enabled, the source driver 602 cooperates with an entire column of switches opened by the odd column gate drive signals to read the red pixel data L ₁ , L ₃ , L ₅ . The Lm _{-1 is} converted and output to the corresponding column pixel data voltage, that is, the horizontal scan line opening time corresponding to the driving gate, and the source driver 602 drives the vertical scanning line to provide the signal required for displaying the picture. Further even number, the red light-emitting diodes (during ^th frame (I illustrated in)) with a time frame enable signal 803 during the lighting, and when the gate G2, G4 ... column gate driving When the signal is enabled, the red pixel data of the even-numbered scan lines L ₂ , L ₄ ... L _m of the even-numbered frame memory block 702 are respectively read out, and the source driver 602 is matched with the even-numbered gates. The entire column of switches opened by the pole drive signal converts the read red pixel data L ₂ , L ₄ ... L _m and outputs the corresponding column pixel data voltage to provide the signal required for displaying the picture.

Similarly, during the enable of the green LED illuminating signal 804, the green pixels of the odd-numbered scan lines L ₁ , L ₃ , L ₅ ... L _m-1 in the odd-frame memory block 701 The data (G ₁ to G _n ) are read out, respectively. Moreover, when the odd column gate drive signal of the gate is enabled, the source driver 602 cooperates with an entire column of switches opened by the odd column gate drive signal to read the green pixel data L ₁ , L ₃ , L ₅ ... L _{m-1 are} converted and output as corresponding column pixel data voltages.

Further, in the period ^(th frame (I illustrated in)) during the same time frame enabling a green light-emitting diode lighting signal 804, when the even column gate drive signal is enabled, then the even-numbered The green pixel data (G ₁ - G _n ) of the even-numbered scan lines L ₂ , L ₄ ... L _m of the block memory block 702 are respectively read out, and the source driver 602 is driven by the even-numbered gates. The entire column of switches opened by the signal converts the read green pixel data L ₂ , L ₄ ... L _m and outputs the corresponding column pixel data voltage to provide the signal required for displaying the picture.

By the same token, the blue of the odd-numbered scan lines L ₁ , L ₃ , L ₅ ... L _m-1 in the odd-frame memory block 701 during the enable of the blue light-emitting diode lighting signal 805 The color pixel data (B ₁ to B _n ) are read out, respectively. Moreover, when the odd column gate drive signal is enabled, the source driver 602 cooperates with an entire column of switches opened by the odd column gate drive signals G1, G3, G5, ... to read out the blue pixel data. L ₁ , L ₃ , L ₅ ... L _{m-1 are} converted and output as corresponding column pixel data voltages.

Further, during the enable period ^(th frame (I illustrated in)) with a frame time of the blue light-emitting diode lighting signal 805 when the gate drive signal even column is enabled, then the even The blue pixel data (B ₁ -B _n ) of the even-numbered scan lines L ₂ , L ₄ ... L _m of the frame memory block 702 are respectively read out, and the source driver 602 is matched with the even-numbered gates An entire column of switches opened by the pole drive signals G2, G4, ... converts the read blue pixel data L ₂ , L ₄ ... L _m into a corresponding column pixel data voltage.

In summary, when driving an even number of scan lines of red, green or blue, the even frame memory block 702 is also being updated at the same time, so that a certain part of the extracted data may be It is the updated data. However, since the frame ((I) ^th frame) is only 1/60 second behind the next frame ((I+1) ^th frame), the difference between the pixels of the front and rear frames is not obvious, almost It will not adversely affect the quality of the monitor.

Next, at the time of the I+ ^1th frame time, that is, during the (I+1) ^th frame period, when the horizontal synchronization signal Hsync is enabled, that is, when the horizontal synchronization signal Hsync is a logic high voltage, the writing timing is When 801 is enabled, the memory will start to be written to the display data of the next frame, that is, the display data of (I+2) ^th frame. More specifically, during the (I+1) ^th frame, only the pixel data of the odd scan lines in the next frame ((I+2) ^th frame) is written to the odd frame memory block 701, wherein The even frame memory block 702 is not updated. Next, please refer to the read timing 802, the red LED lighting signal 803, and the Gate Driving Signals G1 to G5.

The red pixel data (R ₁ -R _n ) of the even-numbered scan lines L ₂ , L ₄ , . . . L _m in the even-frame memory block 702 during the enable of the red light-emitting diode lighting signal 803 ) are read out separately. Moreover, when the even-numbered gate drive signal is enabled, the source driver 602 cooperates with an entire column of switches opened by the even-numbered gate drive signals G2, G4, ... to read the red pixel data L ₂ , L ₄ , ... L _{m are} converted and output as corresponding column pixel data voltages, that is, with horizontal scanning line opening times corresponding to driving gates G2, G4, G6, ..., source driver 602 drives vertical scanning lines , in turn, to provide the signal required to display the screen.

In addition, during the enable of the red LED dimming signal 803 in the same frame time ((I+1) ^th frame period in the illustration), when the odd column gate driving signal is enabled, The red pixel data (R ₁ to R _n ) of the odd-numbered scanning lines L ₁ , L ₃ ... L _m-1 of the odd-frame memory block 701 are respectively read out, and the source driver 602 is matched with the odd-numbered An entire column of switches opened by the gate driving signals G1, G3, G5, ... converts the read red pixel data L ₁ , L ₃ ... L _m-1 into the corresponding column pixel data. Voltage to provide the signal required to display the picture.

Similarly, during the enabling of the green LED illuminating signal 804, the green pixel data of the even scan lines L ₂ , L ₄ , L ₆ ... L _m in the even frame memory block 702 are respectively Read out. Moreover, when the even-numbered gate drive signals of the gates G2, G4, . . . are enabled, the source driver 602 cooperates with an entire column of switches opened by the even-numbered gate drive signals G2, G4, ... The extracted green pixel data L ₂ , L ₄ , L ₆ ... L _{m are} converted and output as corresponding column pixel data voltages.

In addition, during the enable of the green LED illuminating signal 804 at the same frame time ((I+1) ^th frame in the illustration), when the gates G1, G3, G5, ... are odd When the gate driving signal is enabled, the green pixel data (G ₁ to G _n ) of the odd scanning lines L ₁ , L ₃ ... L _m-1 of the odd frame memory block 701 are respectively read. And the source driver 602 cooperates with an entire column of switches opened by the odd column gate drive signals G1, G3, G5, ... to read out the green pixel data L ₁ , L ₃ ... L _m-1 Convert and output the corresponding column pixel data voltage to provide the signal required for display.

By the same token, during the enable of the blue LED illuminating signal 805, the blue of the even number of scan lines L ₂ , L ₄ , L ₆ ... L _m in the even frame memory block 702 The pixel data (B ₁ to B _n ) are read out, respectively. Moreover, when the even-numbered gate drive signals of the gates G2, G4, . . . are enabled, the source driver 602 cooperates with an entire column of switches opened by the even-numbered gate drive signals G2, G4, ... The extracted blue pixel data L ₂ , L ₄ , L ₆ ... L _{m are} converted and output as corresponding column pixel data voltages.

In addition, during the enabling of the blue LED illuminating signal 805 at the same frame time ((I+1) ^th frame in the illustration), when the gates G1, G3, G5... When the odd column gate driving signal is enabled, the blue pixel data (B ₁ to B _n ) of the odd scanning lines L ₁ , L ₃ , L ₅ ... of the odd frame memory block 701 are respectively Read out, and the source driver 602 cooperates with an entire column of switches opened by the odd column gate drive signals G1, G3, G5, ... to read out the blue pixel data L ₁ , L ₃ , L ₅ . .. converts and outputs the corresponding column pixel data voltage.

Further, during the I+1th frame time, when the driving behavior of the odd-numbered scanning lines of red, green or blue is performed, the odd-numbered frame memory block 701 is also being updated, and therefore, some Some of the information that was taken out may be the updated information. However, since the frame ((I+1) ^th frame) is only 1/60 second behind the next frame ((I+2) ^th frame), the difference between the pixels of the two frames before and after is not obvious. There is almost no adverse effect on the picture quality of the display.

In summary, during the first frame time, only the even-numbered frame memory block 702 is updated, so that when the odd-numbered scan lines corresponding to the gate are turned on, the source driver 603 will use the odd-numbered frame memory block. The current frame stored in 701 that is not updated is used as the display material. In the first +1 frame time, only the odd frame memory block 701 is updated, so that when the even-numbered scan lines corresponding to the gate are turned on, the source driver 603 will use the even-numbered frame memory block 502. The current frame stored in the database that has not been updated is used as the display material. Since the time between the front and back frames is only 1/60 second, the difference between the pixels of the front and back frames is not obvious. Therefore, the influence on the image quality of the display is negligible. The invention can reduce the capacity requirement of the frame memory required for driving the field sequential flat display, that is, only half of the frame memory used in the conventional manner can be driven, wherein, in each frame time, Only half of the pixel data needs to be written to the frame memory to achieve power saving.

Second embodiment

9A is a waveform diagram of a driving method of a field sequential flat panel display according to a second embodiment of the present invention, wherein FIG. 9B is an enlarged waveform diagram of the first frame of FIG. 9A, and FIG. 9C is a An enlarged waveform diagram of the first +1 frame of Fig. 9A. Please refer to FIG. 9A, FIG. 9B and FIG. 9C. Similarly, the waveform waveform diagram includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a write timing 901, a read timing 902, and a red light emission. A polar body lighting signal (R-LED on) 903, a green light emitting diode lighting signal (G-LED on) 904, a blue light emitting diode lighting signal (B-LED on) 905, and a gate driving signal (Gate Driving Signal), for example, G1 to G5.

When the I-th time frame (shown in (I) during ^th frame), when the horizontal sync signal can be activated, i.e. the horizontal synchronizing signal is a logic high voltage, enabling the write timing 901, the memory start The display material of the next frame ((I+1) ^th frame) is written. The same as the first embodiment described above, during the (I) ^th frame, only the pixel data of the even scan lines in the next frame ((I+1) ^th frame) is written to the even frame memory area. Block 702. In addition, the odd frame memory block 701 is not updated.

Next, please refer to the read timing 902, the red LED lighting signal 903, and the gate driving signals G1 to G5. During the enable of the red LED lighting signal 903, the red pixel data (R ₁ - R _n ) of the odd-numbered scan lines in the odd-frame memory block 701 are read out, respectively. When the gates G1, G2 of the gate drive signals simultaneously is enabled, the source driver 602 with the gate drive signals G1, G2 of the opened two switches, the read out of the scanning line L red pixel data ₁ (R ₁ ～ R _n ) is converted and output as a corresponding column pixel data voltage; when the gate driving signals of the gates G3 and G4 are simultaneously enabled, the source driver 602 is coupled with the gate driving signals G3 and G4. The two columns of switches are opened, and the red pixel data (R ₁ - R _n ) of the read scan line L ₃ is converted and output as the corresponding column pixel data voltage, and the like and the like.

Next, when the green light-emitting diode and the blue light-emitting diode are enabled, the same as the red light-emitting diode, and details are not described herein again.

At the time of the I+ ^1th frame time ((I+1) ^th frame period in the illustration), when the horizontal synchronizing signal is enabled, when the horizontal synchronizing signal is a logic high voltage, the writing timing 901 is enabled, The memory will begin to be written to the pixel data of the next frame, which is the pixel data of the (I+2) ^th frame. More specifically, during the (I+1) ^th frame, only the pixel data of the odd-numbered scan lines of the (I+2) ^th frame are written to the odd-numbered frame memory block 701 without updating the even-numbered frame memory. Body block 702.

Next, please refer to the read timing 902, the red LED lighting signal 903, and the Gate Driving Signals G1 to G5. During the enable period of the red LED illuminating signal 903, the red pixel data of the even-numbered scanning lines L ₂ , L ₄ , L ₆ ... L _m in the even-frame memory block 702 (R ₁ ～ R _n ) is read out, respectively, and L1 of the odd-numbered frame scan line is read. When the gate driving signal of the gate G1 is enabled, the red pixel data (R ₁ to R _n ) of the first scanning line L ₁ of the odd frame memory block 701 are respectively read out, and the source is The driver 602 converts and outputs the red pixel data (R ₁ -R _n ) of the read scan line L ₁ into a corresponding column pixel data voltage according to an entire column switch opened by the gate drive signal G1; When the gate driving signals of the electrodes G2 and G3 are simultaneously enabled, the source driver 602 cooperates with the two columns of switches opened by the gate driving signals G2 and G3 to read the red pixel data of the read scanning line L ₂ ( R ₁ ～ R _n ) are converted and output as corresponding column pixel data voltages; when the gate driving signals of the gates G4 and G5 are simultaneously enabled, the source driver 602 is turned on by the gate driving signals G4 and G5. The two columns of switches convert and output the red pixel data (R ₁ -R _n ) of the read scan line L ₄ to the corresponding column pixel data voltage; ... and so on.

Next, during the activation of the green LED illuminating signal 904 and the blue LED illuminating signal 905, the operation is the same as the red LED illuminating signal, and details are not described herein.

The first frame I + 1 is the first embodiment of the first scan line L ₁ of the stored pixel data to the display data electrode G1 as a gate frame odd blocks of memory 701, the other gate G2, G3, G4, ... are pixel data using even scan lines L ₂ , L ₄ , L ₆ ... L _m in the even frame memory block 702.

Third embodiment

Fig. 10A is a clock waveform diagram of a driving method of a field sequential flat panel display according to a third embodiment of the present invention. Fig. 10B is an enlarged waveform diagram of the first frame of Fig. 10A. Fig. 10C is an enlarged waveform diagram of the first +1 frame of Fig. 10A. Please refer to FIG. 10A, FIG. 10B and FIG. 10C. Similarly, the waveform waveform diagram includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a write timing 1001, a read timing 1002, and a red light emission. Polar body lighting signal (R-LED on) 1003, green light emitting diode lighting signal (G-LED on) 1004, blue light emitting diode lighting signal (B-LED on) 1005 and partial gate Gate Driving Signal G1 to G5. In addition, in this embodiment, since the driving method of the first frame time is the same as that of the second embodiment, in the following embodiments, the driving method of the first frame time is not described, directly from the first +1. The driving method of the frame time begins to be described.

At the time of the I+1th frame time, when the horizontal synchronizing signal is enabled, that is, when the horizontal synchronizing signal is a logic high voltage, the writing timing 1001 is enabled, and the memory is started to be written to the next frame. Display data, that is, display data of (I+2) ^th frame, in which only pixel data in odd-numbered scan lines of (I+2) ^th frame are written to odd numbers during (I+1) ^th frame The frame memory block 701, and the even frame memory block 702 performs an update operation.

Next, please refer to the reading timing 1002, the red LED lighting signal 1003, and the gate driving signals G1 to G5. During the enable period of the red LED illuminating signal 1003, the red pixel data of the even scan lines L ₂ , L ₄ , L ₆ ... L _m in the even frame memory block 702 (R ₁ ～ R _n ) are read out respectively. When the gate driving signal of the gate G1 is enabled, the source driver 602 cooperates with the entire column of switches opened by the gate driving signal G1 to read the red pixel data of the second scanning line L ₂ read out ( R ₁ ～ R _n ) are converted and output as corresponding column pixel data voltages; when the gate driving signals of the gates G2 and G3 are simultaneously enabled, the source driver 602 is turned on by the gate driving signals G2 and G3. The two columns of switches convert and output the red pixel data (R ₁ -R _n ) of the fourth scanning line L ₄ read out as the corresponding column pixel data voltage; when the gates of the gates G4 and G5 When the driving signal is simultaneously enabled, the source driver 602 cooperates with the two columns of switches opened by the gate driving signals G4 and G5 to read the red pixel data of the sixth scanning line L ₆ (R ₁ to R). _n ) Convert and output to the corresponding column pixel data voltage; ... and so on.

Next, during the enable of the green LED illuminating signal 1004 or the blue LED illuminating signal 1005, the even number of scanning lines L ₂ , L ₄ , L in the even frame memory block 702 The green pixel data (G ₁ to G _n ) or the blue pixel data (B ₁ to B _n ) of ₆ ... L _m are respectively read out, and the subsequent operation is the same as the red light emitting diode lighting signal. No longer.

In summary, the spirit of the present invention is to share the same memory field by using odd-numbered scan lines and even-numbered scan lines in a time division multiplexing manner. When the image data of the odd-numbered scanning lines is taken out from the frame memory and displayed on the display panel, the image data of the even-numbered scanning lines in the next picture is written. When the image data of the even scan lines is taken out by the frame memory and displayed on the display panel, the image data of the odd scan lines in the next screen is written. Therefore, the present invention can reduce the capacity requirement of the frame memory required to drive the field sequential flat display, and can be driven by only half the capacity of the conventional method. In addition, since the demand for the built-in frame memory of the display driver is reduced, the dynamic power consumption of the display driver is relatively reduced.

10. . . LCD Monitor

10a. . . monitor

11, 11a. . . Display panel

12, 12a. . . Data line

13, 13a. . . Source drive circuit

20. . . Pixel

twenty one. . . Red subpixel

21a. . . Red lighting unit

twenty two. . . Green subpixel

22a. . . Green light unit

twenty three. . . Blue subpixel

23a. . . Blue light unit

401. . . Frame memory

601. . . Display panel

602. . . Source driver

603. . . Gate driver

604. . . Timing controller

605. . . Frame memory

701. . . Odd frame memory block

702. . . Even frame memory block

801, 901, 1001. . . Write timing

802, 902, 1002. . . Read timing

803, 903, 1003. . . Red LED illuminating signal (R-LED)

804, 904, 1004. . . Green LED illuminating signal (G-LED)

805, 905, 1005. . . Blue LED illuminating signal (B-LED)

G1～G5. . . Gate Driving Signal

FIG. 1 is a schematic diagram showing the connection of a source driving circuit of a conventional liquid crystal display to a display panel.

FIG. 2 is a schematic diagram showing the connection of a source driving circuit of another conventional display and a display panel.

Figure 3 shows a conventional timing diagram for driving the signal of the display of Figure 2.

Figure 4 is a schematic diagram of two sets of frame memory used in the conventional field sequential liquid crystal display panel driving method.

Fig. 5A is a waveform diagram of a conventional field sequential liquid crystal display panel driving method.

Fig. 5B is an enlarged waveform diagram of the first frame of Fig. 5A.

Fig. 5C is an enlarged waveform diagram of the first +1 frame of Fig. 5A.

Figure 6 is a block diagram of the system of the field sequential flat panel display of the present invention.

Fig. 7 is a view showing the arrangement of the frame memory 605 of the present invention.

Fig. 8A is a clock waveform diagram of a driving method of the flat panel display according to the first embodiment of the present invention.

Fig. 8B is an enlarged waveform diagram of the first frame of Fig. 8A.

Fig. 8C is an enlarged waveform diagram of the first +1 frame of Fig. 8A.

Fig. 9A is a clock waveform diagram of a driving method of the flat panel display according to the first embodiment of the present invention.

Fig. 9B is an enlarged waveform diagram of the first frame of Fig. 9A.

Fig. 9C is an enlarged waveform diagram of the first +1 frame of Fig. 9A.

Fig. 10A is a waveform diagram showing the driving method of the flat panel display of the first embodiment of the present invention.

Fig. 10B is an enlarged waveform diagram of the first frame of Fig. 10A.

Fig. 10C is an enlarged waveform diagram of the first +1 frame of Fig. 10A.

801. . . Write timing

802. . . Read timing

803. . . Red LED illuminating signal (R-LED)

804. . . Green LED illuminating signal (G-LED)

805. . . Blue LED illuminating signal (B-LED)

G1～G5. . . Gate Driving Signal

Claims (19)

A driving method for a field sequential flat panel display, the field sequential flat panel display comprising a plurality of frames respectively composed of a red light source, a blue light source and a map place corresponding to the green light source, wherein the driving method comprises: a. Storing pixel data of an odd number of scan lines in an odd-numbered frame memory block, and storing pixel data of an even number of scan lines in an even-numbered frame memory block; b. during the first frame, when When the pixel data of the odd scan lines is taken out from the odd frame memory block and displayed on the field sequential flat display, the pixel data of the even scan lines in the I+1 frame is written into the even number a frame memory block; and c. during the I+1 frame, when the pixel data of the even scan line is taken out from the even frame memory block and displayed on the field sequential display The pixel data of the odd scan lines in the first +2 frame is written into the odd frame memory block, where I is a natural number. The driving method described in claim 1, wherein in the step b, the pixel data in the odd frame memory block is not updated, and in the c step, the even frame memory block is The pixel data in it will not be updated. The driving method of claim 2, wherein during the first frame, the updated pixel data of the even scan lines are taken out from the even frame memory block and displayed in the field sequence. a flat panel display; and during the (1)th frame, the pixel data of the updated odd scan lines are taken out from the odd frame memory block and displayed on the field sequential flat display. According to the driving method described in claim 3, during the first frame, the pixel data of the odd scanning lines are taken out from the odd frame memory block and displayed on the field sequential plane. a display, wherein when one of the red light source, the blue light source, or the green light source is enabled, pixel data of a corresponding color in the odd-numbered scan lines is taken from the odd-numbered frame memory block, and When the gate is enabled, converting the corresponding pixel data into a corresponding column pixel data voltage according to the odd column gate driving signal; and updating the even-numbered scanning period during the first frame The pixel data of the line is taken out from the even frame memory block and displayed on the field sequential flat display, wherein when the red light source, the blue light source or the green light source is enabled, the even number is The frame memory block extracts the pixel data of the corresponding color in the even number of scan lines, and when the gate is enabled, converts the pixel data corresponding to the corresponding color according to the even column gate drive signal Corresponding Column pixel data voltage. The driving method according to the fourth aspect of the invention, wherein the pixel data of the even-numbered scanning lines are taken out from the even-numbered frame memory block during the first frame frame and displayed in the field sequence In a flat panel display, when one of the red light source, the blue light source or the green light source is enabled, pixel data of a corresponding color of the even-numbered scan lines in the even-numbered frame memory block is read Outputting, according to the even-numbered gate driving signal, converting and outputting the corresponding pixel data voltage; and updating the pixel data of the odd-numbered scanning lines during the first I+1 frame The odd frame memory block is taken out and displayed on the field sequential flat display, wherein the odd frame memory block is when the red light source, the blue light source or the green light source is enabled The pixel data of the corresponding color of the odd-numbered scan lines is read, and according to the odd-numbered gate drive signal, it is converted and output as the corresponding column pixel data voltage. The driving method of claim 2, wherein the field sequential display comprises a plurality of gate lines, and when the red light source, the blue light source or the green light source is enabled, the gate is In the order of the polar line driving, the pixel data in the odd frame memory block and the even frame memory block are taken out, thereby driving the field sequential flat display. For example, in the driving method described in claim 6, the step b further includes: sequentially enabling the gate driving signal when the red light source is enabled; and operating the gate in the 2n+1th gate line When the pole drive signal is enabled, the 2n+1th red data is taken out from the odd frame memory block to drive the 2n+1th scan line of the field sequential display; when the 2n+2th When the gate driving signal in the gate line is enabled, the 2n+2th red data is taken out from the even frame memory block to drive the 2n+2th scan lines of the field sequential display; When the green light source is enabled, the gate driving signal is sequentially enabled; when the gate driving signal in the 2n+1th gate line is enabled, the odd-numbered memory block is taken out a 2n+1th green data to drive the 2n+1th scanning line of the field sequential display; when the gate driving signal in the 2n+2th gate line is enabled, the even number The frame memory block takes out the 2n+2th green data to drive the 2n+2th scan line of the field sequential display; the blue light source is When the energy is enabled, the gate driving signal is sequentially enabled; when the gate driving signal in the 2n+1th gate line is enabled, the 2n+1 blue is taken out by the odd frame memory block Color data to drive the 2n+1th scan line of the field sequential display; and when the gate drive signal in the 2n+2 gate lines is enabled, the even frame memory The block takes out the 2n+2th blue data to drive the 2n+2th scan lines of the field sequential display. According to the driving method described in claim 6, the above c step includes: sequentially enabling the gate driving signal when the red light source is enabled; and when the gate is in the 2n+1th gate line When the driving signal is enabled, the 2n+1th red data is taken out by the odd frame memory block to drive the 2n+1th scan line of the field sequential display; when the 2n+2 gates When the gate driving signal in the line is enabled, the 2n+2th red data is taken out by the even frame memory block to drive the 2n+2th scan lines of the field sequential display; When the light source is enabled, the gate driving signal is sequentially enabled; when the gate driving signal in the 2n+1th gate line is enabled, the 2n+ is taken out from the odd frame memory block. a green data to drive the 2n+1th scanning line of the field sequential display; when the gate driving signal in the 2n+2th gate line is enabled, the even frame is memorized The 2n+2 green data is taken out by the body block to drive the 2n+2 scan lines of the field sequential display; when the blue light source is enabled The gate driving signal is sequentially enabled; when the gate driving signal in the 2n+1th gate line is enabled, the 2n+1th blue data is taken out by the odd frame memory block, Driving the 2n+1th scanning line of the field sequential display; and when the gate driving signal in the 2n+2th gate line is enabled, being taken out by the even frame memory block The 2n+2th blue data is used to drive the 2n+2th scan lines of the field sequential display. The driving method of claim 2, wherein the b step comprises: when the red light source, the blue light source or the green light source is enabled, the pixel data of the odd scan lines is from the odd figure The block memory block is read out, and converted into pairs according to the sequential two gate drive signals. The column of the pixel data voltage should be. The driving method of claim 9, wherein during the period of the (1)th frame, pixel data of the even-numbered scan lines are taken out from the even-numbered frame memory block and displayed in the field sequence. On the flat panel display, if one of the red light source, the blue light source or the green light source is enabled, the even number of scan lines in the even frame memory block and the odd frame memory block The pixel data of the corresponding color in the first scan line is read out, and the pixel data of the first scan line read in the odd frame memory block is converted according to the first gate driving signal And outputting to the corresponding column pixel data voltage, and converting, according to the other two gate driving signals, the pixel data of the corresponding even scanning line read in the even frame memory block into Corresponding column pixel data voltage. The driving method of claim 9, wherein during the first frame, pixel data of the odd scan lines are taken out from the odd frame memory block and displayed on the field sequential plane The display further includes: during the enabling of the red light source, sequentially enabling the gate driving signal, wherein the gate driving signal of the 2n+1th gate line and the 2n+2 gate line The gate driving signal is simultaneously enabled; when the gate driving signal of the 2n+1th gate line and the 2n+2th gate line is enabled, the odd-numbered frame memory block is taken out 2n+1 Red pixel data of the scan line to drive the 2n+1th scan line and the 2n+2 scan lines of the field sequential display; during the green light source enablement, the gate drive signal is sequentially enabled The gate drive signal of the 2n+1th gate line and the gate drive signal of the 2n+2th gate line are simultaneously enabled; when the 2n+1th gate line and the first When the gate driving signal of the 2n+2 gate lines is enabled, the green pixel data of the 2n+1th scan line is taken out by the odd frame memory block to drive the first of the field sequential display 2n+1 scanning lines and the 2n+2 scanning lines; during the enabling of the blue light source, the gate driving signals are sequentially enabled, wherein the gate driving signals of the 2n+1th gate lines are sequentially Simultaneously being enabled with the gate drive signal of the 2n+2th gate line; when the gate drive signal of the 2n+1th gate line and the 2n+2th gate line is enabled, Extracting the 2n+1th blue pixel data from the odd frame memory block to drive the 2n+1th scan line and the 2n+2th scan of the field sequential display Trace the line. The driving method of claim 9, wherein during the period of the (1)th frame, pixel data of the even-numbered scan lines are taken out from the even-numbered frame memory block and displayed in the field The sequential flat display further includes: during the enabling of the red light source, sequentially enabling the gate driving signal, wherein the gate driving signal of the 2n+2 gate lines and the 2n+3 gates The gate drive signal of the pole line is simultaneously enabled; When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the red pixels of the 2n+2th scan lines are taken out by the even-numbered frame memory block. Data to drive the 2n+2th scan line and the 2n+3th scan line of the field sequential display; during the green light source enablement, the gate drive signal is sequentially enabled, wherein the 2n The gate driving signals of the +2 gate lines are simultaneously enabled with the gate driving signals of the 2n+3 gate lines; when the 2n+2 gate lines and the 2n+3 gates are When the gate driving signal of the line is enabled, the green pixel data of the 2n+2th scan lines are taken out by the even frame memory block to drive the 2n+2 scan lines of the field sequential display. And the second n+3 scan lines; the gate drive signal of the gate line is sequentially enabled during the blue light source enablement, wherein the gate drive signal of the second n+2 gate line and the first The gate driving signals of the 2n+3 gate lines are simultaneously enabled; and when the gate driving signals of the 2n+2 gate lines and the 2n+3 gate lines are enabled, I The digital frame memory block extracts the blue pixel data of the 2n+2th scan lines to drive the 2n+2th scan lines and the 2n+3th scan lines of the field sequential flat display. The method for driving a flat panel display according to claim 12, wherein the gate driving signal is sequentially enabled during the enabling of the red light source, the green light source or the blue light source, wherein the second n+ When the gate driving signals of the two gate lines and the gate driving signals of the second n+3 gate lines are simultaneously enabled, the method further includes: First, the gate driving signal of the first scanning line is used to extract the corresponding red pixel data, green pixel data or blue pixel data of the first scanning line from the odd frame memory block, and further Driving the first scan line of the field sequential flat display. The driving method of claim 9, wherein the pixel data of the even scan lines is taken out from the even frame memory block and displayed on the field sequential plane during the first frame On the display, wherein, when one of the red light source, the blue light source or the green light source is enabled, the pixel data corresponding to the even-numbered scan lines in the even-numbered frame memory block is read out, and When the gate is enabled, the pixel data corresponding to the first scan line in the even frame memory block is converted and output as a corresponding column pixel data voltage according to the first gate driving signal. And converting, according to the other two gate drive signals, the pixel data corresponding to the even scan lines in the even frame memory block into the corresponding column pixel data voltage. The driving method according to claim 9, wherein during the frame of the first frame, the pixel data of the even-numbered scanning lines are taken out from the even-numbered frame memory block and displayed in the field sequence. The flat panel display further includes: during the enabling of the red light source, sequentially enabling the gate driving signal, wherein the gate driving signal of the 2n+2 gate lines and the 2n+3 gates The gate drive signal of the line is simultaneously enabled; When the gate driving signals of the 2n+2th gate line and the 2n+3th gate line are enabled, the red pixels of the 2n+4th scan lines are taken out by the even-numbered frame memory block. Data for driving the 2n+2th scanning line and the 2n+3th scanning line of the field sequential display; during the enabling of the green light source, sequentially driving the gate driving signal of the gate line, wherein The gate driving signal of the 2n+2th gate line and the gate driving signal of the 2n+3th gate line are simultaneously enabled; when the 2n+2th gate line and the 2n+3 When the gate driving signal of the gate line is enabled, the green pixel data of the 2n+4th scanning line is taken out by the even frame memory block to drive the 2n+2 of the field sequential display. a scan line and the second n+3 scan lines; wherein the gate drive signal is sequentially enabled during the blue light source enablement, wherein the gate drive signal of the second n+2 gate line The gate drive signal of the 2n+3th gate line is simultaneously enabled; and when the gate drive signal of the 2n+2th gate line and the 2n+3th gate line is enabled, The The even-numbered frame memory block extracts the blue pixel data of the 2n+4th scan lines to drive the 2n+2th scan lines and the 2n+3th scan lines of the field sequential flat display. The driving method of claim 15, wherein the gate driving signal is sequentially enabled during the enabling of the red light source, wherein the gate driving signal of the second n+2 gate line When the gate driving signal of the 2n+3th gate line is simultaneously enabled, the method further includes the steps of: first enabling the gate driving signal of the first scanning line, and in the first scanning When the gate driving signal of the trace is enabled, the red pixel data of the second scan line is taken out by the even frame memory block to drive the first scan line of the field sequential display. The driving method of claim 15, wherein the gate driving signal is sequentially enabled during the green light source enablement, wherein the gate driving signal of the second n+2 gate line When the gate driving signal of the 2n+3th gate line is simultaneously enabled, the method further includes the steps of: first enabling the gate driving signal of the first scanning line, and driving the gate driving signal of the first scanning line. When enabled, the green pixel data of the second scan line is taken out by the even frame memory block to drive the first scan line of the field sequential display. The driving method of claim 15, wherein the gate driving signal is sequentially enabled during the enabling of the blue light source, wherein the gate driving signal of the second n+2 gate line is The gate driving signal of the 2n+3 gate lines is simultaneously enabled, and further includes the steps of: enabling the gate driving signal of the first scanning line and causing the gate driving signal of the first scanning line When possible, the blue pixel data of the second scan line is taken out by the even frame memory block to drive the first scan line of the field sequential display. The driving method of claim 1, wherein the field sequential display comprises a horizontal synchronizing signal in the first frame And updating the pixel data in the even frame memory block when the horizontal synchronization signal is enabled; and updating the odd number during the first I+1 frame and when the horizontal synchronization signal is enabled The pixel data in the memory block of the frame.