CN102087471A - Method for improving photoetching critical dimension in groove process - Google Patents

Method for improving photoetching critical dimension in groove process Download PDF

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Publication number
CN102087471A
CN102087471A CN2009102019069A CN200910201906A CN102087471A CN 102087471 A CN102087471 A CN 102087471A CN 2009102019069 A CN2009102019069 A CN 2009102019069A CN 200910201906 A CN200910201906 A CN 200910201906A CN 102087471 A CN102087471 A CN 102087471A
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China
Prior art keywords
photoresist
groove
spin coating
negative photoresist
negative
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Pending
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CN2009102019069A
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Chinese (zh)
Inventor
阚欢
吴鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN2009102019069A priority Critical patent/CN102087471A/en
Publication of CN102087471A publication Critical patent/CN102087471A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a method for improving a photoetching critical dimension in a groove process. The method comprises the following steps of: 1, spin-coating negative photoresist on the surfaces of a groove and a silicon wafer and then roasting; 2, carrying out exposure and development by using a maskplate with a graph of a groove of a front layer; and 3, spin-coating a bottom antireflection coating (BARC) on a graph formed in the groove and roasting. By the method, the control capacity of the photoetching critical dimension (CD) in the groove process can be improved and a process window can be optimized.

Description

Be used for trench process and improve the method for photoetching critical size
Technical field
The present invention relates to the SIC (semiconductor integrated circuit) field, particularly relate to a kind of method that trench process is improved the photoetching critical size that is used for.
Background technology
At present, after etching groove forms, can give follow-up photoetching process because of the data number percent (data ratio) of step difference that gash depth brought and groove itself and bring great challenge, especially to the control of critical size.At the step difference that gash depth brought, follow-up photoetching process is mainly passed through BARC (bottom antireflective coating) or chemical material spin coating, or does flattening surface by blank etching.Concrete grammar is shown in Fig. 1-6, comprise successively: chemical packing material spin coating (referring to Fig. 1) for the first time, for the first time chemical packing material baking (referring to Fig. 2), blank etching is (referring to Fig. 3, can not have this step yet), chemical packing material spin coating (referring to Fig. 4) for the second time, for the second time chemical packing material baking (referring to Fig. 5), photoresist coating, exposure, development, the back baking waits normal photolithography operation (referring to Fig. 6).But a simple spin coating BARC may not realize planarization fully, and multiple spin coating can cause BARC blocked up.Blocked up BARC causes the corresponding increase of photoresist thickness so that satisfy the subsequent etching arts demand, and the increase of photoresist thickness will directly influence the control ability of the window and the critical size of overall optical carving technology.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that trench process is improved the photoetching critical size that is used for, and can improve the control ability of photoetching critical size CD in the trench process and optimize process window.
For solving the problems of the technologies described above, of the present inventionly be used for trench process to improve the method for photoetching critical size be to adopt following technical scheme to realize:
Step 1, the surperficial spin coating negative photoresist at groove and silicon chip toasts then;
Step 2 is utilized the mask board to explosure with anterior layer groove figure, develops;
Step 3 is carried out the spin coating of bottom anti-reflective material B ARC on the figure that forms in groove, baking.
Before the problem of improving the photoetching critical size in trench process mainly was how to be implemented in photoresist coating, planarization and BARC (bottom antireflective coating) thickness can not be blocked up as much as possible with silicon chip surface.The present invention utilizes a photoetching to realize the filling of original groove is covered, and can control bench height by the adjustment of photoresist thickness.Come further planarization by spin coating bottom anti-reflective material B ARC again and improve influence and the expansion process window of channel bottom incoherent scattering light critical size.Method of the present invention has been cut down etching technics of the prior art, improves the planarization effect, and need not to increase extra resource; Solve the control ability of photoetching critical size CD in the trench process and optimized process window.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1-the 6th, the existing method flow synoptic diagram that in trench process, improves the photoetching critical size;
Fig. 7-the 11st, method flow synoptic diagram of the present invention;
Figure 12 is a method control flow chart of the present invention.
Embodiment
In one embodiment of this invention, describedly be used for trench process to improve the method for photoetching critical size be before groove forms back photoresist coating, the silicon chip that has step is carried out planarization.Comprising a photoetching and a BARC spin coating.Specifically comprise the steps:
Step 1, in conjunction with shown in Figure 7, negative photoresist spin coating, baking.Surperficial spin coating negative photoresist at groove and silicon chip toasts then.Described negative photoresist is meant and the opposite polarity photoresist of conventional groove photoetching, if trench lithography is used negative glue, and the positive glue of spin coating then, and by that analogy.Described negative photoresist can be G-line, I-line, and KrF, ArF even be applicable to more short wavelength's photoresist, its thickness is not limit.
Step 2 in conjunction with shown in Figure 8, is utilized the mask board to explosure with anterior layer groove figure, develops.Described mask plate with anterior layer groove figure can be the mask plate of original groove figure, also can be the mask plate of layer pattern before comprising.The purpose of implementing this step is to utilize the principle of positive photoresist and negative photoresist exposure back figure complementation to realize trench fill, but the outer photoresist of groove is developed and removes.As shown in Figure 9, exposure back figure is formed in the groove.
Step 3 in conjunction with shown in Figure 10, is carried out the spin coating of bottom anti-reflective material B ARC on the figure that forms in groove, baking.The kind of described bottom anti-reflective material B ARC should satisfy the requirement of photoresist coupling in the subsequent process steps.By the further planarization silicon chip surface and improve of the influence of channel bottom incoherent scattering light of this step, increased process window simultaneously to critical size.
Step 4 in conjunction with shown in Figure 11, is carried out the spin coating of photoresist on bottom anti-reflective material B ARC, baking, and exposure is developed.Photoresist described in this step can be a positive photoresist, also can be negative photoresist.
More than by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (5)

1. one kind is used for the method that trench process is improved the photoetching critical size, it is characterized in that, comprises the steps:
Step 1, the surperficial spin coating negative photoresist at groove and silicon chip toasts then;
Step 2 is utilized the mask board to explosure with anterior layer groove figure, develops;
Step 3 is carried out the spin coating of bottom anti-reflective material B ARC on the figure that forms in groove, baking.
2. the method for claim 1 is characterized in that: negative photoresist described in the step 1 is meant and the opposite polarity photoresist of trench lithography, if trench lithography is used negative glue, and the positive glue of spin coating then, and by that analogy; Described negative photoresist can be G-line, I-line, and KrF, ArF even be applicable to more short wavelength's photoresist, the negative photoresist thickness of spin coating is not limit.
3. the method for claim 1, it is characterized in that: the mask plate that has the anterior layer groove figure described in the step 2 can be the mask plate of original groove figure, also can be the mask plate of layer pattern before comprising.
4. the method for claim 1 is characterized in that: the kind of the material B of bottom anti-reflective described in step 3 ARC should satisfy the requirement of photoresist coupling in the subsequent process steps.
5. the method for claim 1 is characterized in that: further comprise the spin coating of carrying out photoresist on bottom anti-reflective material B ARC, baking, exposure, step of developing; Photoresist described in this step can be a positive photoresist, also can be negative photoresist.
CN2009102019069A 2009-12-08 2009-12-08 Method for improving photoetching critical dimension in groove process Pending CN102087471A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
CN2009102019069A CN102087471A (en) 2009-12-08 2009-12-08 Method for improving photoetching critical dimension in groove process

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137442A (en) * 2011-11-30 2013-06-05 上海华虹Nec电子有限公司 Method of manufacturing slender type isolated line patterns in semiconductor technology
CN103268854A (en) * 2013-05-23 2013-08-28 康可电子(无锡)有限公司 Photoetching groove covering technology
CN103576445A (en) * 2012-07-24 2014-02-12 无锡华润上华半导体有限公司 Photoetching method for photoresist as silicon groove etching mask
CN104064450A (en) * 2013-03-19 2014-09-24 中芯国际集成电路制造(上海)有限公司 Manufacturing method for semiconductor device
CN104425216A (en) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 Method for photo-etching semiconductor substrate having trench
CN104465338A (en) * 2014-12-26 2015-03-25 力特半导体(无锡)有限公司 Deep groove multi-layer photoetching covering structure and photoetching covering method thereof
CN109246575A (en) * 2018-08-09 2019-01-18 广州联声电子科技有限公司 A kind of preparation method of the progressive acoustic impedance matching layer of high frequency
CN112147848A (en) * 2019-06-26 2020-12-29 山东华光光电子股份有限公司 Preparation method of small-size groove
CN113223937A (en) * 2021-04-21 2021-08-06 华虹半导体(无锡)有限公司 Method for detecting volatile formed by baking BARC hot plate

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137442B (en) * 2011-11-30 2015-06-03 上海华虹宏力半导体制造有限公司 Method of manufacturing slender type isolated line patterns in semiconductor technology
CN103137442A (en) * 2011-11-30 2013-06-05 上海华虹Nec电子有限公司 Method of manufacturing slender type isolated line patterns in semiconductor technology
CN103576445B (en) * 2012-07-24 2016-08-03 无锡华润上华半导体有限公司 Photoetching method as the photoresist of silicon groove etching mask
CN103576445A (en) * 2012-07-24 2014-02-12 无锡华润上华半导体有限公司 Photoetching method for photoresist as silicon groove etching mask
CN104064450A (en) * 2013-03-19 2014-09-24 中芯国际集成电路制造(上海)有限公司 Manufacturing method for semiconductor device
CN103268854B (en) * 2013-05-23 2015-12-09 康可电子(无锡)有限公司 A kind of lithographic trenches covering process
CN103268854A (en) * 2013-05-23 2013-08-28 康可电子(无锡)有限公司 Photoetching groove covering technology
CN104425216A (en) * 2013-08-20 2015-03-18 中芯国际集成电路制造(上海)有限公司 Method for photo-etching semiconductor substrate having trench
CN104465338A (en) * 2014-12-26 2015-03-25 力特半导体(无锡)有限公司 Deep groove multi-layer photoetching covering structure and photoetching covering method thereof
CN104465338B (en) * 2014-12-26 2017-02-22 力特半导体(无锡)有限公司 Deep groove multi-layer photoetching covering structure and photoetching covering method thereof
CN109246575A (en) * 2018-08-09 2019-01-18 广州联声电子科技有限公司 A kind of preparation method of the progressive acoustic impedance matching layer of high frequency
CN109246575B (en) * 2018-08-09 2020-10-16 广州联声电子科技有限公司 Preparation method of high-frequency progressive acoustic impedance matching layer
CN112147848A (en) * 2019-06-26 2020-12-29 山东华光光电子股份有限公司 Preparation method of small-size groove
CN113223937A (en) * 2021-04-21 2021-08-06 华虹半导体(无锡)有限公司 Method for detecting volatile formed by baking BARC hot plate
CN113223937B (en) * 2021-04-21 2022-08-16 华虹半导体(无锡)有限公司 Method for detecting volatile formed by baking BARC hot plate

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Application publication date: 20110608