CN102074933B - Controlling and activating circuit with low power consumption - Google Patents
Controlling and activating circuit with low power consumption Download PDFInfo
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- CN102074933B CN102074933B CN 201010616057 CN201010616057A CN102074933B CN 102074933 B CN102074933 B CN 102074933B CN 201010616057 CN201010616057 CN 201010616057 CN 201010616057 A CN201010616057 A CN 201010616057A CN 102074933 B CN102074933 B CN 102074933B
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Abstract
The invention discloses a controlling and activating circuit with low power consumption, wherein the circuit comprises a switching circuit, an external keying signal Vin2, an external triggering signal Vin1, a fixed resistor RLP2, a fixed resistor R1, a fixed resistor R2, a fixed resistor R3, a fixed capacitor C1, a fixed capacitor C2, a PMOS (Positive Channel Metal Oxide Semiconductor) tube Q1, a PMOS tube Q2, a NMOS (N-Mental-Oxide-Semiconductor) tube Q3, a RS flip-flop Q4 with a Schmitt inverter, a signal receiving end Vin1 and a power source Vcc. The circuit provided by the invention has the following advantages: (1) the circuit can be applied in an electrical control circuit of a lithium-battery protection system; (2) the utility and storage time of a battery pack is ensured; (3) low power consumption is realized; and (4) the circuit has simple structure and is easy to implement.
Description
(1) technical field:
The present invention relates to battery protection field, especially a kind of low power consumption control and active circuit.
(2) background technology:
Lithium ion battery has been widely used in portable type electronic product (as mobile phone, notebook computer, video camera) and electric vehicle power sources.Power supply is composed in series by a plurality of cells usually, to satisfy equipment required voltage and power requirement.In actual use, after battery pack and BMS composition power brick, after this power brick may need storage for a long time, just can be used by the user.When the user is idle, battery adds the power consumption (power consumption of BMS is in the mA level usually) of BMS from the power consumption electricity, can make power brick in the time of some months, with electric quantity loss totally, so BMS just need to have lower power consumption, the present invention can be the uA level with the power-dissipation-reduced that makes BMS, thereby makes power brick to store the longer time.
(3) summary of the invention:
The object of the present invention is to provide a kind of low power consumption control and active circuit, it can overcome the deficiencies in the prior art, is the circuit of a kind of low-power consumption, easy to control, easy activation, and simple, easy to operate.
Technical scheme of the present invention: a kind of low power consumption control and active circuit is characterized in that it is comprised of switching circuit, external key signal Vin2, outer triggering signal Vin1, fixed resistance RLP2, fixed resistance R1, fixed resistance R2, fixed resistance R3, fixed capacity C1, fixed capacity C2, PMOS pipe Q1, PMOS pipe Q2, NMOS pipe Q3, rest-set flip-flop Q4, signal receiving end Vin1 and power Vcc with Schmidt's reverser; Wherein said switching circuit input connects power Vcc, and an one output head grounding, another output are connected and fixed resistance R 1 and fixed resistance R2 and ground connection successively; Between said fixed resistance R1 and fixed resistance R2, tie point V1 is arranged; Said fixed capacity C1 is connected in parallel between tie point V1 and ground, be with fixed resistance R2 to be connected in parallel, and the fixed resistance R1 tie point of being connected with fixed resistance R2 also is connected with S end with the rest-set flip-flop Q4 of Schmidt's reverser; Said fixed capacity C2 one end connects power Vcc, and the other end is through fixed resistance R3 ground connection, and with the R end of the rest-set flip-flop Q4 of the common connecting band Schmidt of signal receiving end Vin1 reverser; The output of said rest-set flip-flop Q4 with Schmidt's reverser is connected with the grid of NMOS pipe Q3; The drain electrode of said NMOS pipe Q3 is connected with the grid of PMOS pipe Q2, is connected its source ground simultaneously with power Vcc through fixed resistance RLP2; Between said NMOS pipe Q3 and fixed resistance RLP2, tie point V2 is arranged; The grid of said PMOS pipe Q2 is connected with tie point V2, and its source electrode is connected with power Vcc, and it drains through load ground connection.
Above-mentioned said switching circuit is to be made of fixed resistance RLP1, PMOS pipe Q1 and switch Vin2; Wherein said fixed resistance RLP1 one end connects power Vcc, and the other end is through switch Vin2 ground connection; The grid of said PMOS pipe Q1 is connected and fixed the tie point of resistance R LP1 and switch Vin2, and its source electrode is connected with power Vcc, and drain electrode is connected with fixed resistance R1.
Operation principle of the present invention: the method for work of this circuit comprises the following steps:
1. after initially powering on, switch Vin2 opens, and PMOS pipe Q1 is fixed and draws shutoff on resistance R LP1;
2. be fixed resistance R 2 and fixed capacity C1 of the current potential of tie point V1 draws into L (low level), the current potential of signal receiving end Vin1 is due to the reason of fixed capacity C2, be pulled to H (high level) when powering on, this moment, the input R end with the rest-set flip-flop of Schmidt's reverser was H (high level), S end L (low level), output
Be initialized as H (high level);
3. when fixed resistance R3 drew signal receiving end Vin1 into L (low level), the R of rest-set flip-flop end was L (low level), and the S end is L (low level),
Remain H (high level), NMOS pipe Q3 opens, and tie point V2 current potential is pulled to L (low level), and PMOS pipe Q2 opens, and power supply is managed Q2 by PMOS and begun powering load;
4. idle when system, need to reduce power consumption, this moment, switch Vin2 was closed, and PMOS pipe Q1 opens, and the current potential of tie point V1 begins rising by fixed resistance R1 and fixed capacity C1;
5. after tie point V1 current potential rose to logic H (high level), this moment, the R end with the rest-set flip-flop of Schmidt's reverser was L (low level), and the S end is H (high level),
Become L (low level);
6. after, switch Vin2 opens, and is L (low level) with the R end of the rest-set flip-flop of Schmidt's reverser, and the S end is L (low level),
Remain L (low level), NMOS pipe Q3 closes, and V tie point 2 is pulled to H (high level), and PMOS pipe Q2 closes, the load outage.
7. when system need to activate, as long as will draw on tie point Vin1 (high level) a period of time into H, first make this moment the input R end with the rest-set flip-flop of Schmidt's reverser first be H (high level), S end L (low level), output
Become H (high level);
8. after, tie point Vin1 disconnects fixed resistance R3, and tie point Vin1 is drawn into L (low level), is L (low level) with the R end of the rest-set flip-flop of Schmidt's reverser, and the S end is L (low level),
Remain H (high level), this moment, NMOS pipe Q3 opened, and tie point V2 current potential is pulled to L (low level), and PMOS pipe Q2 opens, and power supply begins powering load by Q2.
Superiority of the present invention: 1, can be applied in the control electricity circuit of li-ion cell protection system; 2, guaranteed the use memory time of battery pack when idle; 3, realize that with two outer triggering signals the power supply of load circuit closes, thereby realize low-power consumption, in use again with its activation; 4, simple in structure, easily realize.
(4) description of drawings:
Accompanying drawing is the structured flowchart of the related a kind of low power consumption control of the present invention and active circuit.
(5) embodiment:
Embodiment: a kind of low power consumption control and active circuit (see photo) is characterized in that it is by switching circuit, external key signal Vin2, outer triggering signal Vin1, fixed resistance RLP2, fixed resistance R1, fixed resistance R2, fixed resistance R3, fixed capacity C1, fixed capacity C2, PMOS pipe Q1, PMOS pipe Q2, NMOS pipe Q3, rest-set flip-flop Q4, signal receiving end Vin1 and power Vcc with Schmidt's reverser; Wherein said switching circuit input connects power Vcc, and an one output head grounding, another output are connected and fixed resistance R 1 and fixed resistance R2 and ground connection successively; Between said fixed resistance R1 and fixed resistance R2, tie point V1 is arranged; Said fixed capacity C1 is connected in parallel between tie point V1 and ground, be with fixed resistance R2 to be connected in parallel, and the fixed resistance R1 tie point of being connected with fixed resistance R2 also is connected with S end with the rest-set flip-flop Q4 of Schmidt's reverser; Said fixed capacity C2 one end connects power Vcc, and the other end is through fixed resistance R3 ground connection, and with the R end of the rest-set flip-flop Q4 of the common connecting band Schmidt of signal receiving end Vin1 reverser; The output of said rest-set flip-flop Q4 with Schmidt's reverser is connected with the grid of NMOS pipe Q3; The drain electrode of said NMOS pipe Q3 is connected with the grid of PMOS pipe Q2, is connected its source ground simultaneously with power Vcc through fixed resistance RLP2; Between said NMOS pipe Q3 and fixed resistance RLP2, tie point V2 is arranged; The grid of said PMOS pipe Q2 is connected with tie point V2, and its source electrode is connected with power Vcc, and it drains through load ground connection.
Above-mentioned said switching circuit (see photo) is to be made of fixed resistance RLP1, PMOS pipe Q1 and switch Vin2; Wherein said fixed resistance RLP1 one end connects power Vcc, and the other end is through switch Vin2 ground connection; The grid of said PMOS pipe Q1 is connected and fixed the tie point of resistance R LP1 and switch Vin2, and its source electrode is connected with power Vcc, and drain electrode is connected with fixed resistance R1.
Claims (1)
1. a low power consumption control and active circuit is characterized in that it is to be made of switching circuit, external key signal Vin2, outer triggering signal Vin1, fixed resistance RLP2, fixed resistance R1, fixed resistance R2, fixed resistance R3, fixed capacity C1, fixed capacity C2, PMOS pipe Q1, PMOS pipe Q2, NMOS pipe Q3, rest-set flip-flop Q4, signal receiving end Vin1 and power Vcc with Schmidt's reverser; Wherein said switching circuit input connects power Vcc, and an one output head grounding, another output are connected and fixed resistance R 1 and fixed resistance R2 and ground connection successively; Between said fixed resistance R1 and fixed resistance R2, tie point V1 is arranged; Said fixed capacity C1 is connected in parallel between tie point V1 and ground, be with fixed resistance R2 to be connected in parallel, and the fixed resistance R1 tie point of being connected with fixed resistance R2 also is connected with S end with the rest-set flip-flop Q4 of Schmidt's reverser; Said fixed capacity C2 one end connects power Vcc, and the other end is through fixed resistance R3 ground connection, and with the R end of the rest-set flip-flop Q4 of the common connecting band Schmidt of signal receiving end Vin1 reverser; The output of said rest-set flip-flop Q4 with Schmidt's reverser is connected with the grid of NMOS pipe Q3; The drain electrode of said NMOS pipe Q3 is connected with the grid of PMOS pipe Q2, is connected its source ground simultaneously with power Vcc through fixed resistance RLP2; Between said NMOS pipe Q3 and fixed resistance RLP2, tie point V2 is arranged; The grid of said PMOS pipe Q2 is connected with tie point V2, and its source electrode is connected with power Vcc, and it drains through load ground connection; Said switching circuit is to be made of fixed resistance RLP1, PMOS pipe Q1 and switch Vin2; Wherein said fixed resistance RLP1 one end connects power Vcc, and the other end is through switch Vin2 ground connection; The grid of said PMOS pipe Q1 is connected and fixed the tie point of resistance R LP1 and switch Vin2, and its source electrode is connected with power Vcc, and drain electrode is connected with fixed resistance R1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010616057 CN102074933B (en) | 2010-12-30 | 2010-12-30 | Controlling and activating circuit with low power consumption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010616057 CN102074933B (en) | 2010-12-30 | 2010-12-30 | Controlling and activating circuit with low power consumption |
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| Publication Number | Publication Date |
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| CN102074933A CN102074933A (en) | 2011-05-25 |
| CN102074933B true CN102074933B (en) | 2013-11-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201010616057 Expired - Fee Related CN102074933B (en) | 2010-12-30 | 2010-12-30 | Controlling and activating circuit with low power consumption |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107817734B (en) * | 2017-12-05 | 2019-12-13 | 无锡市瀚为科技有限公司 | Ultra-low power consumption key control circuit |
| CN109950649B (en) * | 2019-04-19 | 2024-04-05 | 惠州市盛微电子有限公司 | Power activation circuit for battery management system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488736A (en) * | 2009-02-06 | 2009-07-22 | 中国航天时代电子公司第七七一研究所 | Dynamic body bias Schmitt trigger circuit |
| CN101771339A (en) * | 2008-12-29 | 2010-07-07 | 深圳艾科创新微电子有限公司 | Soft start circuit for switch power supply |
| CN201966641U (en) * | 2010-12-30 | 2011-09-07 | 天津南大强芯半导体芯片设计有限公司 | Low-power consumption control and activation circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055755A (en) * | 2007-08-29 | 2009-03-12 | Ricoh Co Ltd | Semiconductor device for protecting secondary battery |
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2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771339A (en) * | 2008-12-29 | 2010-07-07 | 深圳艾科创新微电子有限公司 | Soft start circuit for switch power supply |
| CN101488736A (en) * | 2009-02-06 | 2009-07-22 | 中国航天时代电子公司第七七一研究所 | Dynamic body bias Schmitt trigger circuit |
| CN201966641U (en) * | 2010-12-30 | 2011-09-07 | 天津南大强芯半导体芯片设计有限公司 | Low-power consumption control and activation circuit |
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| CN102074933A (en) | 2011-05-25 |
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