CN102064144A - Quad flat non-lead package and manufacturing method thereof - Google Patents
Quad flat non-lead package and manufacturing method thereof Download PDFInfo
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- CN102064144A CN102064144A CN 201010546154 CN201010546154A CN102064144A CN 102064144 A CN102064144 A CN 102064144A CN 201010546154 CN201010546154 CN 201010546154 CN 201010546154 A CN201010546154 A CN 201010546154A CN 102064144 A CN102064144 A CN 102064144A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a quad flat non-lead package and a manufacturing method thereof. The quad flat non-lead package comprises a lead frame, a chip, a package colloid and a protective layer. The lead frame comprises a plurality of leads with each including a lower surface which is divided into a contact region and a noncontact region. The chip is configured on the lead frame and is electrically connected with the lead frame. The package colloid comprises the chip and the leads and is filled between the leads. The package colloid is exposed to the contact region and the noncontact region of each lead. And the protective layer covers the noncontact region of each lead.
Description
Technical field
The present invention relates to a kind of quad flat package, and (Quad Flat Package QFP), and particularly relates to a kind of square flat non-pin encapsulation (Quad Flat Non-leaded package, QFN package) and preparation method thereof.
Background technology
Semiconductor packaging includes many encapsulation forms, the square flat non-pin encapsulation that wherein belongs to quad flat package series has short signaling path and comparatively faster signal transmission speed, therefore the square flat non-pin encapsulation is applicable to the Chip Packaging of high-frequency transmission (for example radio frequency band), and encapsulates one of main flow of kenel for hanging down pin position (low pin count).
In the manufacture method of square flat non-pin encapsulation, earlier with a plurality of chip configuration on nead frame (lead frame).Then, make these chips be electrically connected to nead frame by many bonding wires.Afterwards, come covered section nead frame, these bonding wires and these chips by packing colloid.At last, obtain a plurality of square flat non-pin encapsulation by cutting (punching) or sawing (sawing) singulation said structure.
Summary of the invention
The invention provides a kind of square flat non-pin encapsulation, it can reduce production cost and have preferred making yield.
The invention provides a kind of manufacture method of square flat non-pin encapsulation, it can reduce production cost and have preferred making yield.
The present invention proposes a kind of square flat non-pin encapsulation, and it comprises nead frame, chip, packing colloid and protective layer.Nead frame comprises chip carrier and a plurality of pin, and wherein pin disposes around chip carrier, and each pin has lower surface and lower surface is divided into contact zone and relief area.Chip configuration and is electrically connected to nead frame on nead frame.Packing colloid coating chip and pin, and be filled between the pin, wherein packing colloid exposes the contact zone and the relief area of each pin.Protective layer covers the relief area of each pin.
The present invention proposes a kind of manufacture method of square flat non-pin encapsulation, and wherein manufacture method comprises the steps.The square flat non-pin packaging body is provided, and wherein the bottom surface of square flat non-pin packaging body has a plurality of contact zones and a plurality of relief area.Form protective layer on relief area, to cover relief area.
Based on above-mentioned, etch partially the contact zone that defines pin compared to known see through, the design of square flat non-pin encapsulation of the present invention is to see through the contact zone that relief area that protective layer covers the lower surface of each pin defines pin.Therefore, the design of protective layer of the present invention can effectively reduce the production cost of square flat non-pin encapsulation and have preferred making yield.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section of a kind of square flat non-pin encapsulation of embodiments of the invention.
Fig. 2 A is the generalized section of a kind of square flat non-pin encapsulation of embodiments of the invention.
Fig. 2 B is the elevational schematic view of the square flat non-pin encapsulation of Fig. 2 A.
Fig. 3 A to Fig. 3 G illustrates the manufacture method of a kind of square flat non-pin encapsulation of embodiments of the invention with section.
Description of reference numerals
100: the square flat non-pin packaging body
100a, 100b: square flat non-pin encapsulation
110: nead frame
112: chip carrier
112a: basal surface
114: pin
114a: lower surface
114a ': contact zone
114a ": relief area
120: chip
130: packing colloid
132: the bottom surface
140a, 140b: protective layer
142: opening
150: the first bonding wires
160: the second bonding wires
170: adhesion coating
180: adhesive tape
Embodiment
Fig. 1 is the generalized section of a kind of square flat non-pin encapsulation of embodiments of the invention.Please refer to Fig. 1, in the present embodiment, square flat non-pin encapsulation 100a comprises nead frame 110, chip 120, packing colloid 130 and protective layer 140a.
Packing colloid 130 coating chips 120 and these pins 114, and be filled between these pins 114, wherein packing colloid 130 exposes the contact zone 114a ' and relief area 114a of each pin 114 ".Specifically, in the present embodiment, packing colloid 130 trims in fact with the lower surface 114a of these pins 114, i.e. the lower surface 114a of the bottom surface 132 of packing colloid 130 and these pins 114 copline in fact.Yet at other embodiment, the lower surface 114a of pin 114 also can protrude in the bottom surface 132 of packing colloid 130.
Protective layer 140a covers the relief area 114a of each pin 114 of nead frame 110 ".In other words, the contact zone 114a ' of each pin 114 not protected seam 140a covers, and promptly can be used as the contact that electrically connects with external circuit (not illustrating) and uses.Particularly, in the present embodiment, the contact zone 114a ' of each pin 114 and relief area 114a " area can decide by the area that protective layer 140a covers the lower surface 114a of each pin 114.In the present embodiment, the protective layer 140a area that covers the lower surface 114a of each pin 114 account for pin 114 lower surface 114a 80 40 percent to percent.In addition, but protective layer 140a cover part is filled in the packing colloid 130 between these pins 114 and the basal surface 112a of chip carrier 112, and wherein protective layer 140a is an insulating material, for example is: epoxide resin material (Epoxy).
In brief, the design of the square flat non-pin of present embodiment encapsulation 100a is to see through the relief area 114a that protective layer 140a covers the lower surface 114a of each pin 114 ", define the contact zone 114a ' of pin 114.Therefore, etch partially the contact zone that defines pin compared to known seeing through, the design of the protective layer 140a of present embodiment can effectively reduce the production cost of square flat non-pin encapsulation 100a and have preferred making yield.
What deserves to be mentioned is; the present invention does not limit protective layer 140a form; though the protective layer 140a that reaches mentioned herein is embodied as blocky; be the protective layer 140a basal surface 112a that covers chip carrier 112 fully, be filled in part packing colloid 130 between these pins 114 and these relief areas 114a of these pins 114 "; but known other can reach the structural design that has reducing production costs and have the preferred fabrication yield; still belong to the adoptable technical scheme of the present invention, do not break away from the scope of institute of the present invention desire protection.
For instance, Fig. 2 A is the generalized section of a kind of square flat non-pin encapsulation of embodiments of the invention.Fig. 2 B is the elevational schematic view of the square flat non-pin encapsulation of Fig. 2 A.Please also refer to Fig. 2 A and Fig. 2 B, in the present embodiment, the protective layer 140b of square flat non-pin encapsulation 100b also can have opening 142, and its split shed 142 exposes the part basal surface 112a of the chip carrier 112 of nead frame 110.Specifically, the protective layer 140b of present embodiment is embodied as annular patterns, and annular patterns is around the basal surface 112a configuration of chip carrier 112.Because the opening 142 of protective layer 140b exposes the basal surface 112a of chip carrier 112, so the heat energy that is produced during chip 120 runnings can directly dissipate to the external world by basal surface 112a.Thus, the square flat non-pin of present embodiment encapsulation 100b can have preferred radiating effect, and can keep the normal operation of chip 120.
Below will cooperate Fig. 3 A to Fig. 3 G to describe the manufacture method of these square flat non-pin encapsulation 100a, 100b in detail.
Fig. 3 A to Fig. 3 G illustrates the manufacture method of a kind of square flat non-pin encapsulation of embodiments of the invention with section.Please refer to Fig. 3 A, at first, provide nead frame 110, wherein nead frame 110 comprises chip carrier 112 and a plurality of pin 114.In the present embodiment, these pins 114 are around chip carrier 112 configurations.Each pin 114 has lower surface 114a, and lower surface 114a can divide into contact zone 114a ' and relief area 114a ".
Then, please refer to Fig. 3 B, fixed chip 120 is on the chip carrier 112 of nead frame 110, and its chips 120 is electrically connected to the chip carrier 112 and these pins 114 of nead frame 110.In order to increase the adherence between chip 120 and the chip carrier 112, also can be in fixed chip 120 to chip carrier on 112 before, form adhesion coating 170 on chip carrier 112, make chip 120 see through adhesion coating 170 and be fixed on the chip carrier 112.
Then, refer again to Fig. 3 B, carry out wire-bonded, to form these first bonding wires 150 and these second bonding wires 160, wherein these first bonding wires 150 are in order to connecting between chip 120 and the pairing pin 114, and these second bonding wires 160 are in order to be connected between chip 120 and the chip carrier 112.That is to say that chip 120 is electrically connected to these pins 114 and chip carriers 112 of nead frame 110 through these first bonding wires 150 and these second bonding wires 160.
Then, please refer to Fig. 3 C, attach adhesive tape 180 on the lower surface 114a of the basal surface 112a of chip carrier 112 and these pins 114, that is adhesive tape 180 covers the contact zone 114a ' and relief area 114a of each pin 114 ".
Then, please refer to Fig. 3 D, carry out sealing action (molding), and form packing colloid 130, and be filled between these pins 114 with coating chip 120, these pins 114, these first bonding wires 150 and these second bonding wires 160.
Then, please refer to Fig. 3 E, remove adhesive tape 180,, that is expose the contact zone 114a ' and relief area 114a of each pin 114 with the basal surface 112a of the chip carrier 112 that exposes nead frame 110 and the lower surface 114a of these pins 114 " and the basal surface 112a of chip carrier 112.Particularly, the setting of adhesive tape 180 can allow the packing colloid 130 and the lower surface 114a of these pins 114 trim in fact, i.e. the lower surface 114a of the bottom surface of packing colloid 130 and these pins 114 copline in fact.So far, to finish the making of square flat non-pin packaging body 100.
Then, in order to increase the reliability of subsequent step, can be earlier to the relief area 114a of each pin 114 " carry out the surface chemistry clean, to clean these relief areas 114a of these pins 114 ".In like manner, also can carry out surperficial oxyhydrogen flame clean, with the bottom surface 132 of cleaning packing colloid 130 to the part packing colloid 130 that is filled between these pins 114.
Then, please refer to Fig. 3 F, form protective layer 140a in these relief areas 114a of these pins 114 " on, to cover these relief areas 114a of these pins 114 ".In other words, protective layer 140a does not cover these contact zones 114a ' of these pins 114, promptly can be used as the contact that electrically connects with external circuit (not illustrating) and uses.Particularly, in the present embodiment, the contact zone 114a ' of each pin 114 and relief area 114a " area can decide by the area that protective layer 140a covers the lower surface 114a of each pin 114.In addition; but the protective layer 140a of present embodiment also cover part is filled in the packing colloid 130 between these pins 114 and the basal surface 112a of chip carrier 112; wherein protective layer 140a is an insulating material; for example: epoxide resin material (Epoxy), and the method for formation protective layer 140a for example is to use ink jet printing method, screen painting method, bat printing print process or the method for other transfer printings.
Afterwards, 140a is cured processing to protective layer, and with curing protective coat 140a, wherein cured comprises that infrared light solidifies (IR curing).At last, after being cured processing, packing colloid 130 is carried out the back segment baking-curing, and (Post Mold Curing PMC) handles, with cure package colloid 130.So far, finished the manufacture method of square flat non-pin encapsulation 100a.
Certainly, in other embodiments, please refer to Fig. 3 G, can form the protective layer 140b with opening 142, its split shed 142 exposes the basal surface 112a of the chip carrier 112 of nead frame 110, with as electrically connecting with the external world or the heat radiation purposes.
In brief, because present embodiment is to see through the relief area 114a that protective layer 140a, 140b cover the lower surface 114a of each pin 114 ", define the contact zone 114a ' of pin 114.Therefore, etch partially the contact zone that defines pin compared to known seeing through, the design of protective layer 140a, the 140b of present embodiment can effectively reduce the production cost of square flat non-pin encapsulation 100a, 100b and have preferred making yield.Moreover, because need not of present embodiment adopts known etching partially to form to have the nead frame 110 of these contact zones 114a ', therefore when carrying out wire-bonded, nead frame 110 can provide first bonding wire 150 and the bigger support force of second bonding wire 160, so can avoid going between bad or produce the situation that nead frame 110 breaks.
In sum, because the design of square flat non-pin of the present invention encapsulation is to see through the area that protective layer covers the lower surface of each pin, define the contact zone of pin and the area of relief area.Therefore, compared to the known area that etches partially the contact zone that directly forms pin that sees through, the design of protective layer of the present invention can effectively reduce the production cost of square flat non-pin encapsulation and have preferred making yield.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, those of ordinary skill in any affiliated technical field, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking claim.
Claims (15)
1. square flat non-pin encapsulation comprises:
Nead frame comprises a plurality of pins, and wherein each pin has lower surface and this lower surface is divided into contact zone and relief area;
Chip is disposed on this nead frame, and is electrically connected to this nead frame;
Packing colloid coats this chip and these a plurality of pins, and is filled between these a plurality of pins, and wherein this packing colloid exposes the contact zone and the relief area of each pin; And
Protective layer covers the relief area of each pin.
2. square flat non-pin encapsulation as claimed in claim 1, wherein this nead frame also comprises chip carrier, these a plurality of pins are around this chip carrier configuration, and this chip is positioned on this chip carrier.
3. square flat non-pin encapsulation as claimed in claim 2, wherein this protective layer has opening, and this opening exposes the basal surface of this chip carrier.
4. square flat non-pin encapsulation as claimed in claim 2 also comprises at least one first bonding wire and at least one second bonding wire, and wherein this first bonding wire electrically connects this chip and pairing pin, and this second bonding wire electrically connects this chip and this chip carrier.
5. square flat non-pin as claimed in claim 1 encapsulation, wherein this protective layer also is filled in this packing colloid between these a plurality of pins in the cover part.
6. square flat non-pin encapsulation as claimed in claim 1, wherein the material of this protective layer is an insulating material.
7. square flat non-pin encapsulation as claimed in claim 1, wherein the material of this protective layer is an epoxide resin material.
8. the manufacture method of square flat non-pin encapsulation comprises:
The square flat non-pin packaging body is provided, and wherein the bottom surface of this square flat non-pin packaging body has a plurality of contact zones and a plurality of relief area; And
Form protective layer on these a plurality of relief areas, to cover these a plurality of relief areas.
9. the manufacture method of square flat non-pin encapsulation as claimed in claim 8, the method that wherein forms this protective layer comprises ink jet printing method, screen painting method or bat printing print process.
10. the manufacture method of square flat non-pin encapsulation as claimed in claim 8, wherein the material of this protective layer is an insulating material.
11. the manufacture method of square flat non-pin as claimed in claim 8 encapsulation, the formation step of this square flat non-pin packaging body wherein comprises:
Nead frame is provided, and this nead frame comprises a plurality of pins, and wherein each pin has lower surface and this lower surface defines this contact zone and this relief area;
Fixed chip is on this nead frame, and wherein this chip is electrically connected to this nead frame; And
Form packing colloid, reach these a plurality of pins to coat this chip, and be filled between these a plurality of pins, wherein this packing colloid exposes the contact zone and the relief area of each pin.
12. the manufacture method of square flat non-pin encapsulation as claimed in claim 11, wherein this nead frame also comprises chip carrier, and these a plurality of pins are around this chip carrier configuration, and this chip is positioned on this chip carrier.
13. the manufacture method of square flat non-pin encapsulation as claimed in claim 12, wherein this protective layer has opening, and this opening exposes the basal surface of this chip carrier.
14. the manufacture method of square flat non-pin encapsulation as claimed in claim 11 also comprises:
Before forming this protective layer, to the contact zone of each pin carrying out the surface chemistry clean;
Before forming this protective layer, this packing colloid of part that is filled between these a plurality of pins is carried out surperficial oxyhydrogen flame clean; And
After forming this protective layer, this protective layer is cured processing.
15. the manufacture method of square flat non-pin encapsulation as claimed in claim 14 also comprises:
After carrying out this cured, this packing colloid is carried out the back segment baking-curing handle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010546154 CN102064144A (en) | 2010-11-10 | 2010-11-10 | Quad flat non-lead package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010546154 CN102064144A (en) | 2010-11-10 | 2010-11-10 | Quad flat non-lead package and manufacturing method thereof |
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| CN102064144A true CN102064144A (en) | 2011-05-18 |
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| CN 201010546154 Pending CN102064144A (en) | 2010-11-10 | 2010-11-10 | Quad flat non-lead package and manufacturing method thereof |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412842A (en) * | 2001-10-16 | 2003-04-23 | 新光电气工业株式会社 | Lead frame and method for manufacturing semiconductor device using said lead frame |
| CN102044510A (en) * | 2009-10-13 | 2011-05-04 | 日月光半导体制造股份有限公司 | Chip packaging body |
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2010
- 2010-11-10 CN CN 201010546154 patent/CN102064144A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1412842A (en) * | 2001-10-16 | 2003-04-23 | 新光电气工业株式会社 | Lead frame and method for manufacturing semiconductor device using said lead frame |
| CN102044510A (en) * | 2009-10-13 | 2011-05-04 | 日月光半导体制造股份有限公司 | Chip packaging body |
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Application publication date: 20110518 |