CN102054836B - Thyristor for electrostatic discharge - Google Patents
Thyristor for electrostatic discharge Download PDFInfo
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- CN102054836B CN102054836B CN 200910198070 CN200910198070A CN102054836B CN 102054836 B CN102054836 B CN 102054836B CN 200910198070 CN200910198070 CN 200910198070 CN 200910198070 A CN200910198070 A CN 200910198070A CN 102054836 B CN102054836 B CN 102054836B
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention relates to a thyristor for electrostatic discharge. The thyristor comprises a parasitic PNP tube, a parasitic NPN tube and a short-channel N-channel metal oxide semiconductor (NMOS) tube, wherein the emitter of the parasitic PNP tube is connected with an anode binding post, the base of the parasitic PNP tube is connected with the anode binding post through an N-trap parasitic resistor, and the collector of the parasitic PNP tube is connected with the base of the parasitic NPN tube and is connected with a cathode binding post through a P-trap parasitic resistor; the emitter of the parasitic NPN tube is connected with the cathode binding post, and the collector of the parasitic NPN tube is connected with the anode binding post through the N-trap parasitic resistor; and the drain of the short-channel NMOS tube is connected with the anode binding post through the N-trap parasitic resistor, the source of the short-channel NMOS tube is connected with the cathode binding post, and the grid length of the short-channel NMOS tube is less than 0.35 micron. The actual grid length of the short-channel NMOS tube is changed in a certain range, so that low and adjustable thyristor trigger voltage can be acquired.
Description
Technical field
The present invention relates to the protective circuit design field of semiconductor integrated circuit, especially relate to a kind of thyristor that is used for static discharge.
Background technology
In manufacturing, encapsulation and the use of IC chip, ESD (Electro StaticDischarge, static discharge) phenomenon all can appear.ESD shows as the high-voltage pulse of moment, and a large amount of electric charges of this abrupt release very likely destroy the function element of IC interior.Therefore, a thyristor that is used for static discharge is set usually between internal circuit and outside source or power supply.
At present, the structure of typical discharge cell thyristor is as shown in Figure 1 in the electrostatic discharge protective circuit commonly used, wherein left side P
+, N trap, right side P trap, N
+Formed a thyristor, the N in left side
+And P
+Be connected to anode terminal jointly, the N on right side
+And P
+Be connected to cathode terminal jointly, dash area is represented STI (Shallow Trench Isolation, shallow-trench isolation).The equivalent electric circuit of said protective device is shown in dotted portion, and parasitic PNP triode T1 ' is (by left side P
+, N trap and right side P trap form) base stage be connected to anode terminal 10 ' through N trap dead resistance Rnw ', so that the pressure drop between emitter and the base stage to be provided; Parasitic NPN triode T2 ' is (by N trap, right side P trap and N
+Composition) base stage is connected to cathode terminal 20 ' through P trap dead resistance Rpw ', so that the pressure drop between base stage and the emitter to be provided.
After an esd pulse occurring on the anode; When this ESD voltage height arrives to a certain degree; The reverse p-n junction that N trap and P trap constitute is breakdown, produces a leakage current and flows into the P trap, flow through said P trap dead resistance Rpw ' and in its two ends generation voltage drop of this electric current; Make base stage and the emitter of T2 ' be in positively biased, T2 ' begins conducting.In case after the T2 ' conducting, have electric current to flow into the collector electrode of T2 ', flow through N trap dead resistance Rnw ' and produce voltage drop equally at its two ends of this electric current makes emitter and the base stage positively biased of T1 ' so also conducting thereupon of T1 '.A positive feedback trigger mechanism like this makes whole thyristor structure be able to conducting, the too high voltages of the ESD electric current of releasing, elimination ESD, protection internal circuit.
But; The protective device trigger voltage (conducting voltage) that thyristor constitutes; Depend on the voltage that is added in anode when reverse p-n junction that N trap and P trap constitute takes place to puncture; The conducting voltage of general this protective device all is higher than the gate oxide breakdown voltage of internal circuit, and the effect of protection internal circuit can't be really played in also not conducting of protective device when gate oxide is breakdown.
Summary of the invention
The problem that the present invention solves provides a kind of thyristor that is used for static discharge, to reduce the trigger voltage of thyristor, thereby provide internal circuit is effectively protected.
For addressing the above problem, the present invention provides a kind of thyristor that is used for static discharge, comprising: parasitic PNP pipe, parasitic NPN pipe and short channel NMOS pipe;
The emitter of said parasitic PNP pipe connects anode terminal, and its base stage connects anode terminal through the dead resistance of N trap; Its collector electrode connects the base stage of parasitic NPN pipe, and connects cathode terminal through the dead resistance of P trap;
The emitter of said parasitic NPN pipe connects cathode terminal, and its collector electrode connects anode terminal through the dead resistance of N trap;
The drain electrode of said short channel NMOS pipe connects anode terminal through the dead resistance of N trap, and its source electrode connects cathode terminal, and the grid length of said short channel NMOS pipe is less than 0.35 micron.
Preferably, the grid length of said short channel NMOS pipe is 0.13～0.2 micron.
The present invention also provides another kind to be used for the thyristor of static discharge, comprising: parasitic PNP pipe, parasitic NPN pipe and short channel PMOS pipe;
The emitter of said parasitic PNP pipe connects anode terminal, and its base stage connects anode terminal through the dead resistance of N trap; Its collector electrode connects the base stage of parasitic NPN pipe, and connects cathode terminal through the dead resistance of P trap;
The emitter of said parasitic NPN pipe connects cathode terminal, and its collector electrode connects anode terminal through the dead resistance of N trap;
The drain electrode of said short channel PMOS pipe connects anode terminal through the dead resistance of P trap, and its source electrode connects cathode terminal, and the grid length of said short channel PMOS pipe is less than 0.35 micron.
Preferably, the grid length of said short channel PMOS pipe is 0.13～0.2 micron.
Compared with prior art, the present invention has the following advantages:
The thyristor that is used for static discharge of the present invention; Between N trap and P trap, insert the short channel NMOS pipe or the PMOS pipe of an enhancement mode, make when ESD voltage is low, can be with the thyristor conducting; Release fast the ESD electric current, eliminate the too high voltages of ESD, effectively protect internal circuit;
In addition, long through the actual grid that change short channel NMOS pipe or PMOS pipe within the specific limits, can access lower and thyristor trigger voltage that can regulate, can satisfy the demand of different electrostatic discharge protective circuits.
Description of drawings
Fig. 1 is the structural representation of typical discharge cell thyristor in a kind of electrostatic discharge protective circuit in the prior art;
Fig. 2 is a kind of structural representation that is used for the thyristor of static discharge of the present invention;
Fig. 3 is the equivalent circuit diagram that is used for the thyristor of static discharge in the corresponding diagram 2;
Fig. 4 is when the pipe of the NMOS in Fig. 2 thyristor grid length reduces, the equivalent circuit diagram of thyristor;
Fig. 5 is the structural representation that another kind of the present invention is used for the thyristor of static discharge;
Fig. 6 is when the gate pmos length in Fig. 5 thyristor reduces, the equivalent circuit diagram of thyristor.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the embodiment of the invention done further detailed explanation.
The common thyristor that is used for static discharge utilizes a PNP triode and the mutual positive feedback of NPN triode to form; Just utilized the extremely low a kind of thyristor of conducting resistance of " latch-up " principle structure of CMOS (Complementary Metal OxideSemiconductor, complementary metal oxide semiconductors (CMOS)).Thereby common SCR utilizes N trap/P trap reverse breakdown to produce substrate current and triggers PNP or NPN triode.Owing to there is positive feedback path, no matter be that the PNP triode triggers earlier, or the NPN triode triggers earlier, the another one triode all can trigger thereupon.But in the CMOS manufacture craft, N trap/P trap reverse breakdown voltage is very high, generally all will be higher than 15V, can't protect the thin grid oxic horizon of 0.35um and following technology with such ESD device.
LVT-SCR (Low Voltage Triggered Silicon Controlled Rectmer; Low trigger voltage thyristor) utilized the PN junction low direction breakdown voltage characteristics of metal-oxide-semiconductor drain electrode near grid; In common SCR, added a NMOS pipe; The structure of this thyristor is as shown in Figure 2, and the NMOS pipe of adding is equivalent between the collector electrode of NPN triode T2 and base stage, add the back biased diode of a low reverse breakdown voltage, and is as shown in Figure 3.When applying voltage respectively at anode terminal 10 and cathode terminal 20; Esd event takes place between anode and negative electrode; This equivalence back biased diode can be routed under lower voltage; When the substrate current that produces passes through trap resistance, the substrate electric potential of lifting NPN triode T2 and PNP triode T1, thus trigger PNP triode T1 and NPN triode T2 and then startup thyristor.
The present invention inserts a NMOS pipe in thyristor, as shown in Figure 2, but this NMOS pipe is short channel NMOS pipe, and its channel length is much smaller than general NMOS pipe.The emitter of said parasitic PNP pipe T1 connects anode terminal, and its base stage connects anode terminal 10 through the dead resistance Rnw of N trap, and its collector electrode connects the base stage of parasitic NPN pipe T2, and connects cathode terminal 20 through the dead resistance Rpw of P trap; The emitter of said parasitic NPN pipe T2 connects cathode terminal 20, and its collector electrode connects anode terminal 10 through the dead resistance Rnw of N trap; The drain electrode of said short channel NMOS pipe connects anode terminal 10 through the dead resistance Rnw of N trap, and its source electrode connects cathode terminal 20 through the dead resistance Rpw of P trap.This short channel NMOS pipe can be seen two back-to-back PN junctions (N+/P-of the N+/P-of drain terminal/substrate terminal and source end/substrate terminal) as, the long remote definition of grid NPN manage the width in P district among the T2, equivalent electric circuit is as shown in Figure 4.When there is big pressure reduction in the voltage that applies at two N utmost points, if the P district is exhausted fully, the break-through of electric field can take place, just in general sense device break-through (punch-through).When two N interpolar pressure reduction are higher than the break-through critical voltage, the electric current of the NPN that flows through pipe T2 several magnitudes that increase sharply, this electric current N trap of flowing through, the dead resistance Rnw through the N trap is used to reduce the N trap potential, thereby triggers PNP triode T1, and starts thyristor.
Because these two back-to-back PN junctions of short channel NMOS pipe equivalence all are typical monolateral knot (just the doping content in N district are very high, and the doping content in P district is lower), and the width of depletion region of monolateral knot depends primarily on the lower one side of doping content; P trap for given doping content; The long actual width that defines depletion region of the grid of NMOS, therefore, also remote definition critical punch through voltage; The width of depletion region is more little, and the critical punch through voltage of depletion region is low more.Thus, it is long to change grid within the specific limits, promptly can obtain adjustable required critical punch through voltage.
For example in the prior art, in general 0.13um 1.2V/3.3V technology, the punch through voltage of I/O device is 3.3V, and the minimum gate of 3.3V NMOS length is 0.35um.According to the embodiment of the invention, the 3.3V short channel NMOS pipe that can to make up the long scope of grid be 0.13um～0.2um, punch through voltage is about 7V～9V between the short channel NMOS pipe source-drain electrode in the long scope of these grid.9V trigger voltage with traditional LVT-SCR structure can only obtain fixing is compared, and thyristor of the present invention can obtain more the end and adjustable trigger voltage.
In another embodiment of the present invention, in thyristor, insert a PMOS pipe, as shown in Figure 5, and this PMOS pipe is short channel PMOS pipe, its channel length is managed much smaller than general PMOS.This thyristor comprises: parasitic PNP pipe T3, parasitic NPN pipe T4 and short channel PMOS pipe; The emitter of said parasitic PNP pipe T3 connects anode terminal 30, and its base stage connects anode terminal 30 through the dead resistance Rnw of N trap; Its collector electrode connects the base stage of parasitic NPN pipe T4, and connects cathode terminal 40 through the dead resistance Rpw of P trap; The emitter of said parasitic NPN pipe T4 connects cathode terminal 40, and its collector electrode connects anode terminal 30 through the dead resistance Rnw of N trap; The drain electrode of said short channel PMOS pipe connects anode terminal 30 through the dead resistance Rpw of P trap, and its source electrode connects cathode terminal 40.PMOS in present embodiment pipe can be seen two back-to-back PN junctions (P+/N-of the P+/N-of drain terminal/substrate terminal and source end/substrate terminal) as, the long remote definition of grid PNP manage the width in N district among the T3, equivalent electric circuit is as shown in Figure 6.When there is big pressure reduction in the voltage that applies at two P utmost points, if the N district is exhausted fully, the break-through of electric field can take place, just in general sense device break-through (punch-through).When two P interpolar pressure reduction are higher than the break-through critical voltage, the electric current of the PNP that flows through pipe T3 several magnitudes that increase sharply, this electric current P trap of flowing through, the dead resistance Rnw through the N trap is used to reduce the N trap potential, thereby triggers NPN triode T4, starts thyristor.
Because these two back-to-back PN junctions of short channel PMOS pipe equivalence all are typical monolateral knot (just the doping content in P district are very high, and the doping content in N district is lower), and the width of depletion region of monolateral knot depends primarily on the lower one side of doping content; P trap for given doping content; The long actual width that defines depletion region of the grid of PMOS, therefore, also remote definition critical punch through voltage; The width of depletion region is more little, and the critical punch through voltage of depletion region is low more.Thus, it is long to change grid within the specific limits, promptly can obtain adjustable required critical punch through voltage.
Equally, according to the embodiment of the invention, can make up grid and grow the 3.3V short channel PMOS pipe that scope is 0.13um～0.2um, this thyristor can obtain more the end and adjustable trigger voltage.
It will be appreciated by persons skilled in the art that trigger voltage lower in the safe range can further increase the susceptibility and the response speed of thyristor, therefore, can reach better ESD protection effect.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (4)
1. a thyristor that is used for static discharge is characterized in that, comprising: parasitic PNP pipe, parasitic NPN pipe and short channel NMOS pipe;
The emitter of said parasitic PNP pipe connects anode terminal, and its base stage connects anode terminal through the dead resistance of N trap; Its collector electrode connects the base stage of parasitic NPN pipe, and connects cathode terminal through the dead resistance of P trap;
The emitter of said parasitic NPN pipe connects cathode terminal, and its collector electrode connects anode terminal through the dead resistance of N trap;
The drain electrode of said short channel NMOS pipe connects anode terminal through the dead resistance of N trap, and its source electrode connects cathode terminal, and the grid length of said short channel NMOS pipe is less than 0.35 micron.
2. the thyristor that is used for static discharge according to claim 1 is characterized in that, the grid length of said short channel NMOS pipe is 0.13～0.2 micron.
3. a thyristor that is used for static discharge is characterized in that, comprising: parasitic PNP pipe, parasitic NPN pipe and short channel PMOS pipe;
The emitter of said parasitic PNP pipe connects anode terminal, and its base stage connects anode terminal through the dead resistance of N trap; Its collector electrode connects the base stage of parasitic NPN pipe, and connects cathode terminal through the dead resistance of P trap;
The emitter of said parasitic NPN pipe connects cathode terminal, and its collector electrode connects anode terminal through the dead resistance of N trap;
The drain electrode of said short channel PMOS pipe connects anode terminal through the dead resistance of P trap, and its source electrode connects cathode terminal, and the grid length of said short channel PMOS pipe is less than 0.35 micron.
4. the thyristor that is used for static discharge according to claim 3 is characterized in that, the grid length of said short channel PMOS pipe is 0.13～0.2 micron.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910198070 CN102054836B (en) | 2009-10-28 | 2009-10-28 | Thyristor for electrostatic discharge |
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|---|---|---|---|
| CN 200910198070 CN102054836B (en) | 2009-10-28 | 2009-10-28 | Thyristor for electrostatic discharge |
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|---|---|
| CN102054836A CN102054836A (en) | 2011-05-11 |
| CN102054836B true CN102054836B (en) | 2012-11-21 |
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| CN108878417B (en) * | 2018-07-05 | 2020-10-30 | 江南大学 | Transient voltage suppressor with high-maintenance MOS auxiliary trigger SCR structure |
| CN111739887B (en) * | 2020-07-09 | 2023-08-01 | 中国科学院上海微系统与信息技术研究所 | Electrostatic protection unit based on thyristor and parallel structure thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211968A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | Manufacture method for thyristor for electro-static discharge |
| CN101257018A (en) * | 2008-03-28 | 2008-09-03 | 上海宏力半导体制造有限公司 | Electrostatic protection circuit with discrete polycrystal gate structure |
| CN101442047A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Electrostatic protection structure for low trigger voltage thyristor |
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- 2009-10-28 CN CN 200910198070 patent/CN102054836B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442047A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Electrostatic protection structure for low trigger voltage thyristor |
| CN101211968A (en) * | 2007-12-21 | 2008-07-02 | 上海宏力半导体制造有限公司 | Manufacture method for thyristor for electro-static discharge |
| CN101257018A (en) * | 2008-03-28 | 2008-09-03 | 上海宏力半导体制造有限公司 | Electrostatic protection circuit with discrete polycrystal gate structure |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140217 |
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Effective date of registration: 20140217 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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