CN102054810B - Chip with metal column structures - Google Patents
Chip with metal column structures Download PDFInfo
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- CN102054810B CN102054810B CN200910211805.XA CN200910211805A CN102054810B CN 102054810 B CN102054810 B CN 102054810B CN 200910211805 A CN200910211805 A CN 200910211805A CN 102054810 B CN102054810 B CN 102054810B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
- H01L2224/11902—Multiple masking steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11912—Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
Abstract
The invention relates to a chip with metal column structures. The chip comprises a chip body, at least one chip solder pad, a first protection layer, an under-call metal layer and at least one metal column structure; the chip body is provided with an active face; the chip solder pad is located on the active face; the first protection layer is arranged on the active face and has at least one first opening for exposing part of the chip solder pad; the under-ball metal layer is arranged on the chip solder pad; the at least one column structure is arranged on the metal layer and comprises a metal column and a solder, wherein the metal column is arranged on the under-ball metal layer, the solder is arranged on the metal column, the maximum diameter formed by the solder is less than or equal to the diameter of the metal column. Therefore, when the interval between every two adjacent metal column structures is a micro-interval, the problem of solder bridging can be avoided so that the yield is improved.
Description
Technical field
The invention relates to a kind of chip, in detail, is about a kind of chip with metal column structures.
Background technology
With reference to figure 1, show the known generalized section with the chip of metal column structures.This known chip 1 with metal column structures comprises a chip body 11, at least one chip pad 12,1 first protective layer 13, ball lower metal layer 14 and at least one metal column structures 15.This chip body 11 has an active surface 111.This chip pad 12 is positioned at this active surface 111.This first protective layer 13 is positioned on this active surface 111, and has at least one first opening 131 to appear this chip pad 12 of part.This ball lower metal layer 14 is positioned in this chip pad 12.This metal column structures 15 is positioned on this ball lower metal layer 14, and comprises metal column 16 and a solder 17.This metal column 16 is positioned on this ball lower metal layer 14, and has a metal column outer peripheral face 161.This solder 17 is positioned on this metal column 16, and the maximum gauge that this solder 17 is formed is greater than the diameter of this metal column 16, and protrudes from outside outer peripheral face 161 scope that upwards imagination extends of this metal column 16.
This is known, and to have the shortcoming of the chip 1 of metal column structures as follows.When the spacing of two adjacent metal rod structures 15 in this chip 1 is micro-spacing (Fine Pitch), and the maximum gauge that these solders 17 are formed is when being greater than the diameter of these metal columns 16, two adjacent solder 17 are easy to the problem producing bridge joint (Bridge), and then cause the situation of short circuit.
Therefore, be necessary to provide a kind of chip with metal column structures, to solve the problem.
Summary of the invention
The invention provides a kind of chip with metal column structures, it comprises a chip body, at least one chip pad, one first protective layer, a ball lower metal layer and at least one metal column structures.This chip body has an active surface.This chip pad is positioned at this active surface.This first protective layer is positioned on this active surface, and has at least one first opening to appear this chip pad of part.This ball lower metal layer is positioned in this chip pad.This metal column structures is positioned on this ball lower metal layer, and comprises a metal column and a solder.This metal column is positioned on this ball lower metal layer.This solder is positioned on this metal column, and the maximum gauge that this solder is formed is less than or equal to the diameter of this metal column.
The present invention more provides a kind of chip with metal column structures, and it comprises a chip body, at least one chip pad, one first protective layer, a ball lower metal layer and at least one metal column structures.This chip body has an active surface.This chip pad is positioned at this active surface.This first protective layer is positioned on this active surface, and has at least one first opening to appear this chip pad of part.This ball lower metal layer is positioned in this chip pad.This metal column structures is positioned on this ball lower metal layer, and comprises a metal column and a solder.This metal column is positioned on this ball lower metal layer, and has a metal column outer peripheral face.This solder is positioned at the outer peripheral face upwards imaginary scope extended of this metal column.
By this, when the spacing of two adjacent metal rod structures is micro-spacing in this chip, the problem of solder bridge joint in known technology can be avoided, to promote yield.
Accompanying drawing explanation
Fig. 1 shows the known generalized section with the chip of metal column structures;
Fig. 2 to Fig. 8 shows the schematic diagram that the present invention has the manufacture method of the first embodiment of the chip of metal column structures;
Fig. 9 shows the generalized section that the present invention has the second embodiment of the chip of metal column structures;
Figure 10 shows the generalized section that the present invention has the 3rd embodiment of the chip of metal column structures; And
Figure 11 to Figure 17 shows the schematic diagram that the present invention has the manufacture method of the 4th embodiment of the chip of metal column structures.
Embodiment
Referring to figs. 2 to Fig. 8, display the present invention has the schematic diagram of the manufacture method of the chip of metal column structures.With reference to figure 2, provide a chip body 21, at least one chip pad 22,1 first protective layer 23 and a sputtered layer 24.This chip body 21 has an active surface 211.This chip pad 22 is positioned at this active surface 211.This first protective layer 23 is positioned on this active surface 211, and has at least one first opening 231 to appear this chip pad 22 of part.This sputtered layer 24 covers this first protective layer 23 and this chip pad 22 of part.With reference to figure 3, form a photoresistance 25 in this sputtered layer 24, this photoresistance 25 has at least one photoresistance opening 251, and this photoresistance opening 251 appears this sputtered layer 24 of part, and the position of this photoresistance opening 251 is to should chip pad 22.
With reference to figure 4, form a metal column 26 in this photoresistance opening 251, this metal column 26 is positioned in this sputtered layer 24, and the material of this metal column 26 is copper (Cu), and the height of this metal column 26 is not limit.With reference to figure 5, form a solder 27 in this photoresistance opening 251, this solder 27 is positioned on this metal column 26, and this metal column 26 and this solder 27 form a metal column structures 28.
With reference to figure 6, utilize resist of delustering to remove this photoresistance 25 (Fig. 5), and utilize etching mode to remove this sputtered layer 24 (Fig. 5) of part to form a ball lower metal layer (Under Ball Metal, UBM) 29.This metal column 26 is positioned on this ball lower metal layer 29, and this ball lower metal layer 29 is positioned in this chip pad 22.In the present embodiment, this ball lower metal layer 29 is sandwich construction, the material of this ball lower metal layer 29 comprises aluminium (Al), titanium (Ti), nickel (Ni), vanadium (V) or copper (Cu), and the outer peripheral face 261 of this metal column 26 trims with the outer peripheral face 291 of this ball lower metal layer 29.With reference to figure 7, heat this solder 27 and make it form molten state, and then form a hemisphere because of cohesive force, the maximum gauge that this solder 27 is formed is less than or equal to the diameter of this metal column 26.Preferably, the height of this solder 27 is less than or equal to the radius of this metal column 26.
Referring again to Fig. 7, display the present invention has the generalized section of the first embodiment of the chip of metal column structures.This chip 2 with metal column structures comprises a chip body 21, at least one chip pad 22,1 first protective layer 23, ball lower metal layer 29 and at least one metal column structures 28.This chip body 21 has an active surface 211.This chip pad 22 is positioned at this active surface 211.This first protective layer 23 is positioned on this active surface 211, and has at least one first opening 231 to appear this chip pad 22 of part.This ball lower metal layer 29 is positioned in this chip pad 22, and this ball lower metal layer 29 has a ball lower metal layer outer peripheral face 291.In the present embodiment, this ball lower metal layer 29 is sandwich construction, and the material of this ball lower metal layer 29 comprises aluminium (Al), titanium (Ti), nickel (Ni), vanadium (V) or copper (Cu).
This metal column structures 28 is positioned on this ball lower metal layer 29, and comprises metal column 26 and a solder 27.This metal column 26 is positioned on this ball lower metal layer 29, and has a metal column outer peripheral face 261.In the present embodiment, the material of this metal column 26 is copper (Cu), and the height of this metal column 26 is not limit, and the outer peripheral face 261 of this metal column 26 trims with the outer peripheral face 291 of this ball lower metal layer 29.This solder 27 is positioned on this metal column 26, and the maximum gauge that this solder 27 is formed is less than or equal to the diameter of this metal column 26, makes this solder 27 be positioned at the outer peripheral face 261 upwards imaginary scope extended of this metal column 26.Preferably, this solder 27 is a hemisphere, and the height of this solder 27 is less than or equal to the radius of this metal column 26.In the present invention, the distance definition of the central shaft of two adjacent metal column structures 28 is a space D (Fig. 8), and this space D is less than or equal to 150 μm, i.e. so-called micro-spacing (Fine Pitch).
With reference to figure 9, display the present invention has the generalized section of the second embodiment of the chip of metal column structures.The chip 3 with metal column structures of the present embodiment is roughly the same with the chip 2 (Fig. 2) with metal column structures of the first embodiment, and identical numbering given by wherein identical assembly.The present embodiment more comprises one second protective layer 30 from different being in of the first embodiment in this chip 3, is positioned on this first protective layer 23, and has at least one second opening 301 to appear this chip pad 22 of part.In the present embodiment, the material of this second protective layer 30 is polyimide (Polyimide, PI), and the second opening 301 of this second protective layer 30 is less than the first opening 231 of this first protective layer 23.This ball lower metal layer 29 is positioned in this chip pad 22, and this second protective layer 30 of cover part.
With reference to Figure 10, display the present invention has the generalized section of the 3rd embodiment of the chip of metal column structures.The chip 4 with metal column structures of the present embodiment is roughly the same with the chip 3 (Fig. 9) with metal column structures of the second embodiment, and identical numbering given by wherein identical assembly.The present embodiment and the second embodiment different the second opening 301 be in this second protective layer 30 is greater than the first opening 231 of this first protective layer 23, to appear this chip pad 22 of part and this first protective layer 23 of part.This ball lower metal layer 29 is positioned in this chip pad 22, and this first protective layer 23 of cover part and this second protective layer 30 of part.
By this, when this chip 2,3, when the spacing of two adjacent metal rod structures 28 is micro-spacing in 4, the problem of solder bridge joint in known technology can be avoided, to promote yield.
With reference to figures 11 to Figure 17, display the present invention has the schematic diagram of the manufacture method of the 4th embodiment of the chip of metal column structures.The manufacture method with the chip of metal column structures of the present embodiment is roughly the same with the manufacture method (Fig. 2 to Fig. 8) with the chip of metal column structures of the first embodiment, and identical numbering given by wherein identical assembly.The present embodiment is different from the first embodiment to be in after formation one metal column 26, more form a barrier layer (Barrier Layer) 31 on this metal column 26, the material of this barrier layer 31 is nickel (Ni), then, form a solder 27 again on this barrier layer 31, and this metal column 26, this barrier layer 31 and this solder 27 form a metal column structures 28.
Referring again to Figure 17, display the present invention has the generalized section of the 4th embodiment of the chip of metal column structures.The chip 5 with metal column structures of the present embodiment is roughly the same with the chip 2 (Fig. 7) with metal column structures of the first embodiment, and identical numbering given by wherein identical assembly, as shown in Figures 2 to 7.The present embodiment is different from the first embodiment to be in and more to comprise a barrier layer (Barrier Layer) 31 in this metal column structures 28 and be positioned on this metal column 26, this solder 27 is positioned on this barrier layer 31, and the better material of this barrier layer 31 is nickel (Ni).By this, this barrier layer 31 can stop that this solder 27 penetrates into this metal column 26 upper limb and forms Jie's metal level and cause reliability to reduce.
Only above-described embodiment is only and principle of the present invention and effect thereof is described, and is not used to limit the present invention.Therefore, the personage practised in this technology modifies to above-described embodiment and changes still de-spirit of the present invention.Interest field of the present invention should listed by claims.
Claims (14)
1. there is a chip for metal column structures, comprising:
One chip body, has an active surface;
At least one chip pad, is positioned at this active surface;
One first protective layer, is positioned on this active surface, and has at least one first opening to appear this chip pad of part;
One second protective layer, be positioned on this first protective layer, and there is at least one second opening to appear this chip pad of part, wherein the second opening of this second protective layer is less than the first opening of this first protective layer, and wherein the material of this second protective layer is polyimide;
One ball lower metal layer, is positioned in this chip pad; And
At least one metal column structures, is positioned on this ball lower metal layer, comprises:
One metal column, is positioned on this ball lower metal layer;
One barrier layer, is positioned on this metal column; And
One solder, be positioned on the barrier layer on this metal column, the maximum gauge that this solder is formed is less than the diameter of this metal column.
2. chip as claimed in claim 1, wherein the distance definition of the central shaft of two adjacent metal column structures is a spacing, and this spacing is less than or equal to 150 μm.
3. chip as claimed in claim 1, wherein the material of this barrier layer is nickel.
4. chip as claimed in claim 1, wherein the outer peripheral face of this metal column and the outer peripheral face of this ball lower metal layer trim.
5. chip as claimed in claim 1, wherein the material of this metal column is copper.
6. chip as claimed in claim 1, wherein the height of this solder is less than or equal to the radius of this metal column.
7. chip as claimed in claim 1, wherein this solder is a hemisphere.
8. there is a chip for metal column structures, comprising:
One chip body, has an active surface;
At least one chip pad, is positioned at this active surface;
One first protective layer, is positioned on this active surface, and has at least one first opening to appear this chip pad of part;
One second protective layer, be positioned on this first protective layer, and there is at least one second opening to appear this chip pad of part, wherein the second opening of this second protective layer is less than the first opening of this first protective layer, and wherein the material of this second protective layer is polyimide;
One ball lower metal layer, is positioned in this chip pad; And
At least one metal column structures, is positioned on this ball lower metal layer, comprises:
One metal column, is positioned on this ball lower metal layer, and has a metal column outer peripheral face;
One barrier layer, is positioned on this metal column; And
One solder, be positioned at the outer peripheral face upwards imaginary scope extended of the barrier layer on this metal column, the maximum gauge that this solder is formed is less than the diameter of this metal column.
9. chip as claimed in claim 8, wherein the distance definition of the central shaft of two adjacent metal column structures is a spacing, and this spacing is less than or equal to 150 μm.
10. chip as claimed in claim 8, wherein the material of this barrier layer is nickel.
11. chips as claimed in claim 8, wherein the outer peripheral face of this metal column and the outer peripheral face of this ball lower metal layer trim.
12. chips as claimed in claim 8, wherein the material of this metal column is copper.
13. chips as claimed in claim 8, wherein the height of this solder is less than or equal to the radius of this metal column.
14. chips as claimed in claim 8, wherein this solder is a hemisphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910211805.XA CN102054810B (en) | 2009-10-30 | 2009-10-30 | Chip with metal column structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910211805.XA CN102054810B (en) | 2009-10-30 | 2009-10-30 | Chip with metal column structures |
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| Publication Number | Publication Date |
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| CN102054810A CN102054810A (en) | 2011-05-11 |
| CN102054810B true CN102054810B (en) | 2015-04-29 |
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| CN200910211805.XA Active CN102054810B (en) | 2009-10-30 | 2009-10-30 | Chip with metal column structures |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| CN101060087A (en) * | 2006-04-17 | 2007-10-24 | 尔必达存储器株式会社 | Electrode, manufacturing method of the same, and semiconductor device having the same |
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2009
- 2009-10-30 CN CN200910211805.XA patent/CN102054810B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1437256A (en) * | 2002-02-07 | 2003-08-20 | 日本电气株式会社 | Semiconductor element and producing method thereof, and semiconductor device and producing method thereof |
| CN101060087A (en) * | 2006-04-17 | 2007-10-24 | 尔必达存储器株式会社 | Electrode, manufacturing method of the same, and semiconductor device having the same |
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| Publication number | Publication date |
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| CN102054810A (en) | 2011-05-11 |
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