CN102054083A - Method for checking antenna effect of integrated circuit and device thereof - Google Patents
Method for checking antenna effect of integrated circuit and device thereof Download PDFInfo
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- CN102054083A CN102054083A CN2009102113944A CN200910211394A CN102054083A CN 102054083 A CN102054083 A CN 102054083A CN 2009102113944 A CN2009102113944 A CN 2009102113944A CN 200910211394 A CN200910211394 A CN 200910211394A CN 102054083 A CN102054083 A CN 102054083A
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Abstract
The present invention relates to a method for checking antenna effect of an integrated circuit and a device thereof, wherein the method for checking antenna effect of the integrated circuit comprises the steps of: calculating antenna effect values caused by nodes of each metal layer of an integrated circuit to various components of the integrated circuit; counting a maximum value of accumulated antenna effect values caused by the nodes to the components; if there is provided a node, wherein the maximum value of the accumulated antenna effect value of the node is less than a critical value, defining the node to conform to an antenna effect checking rule.
Description
Technical field
The invention relates to inspection method and its device of integrated circuit, especially about the inspection method and the device thereof of the antenna effect of integrated circuit.
Background technology
The continuous progress of ic manufacturing technology makes the minimum dimension of integrated circuit (IC) chip also descend always.So in, dwindle in the physical Design of chip size trend at this, more need to consider the influence of manufacturing capacity (manufacturability) to qualification rate that integrated circuit (IC) chip causes (yield) and reliability (reliability).For reaching the purpose of dwindling chip size, the many dependences of the processing procedure of integrated circuit (IC) chip now are based on the processing procedures of plasma.Yet, described processing procedure based on plasma can make each layer metal level stored charge of integrated circuit (IC) chip, and then cause each damage of elements in the integrated circuit (IC) chip, the gate oxide that causes for plasma that effect like this claims damages (plasma-induced gateoxide damage), or abbreviates antenna effect (antenna effect) as.
Fig. 1 shows the part sectioned view of an integrated circuit (IC) chip.As shown in Figure 1, described integrated circuit (IC) chip 100 comprises a first grid 102 and a second grid 104.Described first grid 102 is to be connected to described second grid 104 via a ground floor metal level line M1 and a second layer metal layer line M2.In the processing procedure process of described integrated circuit (IC) chip 100, each layer metal level of described integrated circuit (IC) chip 100 is successively to make up from lower to upper.In the building process of described metal level, each metal level line that does not connect as yet is to act on as electric capacity.In other words, the described metal level line stored charge in its processing procedure process that does not connect as yet.Described stored charge can discharge in processing procedure process after a while.Yet the release of described stored charge will cause damage to the element of described integrated circuit (IC) chip 100.If described processing procedure process is an etch process, then described damage is the girth that is proportional to the described metal level line that does not connect as yet.If described processing procedure process is the area that is proportional to the described metal level line that does not connect as yet for polishing processing procedure, then described damage.
Fig. 2 shows that described integrated circuit (IC) chip 100 is in the part sectioned view that has made up described ground floor metal level line M1.As shown in Figure 2, the described ground floor metal level line M1 meeting stored charge that is connected in described second grid 104, and described charges accumulated is if surpass a critical value, can cause damage to described second grid 104, what wherein said damage claimed is that gate oxide collapses, and also is the damage that collapse caused of described second grid 104.According to the processing procedure of described integrated circuit (IC) chip 100, described damage is to be proportional to the gate area of the area of described ground floor metal level line M1 divided by described second grid 104.
In view of the above, the processing procedure of integrated circuit (IC) chip also develops variety of way and overcome antenna effect.Wherein a kind of mode is for to interrupt long metal level line, and connects the described metal level line that interrupts via a bonding line (jumper) and upper metal layers.Therefore, the method can reduce the girth or the area of the described metal level line that does not connect as yet.Another kind method is for increasing diode to protect the described element that may be damaged.The element that another method may be damaged with attenuating for the order of the described metal level of transposing.
Except the positive processing procedure process in integrated circuit (IC) chip overcomes antenna effect with the whole bag of tricks.Qualify Phase in integrated circuit (IC) chip also comprises the step whether described integrated circuit (IC) chip of inspection meets antenna effect inspection rule.Antenna effect inspection rule herein is that representative is not checked rule if meet described antenna effect, and then the antenna effect of described integrated circuit may cause damage to its element.Fig. 3 shows the process flow diagram of inspection method of the antenna effect of existing integrated circuits.In step 302, the node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit, and enters step 304.In step 304, check at each node of each metal level whether its each element to described integrated circuit meets an antenna effect and check rule.
According to the inspection method of the antenna effect of existing integrated circuits shown in Figure 3, when checking each node, all must whether meet an antenna effect inspection rule and judge at each element of described integrated circuit.Therefore, identity element will be by duplicate test when different nodes are checked many times.Check action so repeatedly will expend the required time of described inspection method in a large number.
Fig. 4 shows the synoptic diagram of the part sectioned view of an integrated circuit (IC) chip.As shown in Figure 4, described integrated circuit (IC) chip 400 comprises a ground floor metal level, a second layer metal layer, a three-layer metal layer and several elements P
1To P
25Described ground floor metal level comprises plurality of nodes N
1,1To N
1,25, wherein each node all is connected to an element.Described second layer metal layer comprises plurality of nodes N
2,1To N
2,5, N wherein
2,1Be connected to node N
1,1To N
1,5, N
2,2Be connected to node N
1,6To N
1,10, and the rest may be inferred.Described three-layer metal layer comprises a node N3, and 1, it is to be connected to described node N
2,1To N
2,5
If the antenna effect inspection method of using existing integrated circuit shown in Figure 3 in the integrated circuit (IC) chip of Fig. 4, is then being checked N
1,1When whether meeting antenna effect inspection rule, described element P
1Can be verified once.Checking N
2,1Whether meet described antenna effect and check rule, described element P
1Can be verified once again.Checking N
3,1Whether meet described antenna effect and check rule, described element P
1To be verified once once more.Check action so repeatedly is not inconsistent user demand in fact for the circuit design industry of pursuing timeliness and cost.
In view of the above, industry is needed to be a kind of method and device thereof, and it is spent time during the antenna effect of compression check integrated circuit significantly, so that the entire circuit design cycle can be more efficient.
Summary of the invention
The present invention is by the maximal value of each node of statistics to the accumulation antenna effect value that described element caused, and reaches and reduces the purpose that each element is verified number of times.Required time when whether each node of reduced inspection meets an antenna effect and check rule significantly in view of the above, and reach the purpose of the antenna effect of quickening to check integrated circuit.
The invention provides a kind of method of correction circuit layout, comprise the following step: the node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit; Add up the maximal value of each node to the accumulation antenna effect value that described element caused; And if there is a node, the maximal value of its accumulation antenna effect value then defines described node and meets antenna effect inspection rule less than a critical value.
The invention provides a kind of device that is used for the correction circuit layout, described device comprises a computing unit, a statistics unit and an inspection unit.Described computing unit is to calculate the node of each metal level of an integrated circuit to the antenna effect value that each element caused of described integrated circuit.Described statistic unit is the maximal value of adding up the accumulation antenna effect value of each node according to the result of calculation of described computing unit.Described inspection unit is to check according to the statistics of described statistic unit whether each node meets an antenna effect and check rule.
Sketch out technical characterictic of the present invention above is in order to do making detailed description hereinafter be obtained preferable understanding.Other technical characterictic that constitutes claims of the present invention will be described in hereinafter.Having those of ordinary skill in the technical field of the invention should understand, and hereinafter the notion of Jie Shiing can be used as the basis with specific embodiment and revised or design other structure quite easily or processing procedure and realize the purpose identical with the present invention.Have those of ordinary skill in the technical field of the invention and also should understand, the structure of this class equivalence also can't break away from the spirit and scope of the present invention that the accompanying Claim book is proposed.
Description of drawings
Fig. 1 shows the part sectioned view of an integrated circuit (IC) chip;
Fig. 2 shows the part sectioned view of an integrated circuit (IC) chip in the processing procedure process;
Fig. 3 shows the process flow diagram of inspection method of the antenna effect of existing integrated circuits;
Fig. 4 shows the synoptic diagram of the part sectioned view of an integrated circuit (IC) chip;
Fig. 5 shows the process flow diagram according to the inspection method of the antenna effect of the integrated circuit of one embodiment of the invention;
The process flow diagram of the inspection method of the antenna effect of Fig. 6 demonstration integrated circuit according to another embodiment of the present invention; And
Fig. 7 shows the synoptic diagram according to the testing fixture of the antenna effect of the integrated circuit of one embodiment of the invention.
Embodiment
The present invention is at the inspection method and the device thereof of this direction of inquiring into antenna effect that is a kind of integrated circuit.In order to understand the present invention up hill and dale, detailed step and composition will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that the technician was familiar with of circuit design.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing this exposure unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, its with after claims be as the criterion.
According to the inspection method and the device thereof of the antenna effect of the integrated circuit that one embodiment of the invention provided, be by the maximal value of each node of statistics to the accumulation antenna effect value that described element caused, reach and reduce the purpose that each element is verified number of times.Required time when significantly whether each node of reduced inspection meets an antenna effect and check rule in view of the above, and reach the purpose of the antenna effect of quickening to check integrated circuit.
Inspection method and device thereof according to the antenna effect of the integrated circuit that one embodiment of the invention provided, be further to add up the minimum value of each node, meet described antenna effect and check rule so that the node of all connections is neither under the node that does not meet described antenna effect inspection rule that described inspection method is reported to the accumulation antenna effect value that described element caused.In view of the above, can make circuit designer more conveniently to revise described integrated circuit according to report provided by the present invention.
Fig. 5 shows the process flow diagram according to the inspection method of the antenna effect of the integrated circuit of one embodiment of the invention.In step 502, the node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit, and enters step 504.In step 504, begin successively to add up the maximal value of each node from the node of the undermost metal level of described integrated circuit, and enter step 506 the accumulation antenna effect value that described element caused toward the node of the metal level on upper strata.In step 506, check the maximal value of the accumulation antenna effect value of each node successively toward the node of the metal level of lower floor from the node of the metal level of the superiors of described integrated circuit, if, then defining described node less than a critical value, the maximal value of the accumulation antenna effect value of existence one node meets antenna effect inspection rule.
In one embodiment of this invention, to be described node add the above node in its maximum in maximal value of the accumulation antenna effect value in the node that connected of one deck metal level down to the antenna effect value of described element to the maximal value of the accumulation antenna effect value of arbitrary node.In another embodiment of the present invention, the antenna effect value of arbitrary node is that the metallic area of described node is divided by the gate area of described node to its corresponding element.In another embodiment of the present invention, the antenna effect value of arbitrary node is that the metal girth of described node is divided by the gate area of described node to its corresponding element.In another embodiment of the present invention, the node of each layer metal level is corresponding to different critical values.
If the inspection method of the antenna effect of the integrated circuit that application is shown in Figure 5 is in the integrated circuit (IC) chip of Fig. 4, in step 502, the node of each metal level that calculates described integrated circuit (IC) chip 400 is to the antenna effect value that each element caused of described integrated circuit (IC) chip 400.In the present embodiment, the antenna effect value of arbitrary node be the metallic area of described node divided by the gate area of described node to its corresponding element, and the maximal value of the accumulation antenna effect value of arbitrary node to be described node add the above node in its maximum in maximal value of the accumulation antenna effect value in the node that connected of one deck metal level down to the antenna effect value of described element.In view of the above, node N
1,1The antenna effect value be described node N
1,1Metal connecting line area divided by described element P
1Gate area.Node N
2,1The antenna effect value be described node N
2,1Metal connecting line area divided by described element P
1To P
5Gate area and.The rest may be inferred, and the area of all the other nodes all can be calculated.
At the second layer metal layer, node N
2,1The maximal value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,1To N
1,5In the maximal value of accumulation antenna effect value in the maximum.In the present embodiment, node N
1,1The maximal value of accumulation antenna effect value greater than node N
1,2, N
1,3, N
1,4And N
1,5The maximal value of accumulation antenna effect value, so node N
2,1The maximal value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,1The maximal value of accumulation antenna effect value.The rest may be inferred, all the other node N
2,2To N
2,5The maximal value of accumulation antenna effect value all can be calculated.
At the three-layer metal layer, node N
3,1The maximal value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,1To N
2,5In the maximal value of accumulation antenna effect value in the maximum.In the present embodiment, node N
2,1The maximal value of accumulation antenna effect value greater than node N
2,2, N
2,3, N
2,4And N
2,5The maximal value of accumulation antenna effect value, so node N
3,1The maximal value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,1The maximal value of accumulation antenna effect value.
In step 506, from the node N of the metal level of the superiors of described integrated circuit (IC) chip 400
3,1The node of the metal level of past lower floor is checked the maximal value of the accumulation antenna effect value of each node successively, meets antenna effect inspection rule if the maximal value of the accumulation antenna effect value of existence one node, then defines described node less than a critical value.In the present embodiment, node N
2,1The maximal value of accumulation antenna effect value less than a critical value, so defined node N
2,1Meet an antenna effect and check rule.
Compared to the inspection method of the antenna effect of existing integrated circuits shown in Figure 3, according to the inspection method of the antenna effect of the integrated circuit of the embodiment of Fig. 5, it is remarkable minimizing that each element is verified number of times.When check out a node in step 506, on behalf of all following nodes of described node, the maximal value of its accumulation antenna effect value promptly all meet an antenna effect and is checked rule less than a critical value.In view of the above, promptly do not need further to check all nodes below the described node, and reach time saving purpose.In other words, do not need the described element of a large amount of duplicate tests when different nodes are checked, so spent time can save the antenna effect of checking integrated circuit the time.
The process flow diagram of the inspection method of the antenna effect of Fig. 6 demonstration integrated circuit according to another embodiment of the present invention.In step 602, the node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit, and enters step 604.In step 604, begin successively to add up maximal value and the minimum value of each node from the node of the undermost metal level of described integrated circuit, and enter step 606 the accumulation antenna effect value that described element caused toward the node of the metal level on upper strata.In step 606, check the maximal value of the accumulation antenna effect value of each node successively toward the node of the metal level of lower floor from the node of the metal level of the superiors of described integrated circuit, if the maximal value of the accumulation antenna effect value of existence one node is greater than a critical value, then define described node and be not inconsistent unification antenna effect inspection rule, and enter step 608.In step 608, if institute define do not meet described node memory that described antenna effect checks rule in the minimum value of the accumulation antenna effect value of a node greater than described critical value, then repaying described node, not meet described antenna effect inspection regular.
If the inspection method of the antenna effect of the integrated circuit that application is shown in Figure 6 is in the integrated circuit (IC) chip of Fig. 4, in step 602, the node of each metal level that calculates described integrated circuit (IC) chip 400 is to the antenna effect value that each element caused of described integrated circuit (IC) chip 400.In the present embodiment, the antenna effect value of arbitrary node be the metallic area of described node divided by the gate area of described node to its corresponding element, and the maximal value of the accumulation antenna effect value of arbitrary node to be described node add the above node in its maximum in maximal value of the accumulation antenna effect value in the node that connected of one deck metal level down to the antenna effect value of described element.In view of the above, node N
1,1The antenna effect value be described node N
1,1Metal connecting line area divided by described element P
1Gate area.Node N
2,1The antenna effect value be described node N
2,1Metal connecting line area divided by described element P
1To P
5Gate area and.The rest may be inferred, and the area of all the other nodes all can be calculated.
In step 604, from the node N of the undermost metal level of described integrated circuit (IC) chip 400
1,1To N
1,25The beginning node of the metal level on past upper strata is successively added up each node to described element P
1To P
25The maximal value and the minimum value of the accumulation antenna effect value that is caused.Because node N
1,1To N
1,25There is no the metal level of lower floor, so node N
1,1To N
1,25The maximal value and the minimum value of accumulation antenna effect value promptly equal its antenna effect value.
At the second layer metal layer, node N
2,1The maximal value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,1To N
1,5In the maximal value of accumulation antenna effect value in the maximum, and node N
2,1The minimum value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,1To N
1,5In the maximal value of accumulation antenna effect value in minimum value.In the present embodiment, node N
1,1The maximal value of accumulation antenna effect value greater than node N
1,2, N
1,3, N
1,4And N
1,5The maximal value of accumulation antenna effect value, and N
1,2The minimum value of accumulation antenna effect value less than node N
1,1, N
1,3, N
1,4And N
1,5The minimum value of accumulation antenna effect value.In view of the above, node N
2,1The maximal value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,1The maximal value of accumulation antenna effect value, and node N
2,1The minimum value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,2The minimum value of accumulation antenna effect value.The rest may be inferred, all the other node N
2,2To N
2,5The maximal value and the minimum value of accumulation antenna effect value all can be calculated.
At the three-layer metal layer, node N
3,1The maximal value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,1To N
2,5In the maximal value of accumulation antenna effect value in the maximum, and node N
3,1The minimum value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,1To N
2,5In the minimum value of accumulation antenna effect value in reckling.In the present embodiment, node N
2,1The maximal value of accumulation antenna effect value greater than node N
2,2, N
2,3, N
2,4And N
2,5The maximal value of accumulation antenna effect value, and node N
2,2The minimum value of accumulation antenna effect value less than node N
2,1, N
2,3, N
2,4And N
2,5The minimum value of 5 accumulation antenna effect value.In view of the above, so node N
3,1The maximal value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,1The maximal value of accumulation antenna effect value, and so node N3, the minimum value of 1 accumulation antenna effect value is node N
3,1The antenna effect value add node N
2,2The minimum value of accumulation antenna effect value.
In step 606, from the node N of the metal level of the superiors of described integrated circuit (IC) chip 400
3,1Check the maximal value of the accumulation antenna effect value of each node successively toward the node of the metal level of lower floor, be not inconsistent the unification antenna effect and check rule if the maximal value of accumulation antenna effect value that has a node, then defines described node greater than a critical value.In the present embodiment, node N
3,1And node N
2,1The maximal value of accumulation antenna effect value all greater than a critical value, so definition N
3,1And node N
2,1The neither antenna effect that meets is checked rule.
In step 608, if the described node N that does not meet described antenna effect inspection rule that defines
3,1And node N
2,1The minimum value of the accumulation antenna effect value of interior existence one node is then repaid described node and is not met described antenna effect inspection rule greater than described critical value.In the present embodiment, because node N
3,1The minimum value of accumulation antenna effect value be node N
3,1The antenna effect value add node N
2,2The minimum value of accumulation antenna effect value, it is not greater than described critical value, so do not repay node N
3,1On the other hand, because node N
2,1The minimum value of accumulation antenna effect value be node N
2,1The antenna effect value add node N
1,2The minimum value of accumulation antenna effect value, it is greater than described critical value, so repayment node N
2,1
In one embodiment of this invention, step 606 and 608 is to carry out with recursive fashion (recursive), the maximal value of accumulation antenna effect value of also even finding a node when step 606 is greater than a critical value, and the minimum value of the accumulation antenna effect value of described node is less than described critical value, then continue the lower level node of the described node of check, the minimum value of accumulation antenna effect value of finding a node when satisfying step 608 is repaid described node during greater than described critical value.It should be noted that in this recursive fashion accumulation antenna effect value need deduct the contribution margin of described node when down checking its lower level node by a node.
Shown in above-mentioned embodiment, according to the node that the inspection method of the antenna effect of the integrated circuit that Fig. 6 provided is reported, all nodes of its lower floor also do not meet described antenna effect and check rule.In view of the above, circuit designer can the more convenient integrated circuit of checking according to the report correction that it provided.
In part embodiment of the present invention, the inspection method of the antenna effect of Fig. 5 and integrated circuit shown in Figure 6 is operated according to dynamic programming algorithm (dynamic programming).
Fig. 7 shows the synoptic diagram according to the testing fixture of the antenna effect of the integrated circuit of one embodiment of the invention.As shown in Figure 7, described device 700 comprises a computing unit 702, statistics unit 704, an inspection unit 706 and a control module 708.Described computing unit 702 is to calculate the node of each metal level of an integrated circuit to the antenna effect value that each element caused of described integrated circuit.Described statistic unit 704 is the maximal values of adding up the accumulation antenna effect value of each node according to the result of calculation of described computing unit 702.Described inspection unit 706 is to check according to the statistics of described statistic unit 704 whether each node meets an antenna effect and check rule.Described control module 708 is to control described computing unit 702, described statistic unit 704 and described inspection unit 706 according to dynamic programming algorithm.
In one embodiment of this invention, described statistic unit 704 is according to each node the antenna effect value of described element to be added the above each node in its maximal value of the accumulation antenna effect value of described each node of the maximum statistics in the maximal value of the accumulation antenna effect value in the node that connected of one deck metal level down.In another embodiment of the present invention, described computing unit 702 is antenna effect values of divided by described each node the gate area of its corresponding element being calculated described each node according to the metallic area of each node.In another embodiment of the present invention, described computing unit 702 is antenna effect values of divided by described each node the gate area of its corresponding element being calculated described each node according to the metal girth of each node.In an embodiment more of the present invention, described inspection unit 706 is maximal values of checking the accumulation antenna effect value of each node from the node of the metal level of the superiors successively toward the node of the metal level of lower floor.In an embodiment more of the present invention, described statistic unit 704 is the minimum value of adding up the accumulation antenna effect value of each node in addition according to the result of calculation of described computing unit 702.In an embodiment more of the present invention, described inspection unit 706 is minimum value of checking the accumulation antenna effect value of each node from the node of the metal level of the superiors successively toward the node of the metal level of lower floor.Described statistic unit 704 is according to each node the antenna effect value of described element to be added the above each node in its minimum value of the accumulation antenna effect value of described each node of reckling statistics in the minimum value of the accumulation antenna effect value in the node that connected of one deck metal level down.In an embodiment more of the present invention, described statistic unit 704 is maximal value and minimum value that the node by undermost metal level begins successively to add up toward the node of the metal level on upper strata the accumulation antenna effect value of each node.In another embodiment of the present invention, the node of different layers metal level is corresponding to different critical values.
In one embodiment of this invention, described computing unit 702 is to have calculated the node of each metal level of an integrated circuit to the antenna effect value that each element caused of described integrated circuit, result of calculation is given described statistic unit 704 again.Described statistic unit 704 is the maximal value and the minimum value of having added up the accumulation antenna effect value of each node, statistics is given described inspection unit 706 again.Described inspection unit 706 checks then whether described each node meets an antenna effect and check rule.
In another embodiment of the present invention, described computing unit 702 is its antenna effect values that element caused that contain of a single node of having calculated an integrated circuit, is about to result of calculation and gives described statistic unit 704.Described statistic unit 704 is maximal value and minimum value of the accumulation antenna effect value of the described single node of statistics, statistics is given described inspection unit 706 again.Described inspection unit 706 checks then whether described node meets an antenna effect and check rule.
In another embodiment of the present invention, described computing unit 702 is antenna effect values that element caused that local nodes contained of having calculated an integrated circuit, and is about to result of calculation and gives described statistic unit 704.Wherein said local nodes is all nodes in a social strata relation.Described statistic unit 704 is maximal value and minimum value of the accumulation antenna effect value of the described local nodes of statistics, statistics is given described inspection unit 706 again.Described inspection unit 706 checks then whether described local nodes meets an antenna effect and check rule.Device shown in Figure 7 can be realized by hardware mode, can also utilize a hardware to realize by software.For example, can carry out a software program and realize described device by a computing machine.
In sum, the inspection method of the antenna effect of integrated circuit provided by the present invention and device thereof are to reach the purpose that each element of minimizing is verified number of times by adding up the maximal value of each node to the accumulation antenna effect value that described element caused.In view of the above, required time when whether each node of reduced inspection meets an antenna effect and check rule significantly, and reach the purpose of the antenna effect of quickening to check integrated circuit.
Technology contents of the present invention and technical characterstic disclose as above, yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (24)
1. the inspection method of the antenna effect of an integrated circuit is characterized in that comprising the following step:
The node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit;
Add up the maximal value of each node to the accumulation antenna effect value that described element caused; And
If there is a node, the maximal value of its accumulation antenna effect value then defines described node and meets antenna effect inspection rule less than a critical value.
2. inspection method according to claim 1, it is characterized in that wherein to be described node add the above node in its maximum in maximal value of the accumulation antenna effect value in the node that connected of one deck metal level down to the antenna effect value of described element to the maximal value of the accumulation antenna effect value of arbitrary node.
3. inspection method according to claim 1 is characterized in that, wherein the antenna effect value of arbitrary node is that the metallic area of described node is divided by the gate area of described node to its corresponding element.
4. inspection method according to claim 1 is characterized in that, the antenna effect value of its arbitrary node is that the metal girth of described node is divided by the gate area of described node to its corresponding element.
5. inspection method according to claim 1 is characterized in that, it further comprises the following step:
Check the maximal value of the accumulation antenna effect value of each node successively toward the node of the metal level of lower floor from the node of the metal level of the superiors.
6. inspection method according to claim 1 is characterized in that, it further comprises the following step:
Add up the minimum value of each node to the accumulation antenna effect value of described element; And
If there is a node, the minimum value of its accumulation antenna effect value reports then that greater than a critical value described node does not meet described antenna effect and checks rule.
7. inspection method according to claim 6 is characterized in that, it further comprises the following step:
Check the minimum value of the accumulation antenna effect value of each node successively toward the node of the metal level of lower floor from the node of the metal level of the superiors.
8. inspection method according to claim 6, it is characterized in that wherein to be described node add the above node in its reckling in minimum value of the accumulation antenna effect value in the node that connected of one deck metal level down to the antenna effect value of described element to the minimum value of the accumulation antenna effect value of arbitrary node.
9. inspection method according to claim 1 is characterized in that, the peaked step of the accumulation antenna effect value of wherein said each node of statistics is that the node by undermost metal level begins successively toward the node statistics of the metal level on upper strata.
10. inspection method according to claim 6 is characterized in that, the step of the minimum value of the accumulation antenna effect value of wherein said each node of statistics is that the node by undermost metal level begins successively toward the node statistics of the metal level on upper strata.
11. inspection method according to claim 1 is characterized in that, the node that wherein is positioned at the different layers metal level is corresponding to different critical values.
12. inspection method according to claim 1 is characterized in that it is operated according to dynamic programming algorithm.
13. the testing fixture of the antenna effect of an integrated circuit is characterized in that comprising:
One computing unit, the node of each metal level that calculates an integrated circuit is to the antenna effect value that each element caused of described integrated circuit;
One adds up the unit, adds up the maximal value of the accumulation antenna effect value of each node according to the result of calculation of described computing unit; And
One inspection unit checks according to the statistics of described statistic unit whether each node meets an antenna effect and check rule.
14. device according to claim 13, it is characterized in that, wherein said statistic unit be according to each node to the antenna effect value of described element add the above each node in its down the maximum in the maximal value of the accumulation antenna effect value in the node that connected of one deck metal level add up the maximal value of the accumulation antenna effect value of described each node.
15. device according to claim 13 is characterized in that, wherein said computing unit is an antenna effect value of divided by described each node the gate area of its corresponding element being calculated described each node according to the metallic area of each node.
16. device according to claim 13 is characterized in that, wherein said computing unit is an antenna effect value of divided by described each node the gate area of its corresponding element being calculated described each node according to the metal girth of each node.
17. device according to claim 13 is characterized in that, wherein said inspection unit is a maximal value of checking the accumulation antenna effect value of each node from the node of the metal level of the superiors successively toward the node of the metal level of lower floor.
18. device according to claim 13 is characterized in that, wherein said statistic unit is the minimum value of adding up the accumulation antenna effect value of each node in addition according to the result of calculation of described computing unit.
19. device according to claim 18 is characterized in that, wherein said inspection unit is a minimum value of checking the accumulation antenna effect value of each node from the node of the metal level of the superiors successively toward the node of the metal level of lower floor.
20. device according to claim 18, it is characterized in that, wherein said statistic unit be according to each node to the antenna effect value of described element add the above each node in its down the reckling in the minimum value of the accumulation antenna effect value in the node that connected of one deck metal level add up the minimum value of the accumulation antenna effect value of described each node.
21. device according to claim 13 is characterized in that, wherein said statistic unit is the maximal value that the node by undermost metal level begins successively to add up toward the node of the metal level on upper strata the accumulation antenna effect value of each node.
22. device according to claim 18 is characterized in that, wherein said statistic unit is the minimum value that the node by undermost metal level begins successively to add up toward the node of the metal level on upper strata the accumulation antenna effect value of each node.
23. device according to claim 13 is characterized in that, the node that wherein is positioned at the different layers metal level is corresponding to different critical values.
24. device according to claim 13 is characterized in that, it further comprises:
One control module, it controls described computing unit, described statistic unit and described inspection unit according to a dynamic programming algorithm.
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| CN200910211394.4A CN102054083B (en) | 2009-10-30 | 2009-10-30 | Method for checking antenna effect of integrated circuit and device thereof |
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| CN200910211394.4A CN102054083B (en) | 2009-10-30 | 2009-10-30 | Method for checking antenna effect of integrated circuit and device thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
| CN107122567A (en) * | 2017-05-23 | 2017-09-01 | 上海华虹宏力半导体制造有限公司 | Module carries out antenna effect inspection method before being incorporated to |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030197175A1 (en) * | 2002-04-17 | 2003-10-23 | Chong-Jen Huang | Test structure for evaluating antenna effects |
| US6862723B1 (en) * | 2002-10-03 | 2005-03-01 | Taiwan Semiconductor Manufacturing Company | Methodology of generating antenna effect models for library/IP in VLSI physical design |
| US20060225007A1 (en) * | 2005-04-05 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co. | Antenna effect prevention by model extraction in a circuit design for advanced processes |
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2009
- 2009-10-30 CN CN200910211394.4A patent/CN102054083B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN102955123B (en) * | 2011-08-19 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
| CN107122567A (en) * | 2017-05-23 | 2017-09-01 | 上海华虹宏力半导体制造有限公司 | Module carries out antenna effect inspection method before being incorporated to |
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| CN102054083B (en) | 2015-07-01 |
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