CN102054077A - Method and device for correcting circuit layout - Google Patents
Method and device for correcting circuit layout Download PDFInfo
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- CN102054077A CN102054077A CN2009102113874A CN200910211387A CN102054077A CN 102054077 A CN102054077 A CN 102054077A CN 2009102113874 A CN2009102113874 A CN 2009102113874A CN 200910211387 A CN200910211387 A CN 200910211387A CN 102054077 A CN102054077 A CN 102054077A
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Abstract
The invention relates to a method and device for correcting a circuit layout. The method for correcting the circuit layout comprises the following steps: contrasting an original circuit netlist with a corresponding layout circuit netlist thereof, and then respectively making correct contrast blocks and error contrast blocks; generating a child layout circuit netlist in accordance with the error contrast blocks in an updated layout; according to the child layout circuit netlist, updating the layout circuit netlist; and contrasting the original circuit netlist with the circuit netlist of the updated layout.
Description
Technical field
The invention relates to the method and apparatus of a kind of circuit layout (layout), especially about the method and the device thereof of correction circuit layout.
Background technology
In most of circuit design flow process, at first produce the ifq circuit net table (netlist) of circuit by circuit designer.For example, in Design of Digital Circuit, the hardware description language that the circuit composite software can be write according to circuit designer, for example verilog or VHDL produce the ifq circuit net table of described circuit.In Analog Circuit Design, the circuit composite software can produce the ifq circuit net table of described circuit according to the circuit theory diagrams (schematic) that circuit designer is described.Then, circuit designer can verify whether its function meets expection at described ifq circuit net table.If described ifq circuit net table is by checking, then it just is regarded as the template of the circuit meshwork list of later release.
Because described ifq circuit net table only comprises the information of element that described circuit uses, and do not comprise its real physical characteristics, for example various stray capacitance inductive effects etc. are so described ifq circuit net table can't be used for accurately estimating its function and whether satisfy design requirement on the time.In view of the above, circuit designer can utilize layout coiling software that coiling is put and produced to each element of described ifq circuit net table.The described layout coiling archives that software produced, for example (graphic data system, GDS) archives promptly comprise the layout of described circuit and the data of coiling to graphic data system.
Then, circuit designer can be utilized layout principle of contrast figure (layout versus schematic, LVS) whether software to contrast the graphic data system of described ifq circuit net table and described circuit consistent.Described layout principle of contrast figure software at first produces a layout circuit net table according to the graphic data system of described circuit, and is contrasted at described ifq circuit net table and described layout circuit net table.If comparing result is inconsistent, then circuit designer can be revised the layout and the coiling of described circuit according to comparing result, that is produces a graphic data system of upgrading, and contrasts the graphic data system of described ifq circuit net table and described renewal more again.
Fig. 1 shows the method for existing correction circuit layout.In step 102, contrast an ifq circuit net table and corresponding layout circuit net table thereof, and enter step 104.In step 104, check whether comparing result has inconsistent.If, then enter step 106, otherwise method ends.In step 106, the layout of refresh circuit, and enter step 108.In step 108, produce a layout circuit net table that upgrades according to the layout after upgrading, and get back to step 102.
As shown in Figure 1, circuit designer is promptly by continuous correction circuit layout and contrast the layout circuit net table of described ifq circuit net table and renewal, in the hope of reaching the on all four circuit layout of contrast.Yet in step 108, the described action that produces layout circuit net table according to layout often needs expends tens of hours, so that the method for described correction circuit layout needs the plenty of time just to be accomplished.Therefore, for the circuit design industry of pursuing timeliness and cost, how quickening the correction circuit layout promptly is instant subject under discussion.
In view of the above, industry is needed to be a kind of method and device thereof, and spent time when it can compress the correction circuit layout significantly is so that the entire circuit design cycle can be more efficient.
Summary of the invention
Utilization of the present invention significantly reduces the layout circuit net table of required generation, and significantly reduces the required execution time.And, can reach the purpose of quickening the correction circuit layout owing to only need contrast local block.
The invention provides a kind of method of correction circuit layout, comprise the following step: contrast an ifq circuit net table and corresponding layout circuit net table thereof, and indicate correct block of contrast and the wrong block of contrast respectively; Produce a sub-layout circuit net table according to the wrong block of contrast in the layout after upgrading; Upgrade described layout circuit net table according to described sub-layout circuit net table; And the layout circuit net table that contrasts described ifq circuit net table and described renewal.
The invention provides a kind of device that is used for the correction circuit layout, described device comprises an extracting unit, a contrast unit, indicates a unit and a updating block.Described extracting unit is to produce a layout circuit net table according to a layout.Described contrast unit is contrast one an ifq circuit net table and a layout circuit net table.Described sign unit is to indicate correct block and the wrong block of contrast of contrast in the comparing result that described contrast unit provided.Described updating block is that the layout circuit net table that provides according to described extracting unit upgrades an original layout circuit net table.
Description of drawings
Fig. 1 shows the method for existing correction circuit layout;
Fig. 2 shows the synoptic diagram according to a circuit of one embodiment of the invention;
Fig. 3 shows the layout according to a circuit of one embodiment of the invention;
Fig. 4 shows the circuit diagram according to a layout circuit net table of one embodiment of the invention;
Fig. 5 shows the figure according to one embodiment of the invention;
Fig. 6 shows the process flow diagram according to the method for the correction circuit layout of one embodiment of the invention;
Fig. 7 shows the layout according to a circuit of one embodiment of the invention; And
Fig. 8 shows the schematic representation of apparatus that is used for the correction circuit layout according to one embodiment of the invention.
Embodiment
The method of correction circuit layout provided by the present invention and device thereof, be by indicating block correct and wrong in the comparing result, and when producing the layout circuit net table that upgrades, only produce the corresponding layout circuit net table that contrasts wrong block, and only contrast the local block that makes a mistake according to the layout after the renewal.Because the layout circuit net table of required generation significantly reduces, its required execution time also significantly reduces, and owing to only need contrast local block, so can reach the purpose of quickening the correction circuit layout.
Fig. 2 shows the synoptic diagram according to a circuit of one embodiment of the invention, and wherein said circuit can be that circuit designer is described or produced by the circuit composite software.As shown in Figure 2, described circuit comprises two and door and a rejection gate.The ifq circuit net table of described circuit can be by following expression:
.subckt?AOI?VDD?GND?A0?A1?B0?B1
Y
x101?A0?A11?AND
x102?B0?B1?2AND
x103?12Y?NOR
.eom
Fig. 3 shows that the layout of wherein said circuit is the circuit corresponding to Fig. 2 according to the layout of a circuit of one embodiment of the invention.In the circuit design flow process, be respectively the ifq circuit net table of described circuit and the graphic data system archives of layout thereof to be imported a layout principle of contrast figure software.Described layout principle of contrast figure software at first produces a layout circuit net table according to described graphic data system archives.
Fig. 4 shows the circuit theory diagrams of a layout principle of contrast figure software according to the layout circuit net table that circuit arrangement map produced of Fig. 3.As shown in Figure 4, described circuit theory diagrams are to realize with the CMOS processing procedure, and are made up of several PMOS P1 to P4 and several NMOS N1 to N4.In view of the above, whether the circuit theory diagrams of the circuit theory diagrams that described layout principle of contrast figure software can comparison diagram 2 and Fig. 4 equate.
Secondly, described layout principle of contrast figure software produces corresponding figure at described ifq circuit net table and described layout circuit net table respectively.Fig. 5 shows the figure that circuit theory diagrams produced of described layout principle of contrast figure software at Fig. 4.Similar, described layout principle of contrast figure software also produces corresponding figure at the circuit theory diagrams of Fig. 2.Whether described layout principle of contrast figure software promptly has homotypy (isomorphism) at the respective graphical of described circuit theory diagrams, that is two figures whether essence equates.If unequal, described layout principle of contrast figure software can propose report at the contrast error section.Circuit designer just can be revised circuit layout at this report.Yet as previously mentioned, the method for existing correction circuit layout expends the too much time in the process according to graphic data system archives generation layout circuit net table.
Fig. 6 shows the process flow diagram according to the method for the correction circuit layout of one embodiment of the invention.In step 602, contrast an ifq circuit net table and corresponding layout circuit net table thereof, and enter step 604.In step 604, check whether comparing result has inconsistent.If, then enter step 606, otherwise method ends.In step 606, indicate correct block of contrast and the wrong block of contrast respectively according to comparing result, and enter step 608.In step 608, the layout of refresh circuit, and enter step 610.In step 610, produce a sub-layout circuit net table according to the wrong block of contrast in the layout after upgrading, and enter step 612.In step 612, upgrade described layout circuit net table according to described sub-layout circuit net table, and enter step 614.In step 614, contrast the wrong block of contrast in the layout circuit net table of described ifq circuit net table and described renewal, and get back to step 604.
Fig. 7 shows the layout according to a circuit of one embodiment of the invention.As shown in Figure 7, described circuit 700 comprises a static RAM (SRAM) 702, an ALU 704 (ALU), one first blocks 706 (IP), one second blocks 708 and soft macroelement 710 blocks such as (softmacro).
Following example is used the method for the correction circuit layout of one embodiment of the invention in the circuit layout of Fig. 7.In step 602, the circuit layout of comparison diagram 7 and corresponding ifq circuit net table thereof.In step 604, check whether comparing result has inconsistent.In the present embodiment, described soft macroelement 710 and its corresponding ifq circuit net table of the circuit layout of Fig. 7 are inconsistent, so enter step 606.In step 606, indicate the correct block of contrast according to comparing result, that is described static RAM, described ALU, described first blocks and described second blocks and the described static RAM 702 in the described circuit layout, described ALU 704, described first blocks 706 and described second blocks 708 that indicate in the described ifq circuit net table are corresponding and contrast correct block.Simultaneously, indicate the wrong block of contrast, that is interior described soft macroelement and the described soft macroelement 710 in the described circuit layout of described ifq circuit net table is block corresponding and that contrast is wrong.In the present embodiment, be in information storage to archives with described block, the stored data of wherein said archives comprise described contrast and correctly reach the title of the wrong block of contrast and the hierarchical structure relation of each block.In other words, the described wrong block of contrast that is denoted as only comprises the wrong affected block of block and upper strata thereof of bottom contrast.
In step 608, upgrade the wrong circuit blocks of contrast in the layout, that is upgrade the layout of described soft macroelement 710, and enter step 610.In step 610, produce a sub-layout circuit net table according to the wrong block of contrast in the layout after upgrading.Though the graphic data system archives of the layout after upgrading still comprise blocks such as described static RAM 702, described ALU 704, described first blocks 706, described second blocks 708 and described soft macroelement 710, archives according to the storage comparing result that step 606 produced can only produce its corresponding sub-layout circuit net table at described soft macroelement 710, that is described sub-layout circuit net table only comprises the circuit component in the described soft macroelement 710.Method compared to existing correction circuit layout, if the method for the correction circuit layout of application drawing 1 is in the circuit layout of Fig. 7, even only upgrade the layout of described soft macroelement 710 in step 106, when step 108, the method for described existing correction circuit layout still can produce all layout circuit net tables at blocks such as described static RAM 702, described ALU 704, described first blocks 706, described second blocks 708 and described soft macroelements 710.In view of the above, the method for correction circuit layout of the present invention can reduce the time that produces the circuit meshwork list of described renewal layout when upgrading layout significantly.
In step 612, upgrade described layout circuit net table according to described sub-layout circuit net table.In the present embodiment, be about to corresponding position in the original layout circuit net table of described sub-layout circuit net table replacement, also be about to the described soft macroelement 710 of sub-layout circuit net table replacement in the layout circuit net table that step 602 is used to contrast at the described soft macroelement 710 of step 610 generation.If as follows in the layout circuit net table that step 602 is used to contrast:
.CELL?TOP
.INSTA＝SRAM{…}
.INST?B＝ALU{…}
.INST?C＝IP1{…}
.INST?D＝IP2{…}
.INST?E＝SOFT_MACRO{…}
Then step 612 only can be at the element in the described soft macroelement 710, that is SOFT_MACRO{ ... content in the bracket replaces.
In step 614, contrast the wrong block of contrast in the layout circuit net table of described ifq circuit net table and described renewal.In the present embodiment, promptly the correct block of contrast in the layout circuit net table of described ifq circuit net table and described renewal is indicated in black box mode (black box) according to the archives of the storage comparing result that step 606 produced.In view of the above, the figure that produces according to the described block that indicates in the black box mode is only to comprise a primary element (primitive), that is a point.In other words, when whether the respective graphical contrast at the layout circuit net table of described ifq circuit net table and described renewal has homotypy, in fact only need contrast the respective graphical of described soft macroelement 710.Method compared to existing correction circuit layout, if the method for the correction circuit layout of application drawing 1 is in the circuit layout of Fig. 7, even only upgrade the layout of described soft macroelement in step 106, when step 102, the method for described existing correction circuit layout still can be contrasted at the respective graphical of blocks such as described static RAM 702, described ALU 704, described first blocks 706, described second blocks 708 and described soft macroelement 710.In view of the above, the method for correction circuit layout of the present invention can reduce the time of the layout circuit net table of described ifq circuit net table of contrast and described renewal significantly.
Fig. 8 shows the schematic diagram according to the device that is used for the correction circuit layout of one embodiment of the invention.As shown in Figure 8, described device 800 comprises an extracting unit 802, a contrast unit 804, indicates unit 806, a updating block 808 and an access unit 810.Described extracting unit 802 is to produce a layout circuit net table according to a layout.Described contrast unit 804 is contrast one an ifq circuit net table and a layout circuit net table.Described sign unit 806 is to indicate correct block and the wrong block of contrast of contrast in the comparing result that described contrast unit 804 provided.Described updating block 808 is to upgrade an original layout circuit net table according to the layout circuit net table that described extracting unit 802 is provided.Described access unit 810 is that the block information that described sign unit 806 is provided is stored to archives and reads described archives.
In one embodiment of this invention, the block information that described access unit 810 stores comprises described contrast and correctly reaches the title of the wrong block of contrast and the hierarchical structure relation of each block, and described updating block 808 is that the layout circuit net table that described extracting unit 802 is provided is replaced corresponding position in described original layout circuit net table.
Following example is used the device that is used for the correction circuit layout of one embodiment of the invention in the circuit layout of Fig. 7.Described extracting unit 802 at first produces a layout circuit net table at the circuit layout of Fig. 7.Described contrast unit 804 promptly contrasts a described layout circuit net table and a corresponding ifq circuit net table.Described sign unit 806 is to indicate correct block and the wrong block of contrast of contrast in the comparing result that described contrast unit 804 provided.Described access unit 810 is that the block information that described sign unit 806 is provided is stored to archives.Layout after described extracting unit 802 upgrades at one according to described archives again produces a sub-layout circuit net table.Described updating block 808 is to upgrade described original layout circuit net table according to the sub-layout circuit net table that described extracting unit 802 is provided.Described contrast unit 804 promptly contrasts the layout circuit net table and the described ifq circuit net table of described renewal according to described archives.
Device shown in Figure 8 can be realized by hardware mode, can also utilize a hardware to realize by software.For example, can carry out a software program and realize described device by a computing machine.
In sum, the method of correction circuit layout provided by the present invention and device thereof, be by indicating block correct and wrong in the comparing result, and when producing the layout circuit net table that upgrades according to the layout after upgrading, only produce the layout circuit net table of the wrong block of corresponding contrast, and when contrast, only compare according to the wrong block of previous contrast.Because the layout circuit net table of required generation reduces significantly, its required time also significantly reduces, and owing to only need contrast local block, so can reach the purpose of quickening the correction circuit layout.
Technology contents of the present invention and technical characterstic disclose as above, yet those of ordinary skill in the art still may be based on teaching of the present invention and announcements and done all replacement and modifications that does not deviate from spirit of the present invention.Therefore, protection scope of the present invention should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present invention and modifications, and is contained by the present patent application claim.
Claims (16)
1. the method for a correction circuit layout is characterized in that comprising the following step:
Contrast an ifq circuit net table and corresponding layout circuit net table thereof, and indicate correct block of contrast and the wrong block of contrast respectively;
Produce a sub-layout circuit net table according to the wrong block of contrast in the layout after upgrading;
Upgrade described layout circuit net table according to described sub-layout circuit net table; And
Contrast the layout circuit net table of described ifq circuit net table and described renewal.
2. method according to claim 1 is characterized in that, the step of the layout circuit net table of wherein said contrast described ifq circuit net table and described renewal only contrasts the wrong block of contrast in the layout circuit net table of described ifq circuit net table and described renewal.
3. method according to claim 1 is characterized in that, wherein said sign step is in information storage to archives with described block.
4. method according to claim 3 is characterized in that, wherein the information of the described block of Chu Cuning comprises the title that described contrast correctly reaches the wrong block of contrast.
5. method according to claim 3 is characterized in that, wherein the information of the described block of Chu Cuning comprises the hierarchical structure relation of each block.
6. method according to claim 1 is characterized in that, the step of the described layout circuit net of wherein said renewal table is that described sub-layout circuit net table is replaced corresponding position in the described layout circuit net table.
7. method according to claim 1 is characterized in that, the step of the wrong block of contrast is that the correct block of contrast is indicated and contrasted in the black box mode in the layout circuit net table of wherein said contrast ifq circuit net table and renewal.
8. method according to claim 7 is characterized in that, wherein the block that indicates in the black box mode is represented a primary element in contrast Shi Shi.
9. the device of a correction circuit layout is characterized in that comprising:
One extracting unit produces a layout circuit net table according to a layout;
One contrast unit contrasts an ifq circuit net table and a layout circuit net table;
One indicates the unit, indicates correct block and the wrong block of contrast of contrast in the comparing result that described contrast unit provided; And
One updating block upgrades an original layout circuit net table according to the layout circuit net table that described extracting unit provided.
10. device according to claim 9 is characterized in that it further comprises:
One access unit, the block information that described sign unit is provided is stored to archives and reads described archives.
11. device according to claim 10, it is characterized in that, wherein said contrast unit is that the described archives that read according to described access unit compare, and only contrasts and indicate the wrong block of contrast in the layout circuit net table of described ifq circuit net table and described renewal.
12. device according to claim 10 is characterized in that, wherein the information of the described block of Chu Cuning comprises the title that described contrast correctly reaches the wrong block of contrast.
13. device according to claim 10 is characterized in that, wherein the information of the described block of Chu Cuning comprises the hierarchical structure relation of each block.
14. device according to claim 9 is characterized in that, wherein said updating block is that the layout circuit net table that described extracting unit is provided is replaced corresponding position in described original layout circuit net table.
15. device according to claim 9, it is characterized in that wherein said contrast unit is that the archives that read according to described access unit will before contrast correct block and indicate and contrasted in the black box mode when contrast described ifq circuit net table and described layout circuit net table.
16. device according to claim 15 is characterized in that, wherein the block that indicates in the black box mode is represented a primary element in contrast Shi Shi.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102113874A CN102054077A (en) | 2009-10-30 | 2009-10-30 | Method and device for correcting circuit layout |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102113874A CN102054077A (en) | 2009-10-30 | 2009-10-30 | Method and device for correcting circuit layout |
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| CN102054077A true CN102054077A (en) | 2011-05-11 |
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| CN2009102113874A Pending CN102054077A (en) | 2009-10-30 | 2009-10-30 | Method and device for correcting circuit layout |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105335570A (en) * | 2015-11-24 | 2016-02-17 | 深圳市兴森快捷电路科技股份有限公司 | Method for netlist comparison based on connection relationship of pins of components |
| CN112416867A (en) * | 2020-12-11 | 2021-02-26 | 北京华大九天软件有限公司 | Method for comparing netlists in batches |
-
2009
- 2009-10-30 CN CN2009102113874A patent/CN102054077A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105335570A (en) * | 2015-11-24 | 2016-02-17 | 深圳市兴森快捷电路科技股份有限公司 | Method for netlist comparison based on connection relationship of pins of components |
| CN105335570B (en) * | 2015-11-24 | 2018-11-06 | 深圳市兴森快捷电路科技股份有限公司 | A method of netlist comparison is carried out based on component pin connection relation |
| US10592631B2 (en) | 2015-11-24 | 2020-03-17 | Guangzhou Fastprint Circuit Tech Co., Ltd. | Method for performing netlist comparison based on pin connection relationship of components |
| CN112416867A (en) * | 2020-12-11 | 2021-02-26 | 北京华大九天软件有限公司 | Method for comparing netlists in batches |
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Application publication date: 20110511 |