CN102034737A - Making method of metal interconnection layer - Google Patents
Making method of metal interconnection layer Download PDFInfo
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- CN102034737A CN102034737A CN2009101965487A CN200910196548A CN102034737A CN 102034737 A CN102034737 A CN 102034737A CN 2009101965487 A CN2009101965487 A CN 2009101965487A CN 200910196548 A CN200910196548 A CN 200910196548A CN 102034737 A CN102034737 A CN 102034737A
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- silicon chip
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- edge zone
- fringe region
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Abstract
The invention discloses a making method of a metal interconnection layer, comprising the following steps of: depositing an insulating layer on the surface of a silicon slice; forming patterns to be etched on the surface of the silicon slice by utilizing a photoetching process; removing photoresist positioned in a marginal area of the silicon slice; etching a groove under the protection of the rest photoresist, and removing the rest photoresist after the etching is completed; forming copper plating layers on the inner wall of the etched groove and the surface of the silicon slice by adopting an electrochemical plating process; cleaning the marginal area of the silicon slice; and grinding the silicon slice to the surface of the insulating layer by adopting a chemical mechanical grinding process. The making method of the metal interconnection layer can be used for preventing the insulating layer from being peeled or generating granules.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of manufacture method of metal interconnecting layer.
Background technology
At present, back segment (BEOL at semiconductor device, back-end-of-line) in the technology, can be according to the different needs multiple layer metal interconnection layer of on Semiconductor substrate, growing, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, and this just need form groove, plated metal in groove then on insulating barrier, the metal of deposition is metal interconnecting wires, generally selects for use copper as metal interconnected wire material.
Fig. 1 is the flow chart of the manufacture method of existing metal interconnecting layer.As shown in Figure 1, may further comprise the steps:
Step 11: at the silicon chip surface depositing insulating layer.
Can adopt depositional modes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).Wherein, PVD is meant and utilizes certain physical process, for example transfer of evaporation or sputter realization material, and promptly atom or ion are transferred to silicon chip surface by the source, and deposit becomes film.Specifically, evaporation is meant heating evaporation source in vacuum system, makes atom obtain to break away from the constraint of metal surface behind enough energy and becomes vapor atomic, and then be deposited on the silicon chip; Sputter is meant and charges into inert gas in vacuum system, and under the high voltage electric field effect, the ion that gas discharge forms is quickened by highfield, and the bombardment target material makes target ion overflow and be splashed on the silicon chip.And CVD is meant and will contains the gaseous reactant of formation film element or steam and required other gas introducing reative cell of liquid reactants, and in the process of silicon chip surface by the chemical reaction film former, the thickness of the film of deposit is directly proportional with deposition time.
In actual applications, can select wherein arbitrary mode as required.Usually, deposition insulating layer adopts the CVD depositional mode.
Step 12: utilize photoetching process to form figure to be etched at silicon chip surface.
Photoetching process is a kind of technology of widely using in the semiconductor fabrication, and its implementation procedure mainly comprises:
1) to silicon chip surface clean, dehydration and film forming handle.
Cleaning comprises wet-cleaned and deionized water rinsing, to remove the pollutant of silicon chip surface, as particle, organic substance and technology remnants etc.; Dehydration causes dried baking and banking up with earth in an enclosed cavity and finishes, to remove most of steam of silicon chip surface; Use HMDS (HMDS) etc. to carry out film forming after the dehydration immediately and handle, to strengthen the adhesion of silicon chip surface.
2) the silicon chip surface spin coating one deck photoresist after processing.
Usually, need that also the photoresist that is spun to silicon chip surface is carried out soft baking and handle,, thereby improve photoresist the adhesion of silicon chip surface and the uniformity of photoresist with the solvent in the removal photoresist.
3) aim at successively, expose and develop.
Light shield is aimed at the tram of silicon chip surface, after the aligning, with light shield and silicon wafer exposure, the figure on the light shield with bright dark feature transfer to the silicon chip that scribbles photoresist.
Development is a kind of important process mode in photoetching process, can utilize developer with the dissolving of the zone of the solubilized on the photoresist, and visible figure is stayed silicon chip surface.
Follow-up, also need to carry out post bake and bake and bank up with earth, the heat baking after promptly developing is handled, and to remove residual solvent in the photoresist, further improves the adhesion of photoresist to silicon chip surface.
By above-mentioned 1), 2), 3) shown in process, promptly at silicon chip surface, specific in this example, promptly on insulating barrier, formed figure to be etched, as shown in Figure 2, Fig. 2 is for having the silicon chip schematic diagram after photoetching is finished, the wherein zone that the thick line circle in the figure indicates on the left of the figure correspondence on right side now.
Step 13: etching groove under the protection of photoresist, and after etching is finished, remove remaining photoresist.
Etching is a kind of method by physics or chemistry is removed unwanted material selectively from silicon chip surface a process; Two kinds of etching modes are provided in the existing technology, i.e. dry etching and wet etching.Wherein, dry etching is meant silicon chip surface is exposed in the plasma, makes plasma and silicon chip surface by the zone that photoresist is protected physics or chemical reaction not taken place, thereby removes this regional surfacing; And wet etching is meant silicon chip is immersed in certain reagent solution, makes not the surface in the zone of being protected by photoresist and reagent generation chemical reaction and is removed.
After etching is finished,, need to remove the remaining photoresist of silicon chip surface for fear of subsequent technique is impacted.Concrete removing method is not limit, such as, can utilize carbon dioxide (CO
2) remove photoresist, it is as follows specifically to remove process: on the electrostatic chuck of silicon slice placed in reaction chamber, and import CO in reaction chamber
2, by the CO of electrode with input
2Ionization is plasma, and afterwards, oxonium ion that ionization goes out and the organic component generation chemical reaction in the photoresist generate CO
2Etc. air scavenge, to reach the purpose of removing photoresist.Certainly, also can adopt other removing method, such as utilizing lytic agent that photoresist is cleaned.
Fig. 3 is for having the silicon chip schematic diagram after finishing etching and removing photoresist now.
Step 14: adopt electrochemistry plating (ECP) technology to form the copper electrodeposited coating at trench wall that etches and silicon chip surface.
In this step, utilize mechanical arm that silicon chip is moved to the top of electroplating bath, the top of electroplating bath is provided with a plating ring that is used for fixing silicon chip, and promptly the fringe region of silicon chip is clamped by electroplating ring, and is connected to negative electrode by electroplating ring; Afterwards, by mechanical arm silicon chip is immersed in the electroplate liquid that includes copper ion in the electroplating bath, is generally copper sulphate, electroplate liquid connects anode; Between negative electrode and anode, switch on, under electric field action, form the copper electrodeposited coating.
Fig. 4 is the silicon chip schematic diagram behind the existing formation copper electrodeposited coating.
Step 15: the silicon chip edge zone is cleaned.
The copper electrodeposited coating forms and finishes, and after silicon chip is taken out from electroplate liquid, is clamped because the fringe region of silicon chip electroplates ring originally, so do not plate the copper electrodeposited coating substantially, still, burr may occur, for preventing that these burr from impacting subsequent technique, need clean it.
In this step, utilize hydrogen peroxide (H
2O
2), sulfuric acid (H
2SO
4) and the mixed solvent formed of deionized water (DIW), the fringe region of silicon chip is cleaned; Wherein, hydrogen peroxide accounts for 7% of cleaning solvent cumulative volume, and sulfuric acid accounts for 5.5%, and other is a deionized water.
Usually, described fringe region is meant that the silicon chip ragged edge is along the zone that extends into 0.5 millimeter (mm)～2mm to the silicon chip center position.
Silicon chip is fixed on the board, this board can carry out high speed rotating under the driving of motor, its rotating speed is 800～1200 rev/mins, the nozzles spray that is positioned at the board top goes out cleaning solvent, angle by the control nozzle, can make cleaning solvent only be sprayed onto on the fringe region of silicon chip, thereby utilize the strong oxidizing property of hydrogen peroxide and sulfuric acid to come the burr that may occur are cleaned.Clean sustainable 5～10 seconds of duration (s).
Step 16: adopt cmp (CMP) technology with silicon chip grinding to surface of insulating layer.
CMP technology is a kind of surface global planarization, comes the planarization silicon chip surface by the relative motion between silicon chip and the polishing pad.In actual applications, when needs grind, at first with silicon chip attached on the grinding head, to be ground of silicon chip contacted with grinding pad, wherein, grinding pad is fixed on the abrasive disk; Then, abrasive disk and grinding head all are rotated by counter clockwise direction under the driving of motor, but both rotary speed differences, simultaneously, grinding head also carries out radial motion along the diametric(al) of grinding pad; Simultaneously, utilize the lapping liquid supply pipe to carry slurry to grinding pad, chemical action and mechanism by slurry make the silicon chip surface planarization.
In this step, utilize CMP technology with silicon chip grinding to surface of insulating layer.Fig. 5 is for having the silicon chip schematic diagram after grinding now.
So far, promptly finished the making of metal interconnecting layer.
But can there be certain problem in production method shown in Figure 1 in actual applications, because:
When adopting CMP technology that silicon chip is ground, ideally, effect shown in Figure 5 should appear, still, because the fringe region of silicon chip presents structure shown in Figure 4, promptly there is groove, so when grinding, the stress of fringe region and non-fringe region etc. are different, and then may cause the insulating barrier on the fringe region to peel off (peeling), and may form on the non-fringe region of particle attached to silicon chip, thereby silicon chip is polluted.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of manufacture method of metal interconnecting layer, can avoid insulating barrier to peel off or produce particle.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of method that forms metal interconnecting layer, this method comprises:
At the silicon chip surface depositing insulating layer;
Utilize photoetching process to form figure to be etched at silicon chip surface;
Remove the photoresist in silicon chip edge zone;
Etching groove under the protection of residue photoresist, and after etching is finished, remove remaining photoresist;
Adopt the electrochemistry depositing process to form the copper electrodeposited coating at trench wall that etches and silicon chip surface;
The silicon chip edge zone is cleaned;
Adopt chemical mechanical milling tech with silicon chip grinding to surface of insulating layer.
Preferably, the photoresist in described removal silicon chip edge zone comprises:
Silicon chip is fixed on the board, and described board carries out high speed rotating under the driving of motor;
The nozzles spray that is positioned at the board top goes out lytic agent, and the angle by the control nozzle makes lytic agent only be sprayed on the fringe region of silicon chip;
By lytic agent the photoresist on the silicon chip edge zone is dissolved.
Preferably, described rotating speed of motor is 800～1200 rev/mins.
Preferably, the flow velocity of described nozzle is 14 ml/min.
Preferably, the process of the photoresist in described removal silicon chip edge zone continues 5～10 seconds.
Preferably, described lytic agent is the OK73 solvent, is mixed by 1-Methoxy-2-propyl acetate and the propylene glycol monomethyl ether ratio according to 7: 3 volume.
Preferably, the described silicon chip edge zone is cleaned comprises: the mixed solvent that utilizes hydrogen peroxide, sulfuric acid and deionized water to form, clean the fringe region of silicon chip; Wherein, hydrogen peroxide accounts for 7% of cleaning solvent cumulative volume, and sulfuric acid accounts for 5.5%.
Preferably, described fringe region is that the silicon chip ragged edge is along extending into 0.5 millimeter～2 millimeters zone to the silicon chip center position.
As seen; adopt technical scheme of the present invention; after photoetching process is finished; at first the photoresist in silicon chip edge zone is removed, and then silicon chip is carried out etching, because the silicon chip edge zone does not have the photoresist protection; so the insulating barrier of fringe region also can be etched away; like this, follow-up when carrying out CMP, the insulating barrier that causes with regard to the differences such as stress that can not occur owing to zones of different peels off or produces problems such as particle.
Description of drawings
Fig. 1 is the flow chart of the manufacture method of existing metal interconnecting layer.
Fig. 2 is for having the silicon chip schematic diagram after photoetching is finished now.
Fig. 3 is for having the silicon chip schematic diagram after finishing etching and removing photoresist now.
Fig. 4 is the silicon chip schematic diagram behind the existing formation copper electrodeposited coating.
Fig. 5 is for having the silicon chip schematic diagram after grinding now.
Fig. 6 is the flow chart of the inventive method embodiment.
Fig. 7 is the silicon chip schematic diagram behind the photoresist of removing in the embodiment of the invention on the silicon chip edge zone.
Fig. 8 is for etching in the embodiment of the invention and the silicon chip schematic diagram after removing photoresist.
Fig. 9 is the silicon chip schematic diagram behind the formation copper electrodeposited coating in the embodiment of the invention.
Figure 10 is the silicon chip schematic diagram after grinding in the present embodiment.
Embodiment
At problems of the prior art; the present invention proposes a kind of manufacture method of metal interconnecting layer; after photoetching process is finished; at first the photoresist in silicon chip edge zone is removed, and then silicon chip is carried out etching, because the silicon chip edge zone does not have the photoresist protection; so the insulating barrier of fringe region also can be etched away; like this, follow-up when carrying out CMP, the insulating barrier that causes with regard to the differences such as stress that can not occur owing to zones of different peels off or produces problems such as particle.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 6 is the flow chart of the inventive method embodiment.As shown in Figure 6, may further comprise the steps:
Step 61: at the silicon chip surface depositing insulating layer.
Usually adopt the CVD depositional mode.
Step 62: utilize photoetching process to form figure to be etched at silicon chip surface.
The specific implementation of step 61 and step 62 all with prior art in identical, repeat no more.
Step 63: the photoresist of removing the silicon chip edge zone.
Mention in the example shown in Figure 1, in actual applications, can utilize CO
2Remove photoresist, be about on the electrostatic chuck of silicon slice placed in reaction chamber, and in reaction chamber, import CO
2, by the CO of electrode with input
2Ionization is plasma, and afterwards, oxonium ion that ionization goes out and the organic component generation chemical reaction in the photoresist generate CO
2Etc. air scavenge, to reach the purpose of removing photoresist.But this mode is normally removed at whole silicon wafer, can not be used for only removing the photoresist of the fringe region of silicon chip usually.
So, in the present embodiment, adopt special lytic agent to remove the photoresist in silicon chip edge zone, specific implementation comprises: silicon chip is fixed on the board, and this board can carry out high speed rotating under the driving of motor, usually, its rotating speed is 800～1200 rev/mins, and the nozzles spray that is positioned at the board top goes out lytic agent, by the angle of control nozzle, can make lytic agent only be sprayed on the fringe region of silicon chip, the photoresist on the silicon chip edge zone be dissolved by lytic agent.The lasting duration of said process is about 5～10s.In addition, the flow velocity of the lytic agent that sprays in the nozzle can be 14 ml/min, and like this, the total amount of the lytic agent that whole removal process is used will be about 1.5 milliliters.
Used lytic agent can be the OK73 solvent of using always that is used to remove photoresist, and its Main Ingredients and Appearance is 1-Methoxy-2-propyl acetate (PGMEA) and propylene glycol monomethyl ether (PGME), and the ratio of both volumes is 7: 3.
Fig. 7 is the silicon chip schematic diagram behind the photoresist of removing in the embodiment of the invention on the silicon chip edge zone.
Step 64: etching groove under the protection of residue photoresist, and after etching is finished, remove remaining photoresist.
Because the photoresist on the fringe region of silicon chip is removed in step 63, so whole fringe region all will be etched away.
After etching is finished, remove the remaining photoresist of silicon chip surface.Concrete removing method can be to utilize CO
2The mode of removing also can be a mode of utilizing lytic agent to remove.
Fig. 8 is for etching in the embodiment of the invention and the silicon chip schematic diagram after removing photoresist.
Step 65: adopt ECP technology to form the copper electrodeposited coating at trench wall that etches and silicon chip surface.
In this step, utilize mechanical arm that silicon chip is moved to the top of electroplating bath, the top of electroplating bath is provided with a plating ring that is used for fixing silicon chip, and promptly the fringe region of silicon chip is clamped by electroplating ring, and is connected to negative electrode by electroplating ring; Afterwards, by mechanical arm silicon chip is immersed in the electroplate liquid that includes copper ion in the electroplating bath, is generally copper sulphate, electroplate liquid connects anode; Between negative electrode and anode, switch on, under electric field action, form the copper electrodeposited coating.
Fig. 9 is the silicon chip schematic diagram behind the formation copper electrodeposited coating in the embodiment of the invention.
Step 66: the silicon chip edge zone is cleaned.
The copper electrodeposited coating forms and finishes, and after silicon chip is taken out from electroplate liquid, is clamped because the fringe region of silicon chip electroplates ring originally, so do not plate the copper electrodeposited coating substantially, still, burr may occur, for preventing that these burr from impacting subsequent technique, need clean it.
In this step, the mixed solvent that utilizes hydrogen peroxide, sulfuric acid and deionized water to form cleans the fringe region of silicon chip; Wherein, hydrogen peroxide accounts for 7% of cleaning solvent cumulative volume, and sulfuric acid accounts for 5.5%, and other is a deionized water.
Usually, be the fringe region of silicon chip with the silicon chip ragged edge along the zone definitions that extends into 0.5 millimeter～2 millimeters to the silicon chip center position.
Silicon chip is fixed on the board, this board can carry out high speed rotating under the driving of motor, usually, its rotating speed is 800～1200 rev/mins, the nozzles spray that is positioned at the board top goes out cleaning solvent, angle by the control nozzle can make cleaning solvent only be sprayed onto on the fringe region of silicon chip, thereby utilize the strong oxidizing property of hydrogen peroxide and sulfuric acid to come the burr that may occur are cleaned.Clean the sustainable 5～10s of duration.
Step 67: adopt CMP technology with silicon chip grinding to surface of insulating layer.
Figure 10 is the silicon chip schematic diagram after grinding in the present embodiment.
So far, promptly finished the manufacturing process of the described metal interconnecting layer of present embodiment.
In a word; adopt technical scheme of the present invention; after photoetching process is finished; at first the photoresist in silicon chip edge zone is removed, and then silicon chip is carried out etching, because the silicon chip edge zone does not have the photoresist protection; so the insulating barrier of fringe region also can be etched away; like this, follow-up when carrying out CMP, the insulating barrier that causes with regard to the differences such as stress that can not occur owing to zones of different peels off or produces problems such as particle.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. method that forms metal interconnecting layer, this method comprises:
At the silicon chip surface depositing insulating layer;
Utilize photoetching process to form figure to be etched at silicon chip surface;
Remove the photoresist in silicon chip edge zone;
Etching groove under the protection of residue photoresist, and after etching is finished, remove remaining photoresist;
Adopt the electrochemistry depositing process to form the copper electrodeposited coating at trench wall that etches and silicon chip surface;
The silicon chip edge zone is cleaned;
Adopt chemical mechanical milling tech with silicon chip grinding to surface of insulating layer.
2. method according to claim 1 is characterized in that, the photoresist in described removal silicon chip edge zone comprises:
Silicon chip is fixed on the board, and described board carries out high speed rotating under the driving of motor;
The nozzles spray that is positioned at the board top goes out lytic agent, and the angle by the control nozzle makes lytic agent only be sprayed on the fringe region of silicon chip;
By lytic agent the photoresist on the silicon chip edge zone is dissolved.
3. method according to claim 2 is characterized in that, described rotating speed of motor is 800～1200 rev/mins.
4. according to claim 2 or 3 described methods, it is characterized in that the flow velocity of described nozzle is 14 ml/min.
5. according to claim 2 or 3 described methods, it is characterized in that the process of the photoresist in described removal silicon chip edge zone continues 5～10 seconds.
6. according to claim 2 or 3 described methods, it is characterized in that described lytic agent is the OK73 solvent, mix by 1-Methoxy-2-propyl acetate and propylene glycol monomethyl ether ratio according to 7: 3 volume.
7. according to claim 1,2 or 3 described methods, it is characterized in that the described silicon chip edge zone is cleaned comprises: the mixed solvent that utilizes hydrogen peroxide, sulfuric acid and deionized water to form, clean the fringe region of silicon chip; Wherein, hydrogen peroxide accounts for 7% of cleaning solvent cumulative volume, and sulfuric acid accounts for 5.5%.
8. according to claim 1,2 or 3 described methods, it is characterized in that described fringe region is that the silicon chip ragged edge is along extending into 0.5 millimeter～2 millimeters zone to the silicon chip center position.
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|---|---|---|---|
| CN 200910196548 CN102034737B (en) | 2009-09-27 | 2009-09-27 | Making method of metal interconnection layer |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104513626A (en) * | 2014-12-22 | 2015-04-15 | 深圳市力合材料有限公司 | Silicon chemical-mechanical polishing solution |
| CN104701241A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor component edge etching method |
| CN105087184A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Cleaning reagent, method for cleaning etching residues in semiconductor device and making method for metal interconnection layer |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169197C (en) * | 2001-03-28 | 2004-09-29 | 华邦电子股份有限公司 | Etching machine for chip boundary and its etching method |
| KR100559041B1 (en) * | 2002-07-11 | 2006-03-10 | 매그나칩 반도체 유한회사 | Method of forming a copper wiring in a semiconductor device |
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2009
- 2009-09-27 CN CN 200910196548 patent/CN102034737B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701241A (en) * | 2013-12-05 | 2015-06-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor component edge etching method |
| CN104701241B (en) * | 2013-12-05 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | The corner engraving method of semiconductor devices |
| CN105087184A (en) * | 2014-05-22 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Cleaning reagent, method for cleaning etching residues in semiconductor device and making method for metal interconnection layer |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
| CN105448803B (en) * | 2014-06-30 | 2018-06-05 | 上海格易电子有限公司 | A kind of method for improving the effective channel width of flash cell |
| CN104513626A (en) * | 2014-12-22 | 2015-04-15 | 深圳市力合材料有限公司 | Silicon chemical-mechanical polishing solution |
| CN104513626B (en) * | 2014-12-22 | 2017-01-11 | 深圳市力合材料有限公司 | Silicon chemical-mechanical polishing solution |
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