CN102034526B - Method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) - Google Patents

Method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) Download PDF

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CN102034526B
CN102034526B CN 201010598447 CN201010598447A CN102034526B CN 102034526 B CN102034526 B CN 102034526B CN 201010598447 CN201010598447 CN 201010598447 CN 201010598447 A CN201010598447 A CN 201010598447A CN 102034526 B CN102034526 B CN 102034526B
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refresh
memory
sdram
fpga
particles
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CN 201010598447
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Chinese (zh)
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CN102034526A (en )
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李静
李楠宁
白宗元
张磊
张英文
纪奎
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曙光信息产业股份有限公司
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Abstract

本发明提供了一种用FPGA实现的SDRAM内存颗粒刷新的新方法,内存控制器中有N个片选CS需要刷新;在规定刷新时间到来时,发出刷新命令,选通第一个片选CS0;在CS0刷新周期未完,CS0启动M个周期后,启动刷新命令,选通第二个片选CS1;以此类推刷新全部内存。 The present invention provides a new method of using SDRAM memory refresh particles FPGA implementation, there are N memory controller chip select CS needs to be refreshed; upon arrival at a predetermined refresh time, refresh command is issued, the first chip select strobe CS0 ; the refresh cycle unfinished CS0, CS0 started after M cycles, the refresh start command, the second chip select strobe CSl; so all memory refresh. 通过采用该方案,可有效降低SDRAM颗粒的刷新电流及刷新功耗。 By using this scheme, and can effectively reduce the refresh current power SDRAM refresh particles. 在大容量、多内存系统中,对功耗的降低尤为显著,可有效降低系统整机功耗。 In the large-capacity, multi-memory system, to minimize power consumption is particularly significant, the system can effectively reduce the overall power consumption.

Description

—种用FPGA实现的SDRAM刷新的方法 - Method breeding SDRAM FPGA implementation refresh

技术领域 FIELD

[0001] 本发明涉及内存控制器设计,具体涉及一种用FPGA实现的、降低SDRAM刷新功耗的方法。 [0001] The present invention relates to a memory controller design, particularly to a method implemented in an FPGA, SDRAM refresh to reduce power consumption.

背景技术 Background technique

[0002] 半导体存储器件有动态随机存取存储器(DRAM)和静态随机存取存储器(SRAM)两种。 [0002] The semiconductor memory device has a dynamic random access memory (DRAM) and static random access memory (SRAM) two kinds. SRAM内部采用双稳态电路的形式存储数据,不需要刷新电路即能保存内部存储的数据。 Internal SRAM for storing data in the form of a bistable circuit, i.e. the circuit does not need to refresh the data stored therein can be saved. DRAM的存储单元是由晶体管和电容构成,数据被存储在电容中,由于电容会漏电,随着时间推移,会导致存储在电容中的数据被破坏,因此需要对存储在电容中的数据周期性地重复充电。 DRAM memory cell is composed of a transistor and a capacitor, data is stored in the capacitor, since the capacitance will leak, over time, cause the storage of data stored in the capacitance is destroyed, it is necessary for the data stored in the capacitance of the periodic repeated charging. 可以与CPU时钟同步工作的DRAM称为SDRAM。 DRAM CPU clock can be synchronized with the work called SDRAM.

[0003] SDRAM 的刷新分为自动刷新(auto refresh, AR)和自刷新(self refresh, SR)两种模式。 [0003] SDRAM refresh into automatic refresh (auto refresh, AR) and a self-refresh (self refresh, SR) mode. 无论是何种刷新方式,都不需要外部提供行地址信息,行地址选择由内部操作提供。 No matter what kind of refresh mode, you do not need to provide external row address information provided by the internal row address select operation. SR主要用于休眠模式低功耗状态下的数据保存。 SR mainly used for data storage in sleep mode, low power consumption state. 本发明内容涉及AR操作。 The present invention relates to the operation AR. 按照DDR2JTAG规范,大约需要每隔64ms,要求刷新完所有的8192行,这样每行刷新的时间间隔大约为7.8us。 DDR2JTAG according to specifications, approximately every 64ms, requires complete flush all lines 8192, so that each line refresh time interval is about 7.8us. 刷新时停止其他操作,刷新操作具有最高优先级,刷新时SDRAM响应外部输入的一个命令信号,然后进入自动刷新模式,容量大小不同的SDRAM颗粒刷新命令维持的时间不同,比如256Mb的SDRAM时间为75ns, 512Mb的为105ns, IGb的为127.5ns, 2Gb的为197.5ns。 Stop refresh another operation, the refresh operation having the highest priority, SDRAM in response to a command signal externally input refresh, and then enters the auto-refresh mode, the different sizes SDRAM particles refresh command is maintained at different times, such as a 256Mb SDRAM time 75ns , 512Mb of 105ns, IGb is 127.5ns, 2Gb of 197.5ns. SDRAM的刷新电流较大,由此带来较大的功耗。 SDRAM refresh current is large, and the resulting large power consumption. 在大容量、多内存系统中,内存刷新带来的功耗不容小视,为此需要尽量减小在大容量、多内存系统中由于SDRAM刷新操作带来的功耗,提高系统运行效率,较少系统设计成本。 In the large-capacity, multi-memory system, memory refresh bring power can not be overlooked, which requires a large capacity to minimize power consumption, since the multiple system memory SDRAM refresh operation is brought, improve the system efficiency, less system design costs.

[0004] 在00102790.5号专利“能选择执行存储体的自刷新操作的动态随机存取存储器”中提到了一种降低动态随机存取存储器功耗的方法,该方法在刷新时只针对那些存储数据的存储体进行刷新,而不像传统的刷新是针对所有存储体,这样通过有针对性的选择刷新来降低系统功耗,但是该方法在应用到大容量、多内存系统中时需要增加电路设计,额外又增加了系统的电路功耗,而且该专利只是针对自刷新操作进行的功耗降低。 [0004] The mentioned method of reducing the power consumption of the dynamic random access memory in Patent No. 00102790.5 "bank can choose to perform a self-refresh operation of a dynamic random access memory", the method only for those data stored in the refresh the bank refresh, and the refresh is unlike conventional for all banks, and a refresh selection through targeted to reduce system power consumption, but the method is applied to a large capacity needs to be increased much memory circuit design system extra added power dissipation of the system, and that the patent is only for self-refresh operation of the power reduction.

[0005] 在200510071912.9号专利“半导体存储装置中基于存储体的自刷新控制装置及其方法”中提到的降低存储体刷新功耗的方法,该方法也是通过在自刷新操作时选择性的进行刷新,可以有效降低自刷新电流及功耗,该方法未提及如何降低由于自动刷新操作带来的巨大功耗,而且在大容量、多内存领域,也需要额外增加电路来维持,由此也带来了额外的功耗开销。 [0005] In the method of Patent No. 200510071912.9 bank refresh to reduce power consumption in reference to "a semiconductor memory device in self-refresh bank control apparatus and method based on", the process is carried out by selective operation in the self refresh refresh, self refresh can effectively reduce current and power consumption, this method does not mention how to reduce the auto-refresh operation because of the enormous power consumption, and large-capacity, multi-field memory, also requires additional circuitry to maintain, thereby also It brings additional power overhead.

发明内容 SUMMARY

[0006] 为解决上述问题,本发明用FPGA实现SDRAM的刷新,在刷新时间到来时,由FPGA向SDRAM发送刷新指令,在SDRAM自动刷新AR期间采用错峰叠加的方法降低SDRAM颗粒刷新带来的功耗,进而降低大容量、多内存系统的功耗。 [0006] To solve the above problems, the inventors realized by FPGA SDRAM refresh present, the refresh time arrives, send a refresh command to the FPGA SDRAM, a method using automatic refresh staggering superposed AR decreased during SDRAM SDRAM refresh particles brought power, thereby reducing power consumption of a large-capacity, multi-memory system.

[0007] 一种用FPGA实现的SDRAM内存颗粒刷新的方法,步骤如下:[0008] A、内存控制器中有片选CS需要刷新; [0007] A method implemented in FPGA SDRAM memory refresh particles, as follows: [0008] A, the memory controller chip select CS needs to be refreshed;

[0009] B、在规定刷新时间到来时,发出刷新命令,选通第一个片选CSO进行刷新; [0009] B, when the predetermined refresh time comes, refresh command is issued, the first chip select strobe CSO refreshed;

[0010] C、在CSO刷新周期未完时,CSO接收刷新指令M个周期后,FPGA发送再次刷新命令,选通第二个片选CSl ; After the [0010] C, when the refresh cycle unfinished CSO, CSO M cycles refresh command received, FPGA again send a refresh command, the second strobe CSl the chip select;

[0011] D、以此类推刷新全部内存。 [0011] D, and so on all the refresh memory.

[0012] 本发明的一种优选技术方案在于:M的取值可变。 [0012] In a preferred aspect of the present invention, wherein: M is a variable value.

[0013] 本发明的另一优选技术方案在于:在内存型号不一样的情况下,利用FPGA可编程特性,CSn的刷新周期可随时进行调整。 [0013] Another preferred aspect of the present invention is: at the memory model is not the same case, the FPGA programmable features, CSn refresh cycle can be adjusted at any time.

[0014] 通过采用该方案,可有效降低SDRAM颗粒的刷新电流及刷新功耗。 [0014] By using this scheme, and can effectively reduce the refresh current power SDRAM refresh particles. 在大容量、多内存系统(N >4)中,对功耗的降低尤为显著,可有效降低系统整机功耗。 In the large-capacity, multi-memory system (N> 4), reducing power consumption is particularly significant, the system can effectively reduce the overall power consumption.

附图说明 BRIEF DESCRIPTION

[0015] 图1是本发明刷新示意图具体实施方式 [0015] FIG. 1 is a schematic diagram of the present invention, the refresh DETAILED DESCRIPTION

[0016] 如附图1所示。 [0016] As shown in Figure 1. 若在当前内存控制器中有三个片选CS需要刷新,在规定的刷新时间到来时,如图中第I个时钟周期所示,FPGA发出刷新命令,选通第一个片选CSO,在CSO刷新周期未完,CSO启动刷新5个周期后,发出第二个刷新命令,选通第二个片选CS1,同样在CSl选通刷新5个周期后,发出第三个刷新命令,同时选通第三个片选CS2,由于内存型号相同,在CS2的刷新周期满足的前提下,CSO和CSl的刷新周期也必定满足。 If there are three chip select CS needs to be refreshed, the refresh arrives at a predetermined time, as shown in the I-th clock cycle as shown, FPGA refresh command is issued, the first chip select strobe CSO, CSO in the current memory in the controller refresh cycle unfinished, CSO started after the refresh cycle 5, a second refresh command issued, the second chip select strobe CS1, also in CSl after 5 cycles refresh strobe, the refresh command issued third, while the gate of three chip select CS2, due to the same memory model, under the premise of CS2 refresh cycle to meet, CSO and CSl refresh cycles must be met. 正常情况下,在启动CSO刷新后,若刷新周期为T,必须等待刷新周期T结束后才能启动CSl的刷新,依次类推刷新这三个片选需要的时间为3T,而在该刷新模式下,在启动CSO刷新后到刷新完CS2,总共不要2T的时间(如附图为T+10个周期),刷新时间大大减小,可有效降低刷新电流及刷新带来的功耗。 Under normal circumstances, after starting the CSO refresh if a refresh cycle is T, we must wait to start refresh CSl after the end of the refresh cycle T, and so the three chip select refresh time required for 3T, down in the refresh mode, after completion of the refresh start CSO refresh CS2, not total time 2T (T + 10 as indicated by reference of cycles), the refresh time is greatly reduced, effectively reducing the refresh current and the refresh power consumption caused.

Claims (3)

  1. 1.一种用FPGA实现的SDRAM内存颗粒刷新的方法,其特征在于:步骤如下: A、内存控制器中有片选CS中内存颗粒需要刷新,在规定刷新时间到来时,FPGA发出刷新命令,选通第一个片选CSO ;B、在CSO刷新周期未完,CSO启动M个周期后,启动刷新命令,选通第二个片选CSl ; C、以此类推刷新全部内存。 CLAIMS 1. A method implemented in FPGA SDRAM memory refresh particles, wherein: the steps of: A, the memory controller chip select CS particles need to refresh the memory, when the predetermined refresh time comes, FPGA refresh command is issued, a first chip select gating CSO; B, in the refresh cycle unfinished CSO, CSO M periods start, start the refresh command, the second chip select strobe CSl; C, so refresh the entire memory.
  2. 2.如权利要求1所述一种用FPGA实现的SDRAM内存颗粒刷新的方法,其特征在于:M的取值可变。 A method of using the particles SDRAM memory refresh the FPGA implementation as claimed in claim 1, wherein: M is a variable value.
  3. 3.如权利要求1所述一种用FPGA实现的SDRAM内存颗粒刷新的方法,其特征在于:在内存型号不一样的情况下,利用FPGA可编程特性,CSn中内存颗粒的刷新周期可随时进行调整。 3. A method for use SDRAM memory refresh particles FPGA implementation of claim 1, wherein: the model in memory is not the same case, the FPGA programmable features, the memory refresh period CSn particles may at any time Adjustment.
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