CN102426854A - Method for lowering DDR3 (Double Data Rate) memory refreshing power consumption - Google Patents
Method for lowering DDR3 (Double Data Rate) memory refreshing power consumption Download PDFInfo
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- CN102426854A CN102426854A CN2011104134887A CN201110413488A CN102426854A CN 102426854 A CN102426854 A CN 102426854A CN 2011104134887 A CN2011104134887 A CN 2011104134887A CN 201110413488 A CN201110413488 A CN 201110413488A CN 102426854 A CN102426854 A CN 102426854A
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Abstract
The invention provides a method for lowering DDR3 (Double Data Rate) memory refreshing power consumption, which is used for lowering power consumption brought about by memory particle refreshing with a refreshing staggered-peak overlaying method so as to lower memory operation power consumption. With the method for lowering DDR3 memory refreshing power consumption, which is disclosed by the invention, the refreshing current and the refreshing power consumption of an SDRAM (Synchronous Dynamic Random Access Memory) particle can be effectively lowered. In a large-volume and multi-memory system, the method has an especially obvious effect on lowering power consumption, and the complete machine power consumption of the system can be effectively lowered.
Description
Technical field
The invention belongs to DDR3 Memory Controller Hub design field, be specifically related to a kind of method of the DDR3 of reduction memory refresh power consumption.
Background technology
The SDRAM particle is owing to need periodic refreshing could guarantee that internal storage data do not lose, and at the appointed time, the SDRAM particle must be accomplished corresponding refresh operation.SDRAM particle electric current when refreshing is bigger, and the refresh cycle is longer, and with other operation compared, because the power consumption that refresh operation brings is bigger, prior art generally is according to the JEDEC standard, according to refreshing requirement, accomplishes refresh operation at the appointed time.
Patent No. CN201010598447.5 (new method that a kind of SDRAM that realizes with FPGA refreshes) discloses the new method that a kind of sdram memory particle of realizing with FPGA refreshes, and has N sheet to select CS to refresh in the Memory Controller Hub; When the regulation refresh time arrives, send refresh command, first sheet of gating selects CS0; Not intact in the CS0 refresh cycle, CS0 starts M all after date, starts refresh command, and second sheet of gating selects CS1; Refresh full memory by that analogy.Through adopting this scheme, can effectively reduce refreshing electric current and refreshing power consumption of SDRAM particle.In high capacity, multi-memory system, particularly remarkable to the reduction of power consumption, can effectively reduce system's Overall Power Consumption.
Patent No. CN200610137607.X (preventing the method and apparatus that internal storage data is lost) discloses a kind of method and apparatus that prevents that internal storage data from losing, and belongs to field of processors.In order to solve that internal storage data possibly lost during cpu reset in the prior art, reliability is low and problem such as cost height; The invention provides a kind of method that prevents that internal storage data from losing; Comprise the steps: that when CPU resets the delayed management time also makes internal memory get into the self-refresh state; Finish to postpone and trigger CPU really to reset.The present invention also provides a kind of device that prevents that internal storage data from losing, and comprises Postponement module, self-refresh configuration module and reseting module.The present invention really resets the later CPU of internal memory self-refresh through increasing the reset delay circuit again, can when CPU resets, keep internal storage data not lose, and has not only strengthened the reliability of running software, has also improved the starting efficiency of software.
The invention solves in the prior art and refresh the huge power problems that brings, can effectively reduce the refresh time and the power consumption of DDR3 SDRAM particle, and then reduce the power consumption of internal memory owing to DDR3 SDRAM particle.
Summary of the invention
The present invention overcomes the prior art deficiency, reduces the refresh time and the power consumption of DDR3 SDRAM particle, and then reduces the power consumption of internal memory.
The invention provides a kind of method of the DDR3 of reduction memory refresh power consumption, it adopts the method that refreshing the stack of avoiding the peak hour to reduce the internal memory particle and refresh the power consumption of bringing, and then reduces the power consumption of internal memory operation.
The method of reduction DDR3 memory refresh power consumption provided by the invention; When initialization refreshes, after providing the period 1 of first refresh command, and then provide second refresh command; After the second round that provides second refresh command, and then provide the 3rd refresh command afterwards.
The method of reduction provided by the invention DDR3 memory refresh power consumption, be the refresh cycle T of internal memory particle the 3rd refresh command effective time.
The method of reduction DDR3 memory refresh power consumption provided by the invention, the time span of period 1 and second round is far smaller than T.
The method of reduction DDR3 memory refresh power consumption provided by the invention, the time span of period 1 is identical with the time span of second round.
The method of reduction DDR3 memory refresh power consumption provided by the invention, the time span of period 1 and second round all is 5 clock period.
The method of reduction provided by the invention DDR3 memory refresh power consumption, in save as SDRAM.
With prior art property ratio, beneficial effect of the present invention is: through adopting this scheme, can effectively reduce refreshing electric current and refreshing power consumption of SDRAM particle.In high capacity, multi-memory system, particularly remarkable to the reduction of power consumption, can effectively reduce system's Overall Power Consumption.
Description of drawings
Fig. 1 periodic structure synoptic diagram of the present invention.
Embodiment
The present invention adopts the method reduction SDRAM particle that refreshes the stack of avoiding the peak hour to refresh the power consumption of bringing, and then reduces the power consumption of internal memory operation.Synoptic diagram is shown in accompanying drawing 1.If in current Memory Controller Hub, there are three sheets to select CS to refresh, when the refresh time of regulation arrives, shown in the 1st clock period among the figure; Send refresh command, first sheet of gating selects CS0, and is not intact in the CS0 refresh cycle; CS0 starts and refreshes 5 all after dates, sends second refresh command, and second sheet of gating selects CS1; Refresh 5 all after dates at the CS1 gating equally, send the 3rd refresh command, the 3rd sheet of gating selects CS2 simultaneously; Because the internal memory model is identical, under the prerequisite that satisfies in the refresh cycle of CS2, the refresh cycle of CS0 and CS1 also must satisfy.Under the normal condition, after startup CS0 refreshes, if the refresh cycle is T; Must wait for after refresh cycle T finishes could starting refreshing of CS1, and the like refresh these three sheet choosings needs time be 3T, and under this refresh mode; Refresh the back to having refreshed CS2 at startup CS0; Do not want the time (is T+10 cycle like accompanying drawing) of 2T altogether, refresh time reduces greatly, can effectively reduce and refresh electric current and refresh the power consumption of bringing.
The present invention adopts the method refreshing the stack of avoiding the peak hour to reduce in the prior art because DDR3 SDRAM particle refreshes the huge power problems that brings, and can effectively reduce the refresh time and the power consumption of DDR3 SDRAM particle, and then reduce the power consumption of internal memory.
Above embodiment is only in order to technical scheme of the present invention to be described but not to its restriction; Although the present invention has been carried out detailed explanation with reference to the foregoing description; The those of ordinary skill in said field is to be understood that: still can specific embodiments of the invention make amendment or replacement on an equal basis; And do not break away from any modification of spirit and scope of the invention or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (7)
1. a method that reduces DDR3 memory refresh power consumption is characterized in that adopting the method that refreshes the stack of avoiding the peak hour to reduce the internal memory particle and refreshes the power consumption of bringing, and then reduces the power consumption of internal memory operation.
2. the method for claim 1 is characterized in that, during memory refresh; Providing some all after dates of first refresh command; And then provide second refresh command, providing some all after dates of second refresh command afterwards, and then provide the 3rd refresh command.
3. the method for claim 1-2 is characterized in that, be the refresh cycle T of internal memory particle the 3rd refresh command effective time.
4. the method for claim 1-3 is characterized in that, for the first time refresh time is far smaller than T with refresh time length for the second time.
5. the method for claim 1-4 is characterized in that, refresh command is identical with the time span that the second time, refresh command continued for the first time.
6. the method for claim 1-5 is characterized in that, three refresh commands gap length between any two all is 5 clock period.
7. the method for claim 1-6 is characterized in that, in save as SDRAM.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011104134887A CN102426854A (en) | 2011-12-13 | 2011-12-13 | Method for lowering DDR3 (Double Data Rate) memory refreshing power consumption |
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| CN2011104134887A CN102426854A (en) | 2011-12-13 | 2011-12-13 | Method for lowering DDR3 (Double Data Rate) memory refreshing power consumption |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148248A (en) * | 2022-09-06 | 2022-10-04 | 北京奎芯集成电路设计有限公司 | Deep learning-based DRAM (dynamic random Access memory) refreshing method and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926434A (en) * | 1997-06-26 | 1999-07-20 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device capable of reducing electricity consumption on standby |
| CN1853175A (en) * | 2003-09-29 | 2006-10-25 | 英特尔公司 | Memory buffer device integrating refresh |
| CN102034526A (en) * | 2010-12-17 | 2011-04-27 | 天津曙光计算机产业有限公司 | Novel method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5926434A (en) * | 1997-06-26 | 1999-07-20 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device capable of reducing electricity consumption on standby |
| CN1853175A (en) * | 2003-09-29 | 2006-10-25 | 英特尔公司 | Memory buffer device integrating refresh |
| CN102034526A (en) * | 2010-12-17 | 2011-04-27 | 天津曙光计算机产业有限公司 | Novel method for realizing static and dynamic random access memory (SDRAM) refresh by using field programmable gate array (FPGA) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115148248A (en) * | 2022-09-06 | 2022-10-04 | 北京奎芯集成电路设计有限公司 | Deep learning-based DRAM (dynamic random Access memory) refreshing method and device |
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Application publication date: 20120425 |