CN102027633A - Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance - Google Patents
Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance Download PDFInfo
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- CN102027633A CN102027633A CN2009801177148A CN200980117714A CN102027633A CN 102027633 A CN102027633 A CN 102027633A CN 2009801177148 A CN2009801177148 A CN 2009801177148A CN 200980117714 A CN200980117714 A CN 200980117714A CN 102027633 A CN102027633 A CN 102027633A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P9/00—Delay lines of the waveguide type
- H01P9/006—Meander lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P9/00—Delay lines of the waveguide type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A transmission line structure includes a signal line (50) (e.g. S), a first ground return structure (55) (e.g. G1) that causes a first delay (t1) and a first characteristic impedance (ZoI) in the transmission line structure, and a second ground return structure (75) (e.g. G2) that causes a second delay (t2) and a second characteristic impedance (Zo2) in the transmission line structure. The first delay (t1) is different from the second delay (t2), and the first characteristic impedance (Zo1) is substantially the same as the second characteristic impedance (Zo2).
Description
Technical field
The present invention relates to transmission line, and more specifically, relate to the project organization, structure and the method that are used to provide variable delay transmission line on the sheet with fixed characteristic impedance.
Background technology
Transmission line structure generally has blocked impedance and fixed delay on traditional sheet.Usually, for given transmission line, can't select arbitrarily to postpone and impedance.On the contrary, delay and impedance are subjected to the influence of electric capacity and inductance, and wherein electric capacity and inductance reciprocally change based on the distance between holding wire and the grounded circuit line.Therefore, be possible though change the delay of transmission line, changing the cost that postpones is to increase loss of signal, change characteristic impedance and/or increase the required area (for example area occupied) of transmission-line device.
Yet for a lot of application, the delay that changes transmission line is expected.For example, in signal processing operations, use delay line, to regulate the time of advent of a signal with respect to secondary signal.Can come the manufacturing delay line at digital circuit or analog circuit, and delay can be that fix or variable.Have sine-shaped signal (this is common situation) for postponing in microwave applications, the effect of delay line is to give phase shift; Thus, in this case, delay line can be considered phase shifter.
But in phased array, can use a plurality of phase place line transfers.Generally speaking, phased array is one group of antenna, and wherein the relative phase of the corresponding signal of feed antenna changes as follows: the effective radiation pattern that makes array strengthens and is suppressed in the direction of not expecting in the direction of expectation.Determine effective radiation pattern of array by the relative amplitude between the signal of single antenna radiation and constructive interference and destructive interference effect.Phased array is used to the peak response direction of receiver control electronically, and the higher antenna gain of spatial selectivity or equivalence is provided.Phased array can be used for including but not limited to RADAR and data communication in the multiple different wireless application.Wave beam control realizes like this: at first be offset with the phase place of progressive amount to each received signal, with the successive difference between the compensation arrival phase place.Then make up these signals, wherein for the direction of expectation superposed signal longways mutually, for other directions ground superposed signal that then disappears mutually.
The traditional approach of the phase place of each element is in the control phased array: for each element provides a plurality of transmission lines, each transmission line has known delay.Switch in the signal path of each element is used to select the specific transmission line of this element, thereby gives the element known delay.Yet such system has a plurality of shortcomings.For example, provide a plurality of transmission lines higher for each element in the cost of aspects such as usage space (for example, area occupied), manufacturing.And the switch in the signal path of each element will cause signal attenuation, and this does not expect in this type of is used.
In addition, as mentioned above, traditional system can't not increase loss of signal, not change characteristic impedance and/or not increase the delay that changes transmission line under the situation of the needed area of transmission-line device (for example, area occupied).Use the system's (for example, phased array antenna system) that postpones to have these shortcomings.
Therefore, there are the needs that overcome above-mentioned defective and restriction in this area.
Summary of the invention
In a first aspect of the present invention, a kind of transmission line structure comprises: holding wire; The first grounded circuit structure, it causes first to postpone and first characteristic impedance in transmission line structure; And the second grounded circuit structure, it causes second to postpone and second characteristic impedance in transmission line structure.First delay and second postpones different, and first characteristic impedance is identical in fact with second characteristic impedance.
In execution mode, holding wire, the first grounded circuit structure and the second grounded circuit structure are formed at semiconductor structure.Holding wire can be formed at first wiring layer (wiring level) of semiconductor structure, and the first grounded circuit structure can be formed at second wiring layer of semiconductor structure, and the second grounded circuit structure can be formed at the 3rd layer of semiconductor structure.In addition, first wiring layer can be different with second wiring layer, and the part of the first grounded circuit structure also can be formed at first wiring layer.In other execution mode, holding wire is formed at first wiring layer of semiconductor structure, and the first grounded circuit structure is formed at first wiring layer, and the part of the second grounded circuit structure is formed at first wiring layer and second wiring layer of semiconductor structure.
The each side according to the present invention, switch are operated respectively in order to a ground connection in the first grounded circuit structure and the second grounded circuit structure, and make in the second grounded circuit structure and the first grounded circuit structure another unsettled.In addition, the first grounded circuit structure can comprise the first grounded circuit rail and first capacitance structure, and the second grounded circuit structure can comprise the second grounded circuit rail and second capacitance structure.In addition, the first grounded circuit rail can be than the second grounded circuit rail further from holding wire, and first capacitance structure can be than the more close holding wire of second capacitance structure.It can be the delay of signal in the holding wire that first delay and second postpones.
In a second aspect of the present invention, a kind of semiconductor structure comprises: holding wire; The first grounded circuit rail and first capacitance structure; And second the grounded circuit rail and second capacitance structure.Further from holding wire, first capacitance structure is than the more close holding wire of second capacitance structure, and the ground connection of holding wire can optionally be switched between the first grounded circuit rail and the second grounded circuit rail than the second grounded circuit rail for the first grounded circuit rail.
In a third aspect of the present invention, a kind ofly be used for designing, manufacturing or testing integrated circuits, visibly be included in the project organization of machine readable media, this project organization comprises: holding wire; The first grounded circuit structure, it causes first to postpone and first characteristic impedance in transmission line structure; And the second grounded circuit structure, it causes second to postpone and second characteristic impedance in transmission line structure.First delay and second postpones different, and first characteristic impedance is identical in fact with second characteristic impedance.
In a fourth aspect of the present invention, a kind of hardware description language (HDL) project organization that is coded on the machine-readable data storage media, described HDL project organization comprises element, when this element is processed in computer aided design system, the machine that generates transmission line structure can be carried out expression, and wherein this HDL project organization comprises: holding wire; The first grounded circuit rail and first capacitance structure; And second the grounded circuit rail and second capacitance structure.Further from holding wire, and first capacitance structure is than the more close holding wire of second capacitance structure than the second grounded circuit rail for the first grounded circuit rail.
Description of drawings
Below according to the mode of the non-limiting example of illustrative embodiments of the present invention, a plurality of accompanying drawings of reference marker are described the present invention in embodiment.
Fig. 1-Fig. 5 shows the structure of the each side according to the present invention;
Fig. 6-Fig. 8 shows the intermediate structure and the processing step of the each side according to the present invention;
Fig. 9-Figure 14 shows the structure of the each side according to the present invention;
Figure 15 shows the block diagram of the each side according to the present invention;
Figure 16 is a flow chart of drawing the technology of each side according to the present invention;
Figure 17 is the flow chart of the design process of use in semiconductor design, manufacturing and/or test.
Embodiment
The present invention relates to transmission line, and more specifically, relate to the project organization, structure and the method that are used to provide variable delay transmission line on the sheet with fixed characteristic impedance.In execution mode, transmission line structure has a plurality of selectable grounded circuits path.More specifically, each grounded circuit path is formed with different geometries, and different with the distance of holding wire, makes each grounded circuit path cause transmission line structure to have different delays.In addition, grounding path designs like this, makes that no matter use which grounding path it is constant in fact that the characteristic impedance of transmission line structure all keeps.In this way, by controlling which grounded circuit grounding structure, and which is unsettled, can substantially not change the delay that changes transmission line structure under the situation of characteristic impedance of transmission line structure.Therefore, realization of the present invention provides single microstrip structure, wherein postpone and can change, and the characteristic impedance maintenance is constant relatively.
Fig. 1 shows the schematic diagram of the structure of each side according to the present invention.This structure comprises holding wire 10 and grounded circuit line 15, and it can be formed in the wiring layer of semiconductor device, as hereinafter describing in detail.Semiconductor device for example can comprise transmission line structure.
The characteristic impedance of transmission line structure can be similar to the square root of the ratio of inductance (" L ") and electric capacity (" C "), SQRT (L/C) for example, and this is known, therefore thinks to need not further explanation.In addition, the delay of transmission line structure can be similar to the square root of the product of inductance and electric capacity, for example SQRT (L*C).And the electric capacity of transmission line structure reduces along with the distance between holding wire and the grounded circuit line usually, and the inductance of transmission line structure increases along with the distance between holding wire and the grounded circuit line usually.
Therefore, if grounded circuit line 15 moves near holding wire 10, then the electric capacity of transmission line structure will increase, and the inductance of transmission line structure will reduce.Alternatively, along with grounded circuit line 15 moves away from holding wire 10, the electric capacity of transmission line structure reduces, and the inductance of transmission line structure increases., electric capacity and inductance do not change the characteristic impedance of transmission line structure because with respect to this relativeness of distance between holding wire and the grounded circuit line, can not using traditional structure to change the transmission line structure delay.
Yet the each side according to the present invention, structure shown in Figure 1 comprise electric capacity shielding (shield) 20, and it optionally changes the electric capacity of transmission line structure under the situation of the inductance that does not significantly change transmission line structure.As shown in Figure 1, electric capacity shielding 20 is formed between holding wire 10 and the grounded circuit line 15, for example, is formed in the wiring layer between the corresponding wiring line layer of holding wire 10 and grounded circuit line 15.In execution mode shown in Figure 1, electric capacity shielding 20 comprises the traces 25 that form with snakelike form, has the interval 30 vertical with holding wire 10 between trace 25 parts.In this way, electric capacity shielding 20 can be used to influence the electric capacity of transmission line structure, and induction is invisible in fact.
Still with reference to figure 1, when electric capacity shielding 20 is grounded to grounded circuit line 15, the electric capacity of transmission line structure will be first value, and work as electric capacity shield 20 unsettled (for example, be not grounded to grounded circuit line 15) time, then the electric capacity of transmission line structure will be second value different with first value.In this way, by using the switch (for example, in semi-conductive active area) in the grounded circuit path, electric capacity shielding 20 can be optionally ground connection with unsettled between switching, so that optionally change the capacitance of transmission line structure, keep the inductance of transmission line structure constant relatively simultaneously.
Electric capacity will depend on such as following parameter in the ground connection and the difference between the vacant state of electric capacity shielding 20: for example, and the vertical range between the plane of holding wire 10 and electric capacity shielding 20, the width of trace 25, and the width at interval 30.In execution mode, these parameters can be used any suitable value.For example, table 1 shows ground connection and the electric capacity of vacant state and the comparison of inductance value of two exemplary arrangement.In first arranged, the width of trace 25 approximately was 1 μ m, and 30 width approximately is 1 μ m at interval.In second arranged, the width of trace 25 approximately was 2 μ m, and 30 width approximately is 2 μ m at interval.
Table 1
| Arrange | The state of electric capacity shielding | Electric capacity (millimicro microfarad) | Inductance (Pi Heng) |
| First | Unsettled | 15.009 | 11.627 |
| First | Ground connection | 20.186 | 11.615 |
| Second | Unsettled | 14.797 | 11.678 |
| Second | Ground connection | 19.293 | 11.656 |
Fig. 2 shows another structure of the each side according to the present invention.Similar with Fig. 1, this structure comprises holding wire 10, grounded circuit line 15 and electric capacity shielding 20, and it can be by forming such as the metal in the wiring layer of the semiconductor device of transmission line.The structure of Fig. 2 comprises second electric capacity shielding 35, and it is arranged between shielding 20 of first electric capacity and the grounded circuit line 15.At least one switch (not shown) may be operably coupled to grounded circuit line 15, first electric capacity shielding, 20 and second electric capacity shielding 35, make a shielding can be grounded to the grounded circuit line, and another shielding is unsettled.
Table 2 shows according to the electric capacity of the transmission line structure of Fig. 2 and inductance value.The value of table 2 is used for following transmission line, and wherein the width of the trace 25 of each electric capacity shielding 20,35 approximately is 2 μ m, and the width at the interval between the part of trace 30 approximately is 2 μ m.Easily see according to table 2, can be by optionally with one of electric capacity shielding 20,35 or the two ground connection, with the electric capacity of control transmission line structure, inductance keeps constant relatively simultaneously.
Table 2
Fig. 3 shows another transmission line structure of the each side according to the present invention.This transmission line structure comprises holding wire 50, and it can be the metal wire that for example is formed in the wiring layer of semiconductor device, as hereinafter describing in detail.Transmission line structure also comprises grounded circuit structure 55, and it can comprise metal structure under the layer that for example is formed at holding wire 50, in the wiring layer in the semiconductor device, as hereinafter describing in detail.
In execution mode, grounded circuit structure 55 comprises grounded circuit rail 60, and it is parallel to holding wire 50 in fact.And grounded circuit structure 55 comprises electric capacity carding element 65, and it is formed between the grounded circuit rail 60, and is orthogonal to holding wire 50 in fact.In such transmission line structure, the electric capacity of transmission line structure equals the electric capacity on the plane from holding wire to electric capacity carding element 65, and the inductance of transmission line structure is formed in the current loop path of grounded circuit rail 60 and holding wire 50.
Fig. 4 shows another transmission line structure of the each side according to the present invention.Be similar to the transmission line structure of Fig. 3, the transmission line structure of Fig. 4 comprises holding wire 50 and grounded circuit structure 55 (being called " G1 " in this figure and other accompanying drawings), and it has grounded circuit rail 60 and carding element 65.In addition, the transmission line structure among Fig. 4 comprises the second grounded circuit structure 75 (being called " G2 " in this figure and other accompanying drawings), and it has grounded circuit rail 80 and carding element 85.The second grounded circuit structure 75 for example can comprise the metal structure in the wiring layer under the layer that is formed at the first grounded circuit structure 55, semiconductor device, as hereinafter describing in detail.Can provide at least one switch (not shown) to be used between ground connection and vacant state, switching the first grounded circuit structure 55 and the second grounded circuit structure 75, so that the first grounded circuit structure or the second grounded circuit structure are followed in the grounded circuit path of transmission line structure.
In execution mode, electric capacity comb 65,85 forms perpendicular to holding wire 50, and has that to make it be sightless size and dimension for holding wire 50 in induction in fact.Thus, the grounded circuit rail that the inductance of transmission line structure is formed at holding wire 50 and any one grounded circuit structure that is grounded (for example, 60 or 80) in the current loop path, and hanging structure is to the very little or not influence of inductive impact of transmission line structure.So, for example, in the state of and the second grounded circuit structure, 75 ground connection unsettled in the first grounded circuit structure 55, the inductance of transmission line structure is formed in the current loop path of grounded circuit rail 80 and holding wire 50, the very little or not influence of the influence of the inductance of 55 pairs of transmission line structures of the first grounded circuit structure.
Similarly, the electric capacity of the transmission line structure shown in Fig. 4 is mainly driven by one (for example, 55 or 75) of ground connection in the grounded circuit structure.That is to say that in the state of and the second grounded circuit structure, 75 ground connection unsettled in the first grounded circuit structure 55, the electric capacity of transmission line structure equals the electric capacity on the plane from holding wire to comb 85 upper surfaces in fact.Yet different with inductance, the electric capacity of unsettled grounded circuit structure influence transmission line structure is although the capacity effect of hanging structure is compared less with the capacity effect of ground structure.
In execution mode, the first grounded circuit structure 55 and the second grounded circuit structure 75 form have geometry and with the distance of holding wire 50, thus, depend on that in two grounded circuit structures which is grounded, transmission line structure will have different delay (for example, SQRT (L*C)).Yet, the geometry and the relative position of the first grounded circuit structure 55 and the second grounded circuit structure 75 also design like this, make that regardless of which ground connection in two grounded circuit structures (for example, SQRT (L/C)) is constant in fact in the characteristic impedance of transmission line structure.In this way, by controlling which grounded circuit structure (for example, 55 or 75) ground connection and which is unsettled, can substantially not change the delay that changes transmission line structure under the situation of characteristic impedance of transmission line structure.Therefore, realization of the present invention provides a kind of single microstrip structure, wherein postpones to change and characteristic impedance keeps constant relatively.
For example,, in embodiments of the present invention, regulate the size of grounded circuit rail 60 and at interval still with reference to exemplary configurations shown in Figure 4, make its than grounded circuit rail 80 further from holding wire 50.This causes the first grounded circuit structure 55, and (for example, the inductance that G1) provides is higher than the second grounded circuit structure 75 (for example, G2).In addition, regulate the size and the interval of comb 65, make it than comb 85 more close holding wires 50, the electric capacity that the grounded circuit structure 55 of winning is provided is higher than the second grounded circuit structure 75.By suitably select feature () size and position for example, 50,60,65,80,85, can realize following relation:
t1＝SQRT(L1*C1)＞t2＝SQRT(L2*C2)
Wherein:
Transmission line structure when t1 ≡ G1 ground connection and G2 are unsettled postpones;
Transmission line structure when t2 ≡ G2 ground connection and G1 are unsettled postpones;
Transmission line structure characteristic impedance when Zo1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure characteristic impedance when Zo2 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure inductance when L1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure electric capacity when C1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure inductance when L2 ≡ G2 ground connection and G1 are unsettled;
Transmission line structure electric capacity when C2 ≡ G2 ground connection and G1 are unsettled.
Fig. 5 shows another structure of the each side according to the present invention.The similar that Fig. 5 painted is in structure shown in Figure 4, and it comprises holding wire 50, has grounded circuit rail 60 and comb 65 the first grounded circuit structure 55 and has grounded circuit rail 80 and comb 85 the second grounded circuit structure 75 in the figure.
In exemplary configurations shown in Figure 5, what holding wire 50 was formed at the analog semiconductor structure goes up wiring layer (for example, the N layer) most, and has the width of about 10 μ m in " x " direction, and has the length of about 50 μ m in " y " direction.In execution mode, the first grounded circuit structure 55 is formed in the N-1 wiring layer, and has the length identical with holding wire 50 in " y " direction.Each has the length of about 100 μ m in " x " direction comb 65, and grounded circuit rail 60 each have the width of about 8 μ m in " x " direction.And the second grounded circuit structure 75 is formed in the N-4 wiring layer, and has the length identical with holding wire 50 in " y " direction.Each has the length of about 50 μ m in " x " direction comb 85, and grounded circuit rail 80 each have the width of about 12 μ m in " x " direction.
Table 3 shows the value of transmission line structure electric capacity, transmission line structure inductance, transmission line structure characteristic impedance and the transmission line structure delay of exemplary configurations shown in Figure 5.
Table 3
As shown in table 3, realized that between two states about 16.1% transmission line structure postpones to change, and the characteristic impedance of transmission line structure has only changed about 5.5% between two identical states.Though described specific dimensions, size and geometry, the invention is not restricted to these specific examples.But, by using different semiconductor structures, can obtain about 30% to 40% delay difference, still keep nearly about 5% characteristic impedance difference simultaneously.More specifically, can in realization of the present invention, use the structure (for example, 50,55,75) of any desired size and shape.For example, the structure that can use different sizes and shape within the scope of the invention (for example, 50,55,75), have the different transmission line structures that postpone still to have identical or identical in fact characteristic impedance to provide at different grounded circuits path (for example, G1, G2).
Fig. 6-Fig. 8 shows intermediate structure and the respective handling step that is used to form the each side according to the present invention.Particularly, Fig. 6 shows the sectional view of exemplary semiconductor structure, and it comprises substrate 100 and wiring layer 105 formed thereon.Substrate 100 can use traditional treatment technology to form, and can comprise the silicon substrate that for example has the semiconductor device (for example, grid, source/drain regions) that is formed at wherein.Wiring layer 105 can use traditional handicraft to form, and can be made up of any suitable material, includes but not limited to high k value dielectric, low k value dielectric, ultralow k value dielectric etc.
Still with reference to figure 6, grounded circuit structure 110 is formed in the wiring layer 105.Grounded circuit structure 75 can be made up of any suitable conductive material, includes but not limited to: copper, aluminium, alloy etc., and can use traditional handicraft to form.Grounded circuit structure 110 can perhaps can have different shapes being similar in shape above with reference to figure 4 and the described grounded circuit structure 75 of Fig. 5.For example, grounded circuit structure 110 can comprise that grounded circuit rail part 115 (for example, being similar to grounded circuit rail 80) and comb section divide 120 (for example, being similar to comb 85).
Fig. 7 shows the structure of Fig. 6, has formed additional wiring layer 130,135 and 140 thereon.Be formed with grounded circuit structure 145 in the wiring layer 140, it can use material similar to grounded circuit structure 110 and technology to form.Grounded circuit structure 145 can perhaps can have different shapes being similar in shape above with reference to figure 4 and the described grounded circuit structure 55 of Fig. 5.For example, grounded circuit structure 145 can comprise that grounded circuit rail part 150 (for example, being similar to grounded circuit rail 60) and comb section divide 155 (for example, being similar to comb 65).
Fig. 8 shows the structure of Fig. 7, for example uses traditional material and technology to form other wiring layer 160 thereon.In addition, holding wire 165 is formed in the wiring layer 160.Holding wire 165 can be similar to above with reference to figure 4 and the described holding wire 50 of Fig. 5, perhaps can have different shapes.Holding wire 165 can be made by any suitable electric conducting material, includes but not limited to: copper, aluminium, alloy etc., and can use traditional handicraft to form.
The feature of Fig. 6-Fig. 8 (for example, 100,105,110,130,135,140,145,160,165) can use conventional art (such as standard rear end operation (BEOL) technology) to form.For example, these features can use manufacturing process to form, manufacturing process includes but not limited to: photo etched mask and exposure, etching are (for example, reactive ion etchings (RIE) etc.), metallization (for example, chemical vapor deposition (CVD) etc.) and planarization and polishing (for example, chemico-mechanical polishing (CMP) etc.).In addition, the supplementary features shown in Fig. 6-Fig. 8 can be used with realization of the present invention.For example, barrier material can be used as liner, cap etc.In addition, can between any wiring layer, insert via layer.
In addition, wiring layer can have the thickness that is fit to arbitrarily, and thickness can be relative to each other different.For example, wiring layer 105,130,135 can have the thickness of about 0.5 μ m to 0.6 μ m, and wiring layer 140 can be that about 3 μ m are thick, and wiring layer 160 can be that about 4 μ m are thick.Yet, the invention is not restricted to these values, but can utilize the thickness that is fit to arbitrarily.In addition, the wiring layer number shown in the invention is not restricted to.But each side of the present invention can be used together with the semiconductor device with arbitrary number wiring layer (for example, analogue device, digital device etc.).
In addition, grounded circuit structure 110,145 and holding wire 165 can be any suitable size and dimensions.And grounded circuit structure 110,145 (for example, G1, G2) is not limited to single corresponding wiring line layer, and (via layer for example, if present), hereinafter with reference Fig. 9-Figure 12 describes in detail but can stride a plurality of wiring layers.In addition, the invention is not restricted to two grounded circuit structures 110,145 shown in Figure 8.But, can use the grounded circuit structure 110,145 of arbitrary number so that provide the difference of any desirable number to postpone as transmission line structure.
In execution mode, can in the device area of substrate 100, provide at least one switch 170.Switch 170 can be operated optionally arbitrary grounded circuit structure (for example, 110 or 145) is connected to ground, makes the grounded circuit structure (for example, 110 or 145) of ground connection become the grounded circuit path of holding wire 165.Switch 170 can comprise any suitable switching device, such as PIN diode, FET etc.In execution mode, switch 170 is arranged in the grounded circuit path of transmission line structure rather than in the signal path, to avoid the signal attenuation in the signal path.
Said method is used to the manufacturing of integrated circuit (IC) chip.The integrated circuit (IC) chip that obtains can be distributed as nude film with undressed wafer form (that is, as the single wafer with a plurality of unpackaged chips) by the producer, perhaps distributes with packing forms.In the later case, chip is installed in the one chip encapsulation (such as the plastic carrier that has attached to the lead-in wire on motherboard or other higher level carriers), perhaps is installed in the multicore sheet encapsulation (such as having or the ceramic monolith of the two in surface interconnection or the buried interconnects).In any situation, chip is integrated with other chips, discrete circuit element and/or other signal processors then, with as the intermediate products of (a) such as motherboard or (b) part of any in the final products.Final products can be any products that comprises integrated circuit (IC) chip.
Fig. 9 and Figure 10 show the alternative transmission line structure of the each side according to the present invention.Particularly, Fig. 9 show comprise holding wire 200, the first grounded circuit structure 205 (for example, G1) and the second grounded circuit structure 225 (for example, transmission line structure G2), all these structures form according to above-described mode.The first grounded circuit structure 205 comprises single grounded circuit rail 210, and it can be similar to grounded circuit rail for example 60,80 etc. in material and manufacturer.The first grounded circuit structure 205 also comprises electric capacity comb 215, and it extends from grounded circuit rail 210, extends upward by a plurality of wiring layer (not shown), and ends at holding wire 200 and be formed at capacity cell 220 in the identical wiring layer.
Still comprise single grounded circuit rail 230 with reference to figure 9, the second grounded circuit structures 225, it can be similar to grounded circuit rail 210.The second grounded circuit structure 225 also comprises electric capacity comb 235, and it extends from grounded circuit rail 230, extends upward by a plurality of wiring layer (not shown), and ends at holding wire 200 and be formed at capacity cell 240 in the identical wiring layer.At least one switch (not shown) can be provided, and optionally placing ground state with one in corresponding grounded circuit structure 205 and 225, and another is unsettled.
Figure 10 shows the cross-sectional view of Fig. 9 structure.The electric capacity contribution of the first grounded circuit structure 205 is labeled as " C1 " mainly from element 220 in Figure 10.The electric capacity contribution of the second grounded circuit structure 225 is labeled as " C2 " mainly from element 240 in Figure 10.The main inductance contributor of the first grounded circuit structure 205 is grounded circuit rails 210, is labeled as " L1 " in Figure 10.The main inductance contributor of the second grounded circuit structure 225 is grounded circuit rails 230, is labeled as " L2 " in Figure 10.
Figure 11 and Figure 12 show the alternative transmission line structure of the each side according to the present invention.Particularly, Figure 11 show comprise holding wire 300, the first grounded circuit structure 305 (for example, G1) and the second grounded circuit structure 325 (for example, transmission line structure G2), all these structures can form according to above-described mode.The first grounded circuit structure 305 comprises single grounded circuit rail 310, and it can be similar to grounded circuit rail 205 (for example among Fig. 9).The first grounded circuit structure 305 also comprises comb 315, and it extends from grounded circuit rail 310, extends upward by a plurality of wiring layer (not shown), and ends at holding wire 300 and be formed at capacity cell 320 in the identical wiring layer.
Still with reference to Figure 11, the second grounded circuit structure 325 comprises two grounded circuit rails 330, and it can be similar to grounded circuit rail 310.Grounded circuit rail 330 is formed in the identical wiring layer with holding wire 300, constitutes coplanar transmission.The second grounded circuit structure 325 does not comprise the electric capacity comb.At least one switch (not shown) can be provided, place ground state with of being used for optionally corresponding grounded circuit structure 305 and 325, and another be unsettled.
Figure 12 shows the sectional view of the structure of Figure 11.The electric capacity contribution of the first grounded circuit structure 305 is labeled as " C1 " mainly from element 320 in Figure 12.The electric capacity contribution of the second base loop structure 325 is labeled as " C2 " mainly from grounded circuit rail 330 in Figure 12.The main inductance contributor of the first grounded circuit structure 305 is grounded circuit rails 310, is labeled as " L1 " in Figure 10.The main inductance contributor of the second grounded circuit structure 325 is grounded circuit rails 330, is labeled as " L2 " in Figure 10.
Figure 13 and Figure 14 show the alternative transmission line structure of the each side according to the present invention.Particularly, Figure 13 shows the transmission line structure that comprises holding wire 400, the first grounded circuit structure 405 (for example G1) and the second grounded circuit structure 425 (for example G2), and all these structures can form according to above-described mode.The first grounded circuit structure 405 comprises two parallel grounded circuit rails 410, and it can be formed in the identical wiring layer with holding wire 400.The first grounded circuit structure 405 also comprises comb 415, extends between the grounded circuit rail 410 in its wiring layer under holding wire 400.
Still with reference to Figure 13, the second grounded circuit structure 425 comprises two parallel grounded circuit rails 430, and it is formed in the identical wiring layer with holding wire 400.The second grounded circuit structure 425 also comprises comb 435, extends between the grounded circuit rail 430 in its wiring layer under holding wire 400.At least one switch (not shown) can be provided, place ground state with of being used for optionally corresponding grounded circuit structure 405 and 425, and another be unsettled.
Figure 14 shows the cross-sectional view of the structure of Figure 13.The electric capacity contribution of the first grounded circuit structure 405 is labeled as " C1 " mainly from comb 415 in Figure 14.The electric capacity contribution of the second grounded circuit structure 425 is labeled as " C2 " mainly from comb 435 in Figure 14.The main inductance contributor of the first grounded circuit structure 405 is grounded circuit rails 410, is labeled as " L1 " in Figure 14.The main inductance contributor of the second grounded circuit structure 425 is grounded circuit rails 430, is labeled as " L2 " in Figure 14.
In execution mode, the feature of the corresponding grounded circuit structure shown in Fig. 9-Figure 14 can form according to any suitable size and shape, and can form according to any suitable spatial relationship with respect to holding wire (for example, 200,300,400).Especially, corresponding grounded circuit structure (for example, G1 and G2) feature can form like this, make transmission line structure (for example postpone according to which grounded circuit structure, G1 or G2) be grounded and difference, and no matter which grounded circuit structure is grounded, it is constant that the transmission line structure characteristic impedance all keeps in fact.In execution mode, characteristic impedance is set to about 50ohm, but the invention is not restricted to this value, and any characteristic impedance can be used with the present invention.
Up to the present each has comprised two switchable grounded circuit structures described transmission line structure.Yet, the invention is not restricted to only have the transmission line structure of two changeable grounded circuit structures.But more than two changeable grounded circuit structures such as (for example, three, four) can be used to transmission line structure that bigger adjustability is provided.
In other execution mode, can be by forming a plurality of adjustable delaies, blocked impedance part along the transmission line series connection, coming provides additional adjustability for transmission line.For example, Figure 15 shows the block diagram of the each side according to the present invention, and wherein transmission line 500 extends between two points 501,502.Transmission line 500 provides three corresponding parts 510,515,520 of adjustable delay, blocked impedance, and it can use the structure that is similar to reference to figure 1-Figure 14 description to form.
More specifically, first 510 can comprise such transmission line structure, and it has three and selects controlled length of delay t1, t2, t3, and constant relatively characteristic impedance Zo.Similarly, second portion can comprise such transmission line structure, and it has three and selects controlled length of delay t4, t5, t6, and constant relatively characteristic impedance Zo.Similarly, third part 520 can comprise such transmission line structure, and it has three and selects controlled length of delay t7, t8, t9, and constant relatively characteristic impedance Zo.
According to an aspect of the present invention, part 510,515 is identical with 520, makes t1=t4=t7, and t2=t5=t8, and t3=t6=t9.In such execution mode, transmission line 500 exists ten kinds of different delays to arrange, and every kind of arrangement has identical in fact characteristic impedance Zo.According to a further aspect in the invention, part 510,515 and 520 all is different, makes t1 ≠ t2 ≠ t3 ≠ t4 ≠ t5 ≠ t6 ≠ t7 ≠ t8 ≠ t9.In such execution mode, transmission line 500 exists 20 kinds of different delays to arrange, and every kind of arrangement has identical in fact characteristic impedance Zo.
Figure 16 is a flow chart of realizing the step of each side according to the present invention.Flow chart can be represented high level block diagram of the present invention equivalently.In the client-server relation, the step of flow chart can be by the computing equipment in ad hoc (self-organizing) network by server controls and execution, and perhaps it can utilize the operation information that is sent to the teller work station and move on the teller work station.And, the present invention can use the execution mode of devices at full hardware, fully software execution mode or comprise that the two execution mode of hardware and software element controls.In one embodiment, software element comprises firmware, resident software, microcode etc.
In addition, the present invention can be used or the addressable computer program control of computer-readable medium by computer, uses or connected code to provide by computer or any instruction execution system.For the purpose of this specification, computer can with or computer-readable medium can be comprise, any device of storage, communication, propagation or convey program, this program is used by instruction execution system, device or equipment or is connected with it.Medium can be electronics, magnetic, light, electromagnetism, infrared or semiconductor system (perhaps device or equipment) or propagation medium.The example of computer-readable medium comprises semiconductor or solid-state memory, tape, movable computer floppy disk, random-access memory (ram), read-only memory (ROM), hard disc and CD.The current example of CD comprises compact disk-read-only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD.
More specifically, Figure 16 shows the flow chart of the controlled step of the method for drawing the delay that is used for regulating transmission line structure.In step 610, the first grounded circuit structure of transmission line structure is electrically connected to earth potential.In execution mode, transmission line structure and grounded circuit structure can be similar to transmission line structure and the grounded circuit structure of above describing with reference to figure 4-Figure 15 (for example G1).In execution mode, the switch that is integrated in by operation in the semiconductor device zone of transmission line structure is created connection.The operation of switch can be carried out according to any suitable mode, such as, computer control.As the result of step 610, the first grounded circuit structure is provided as the grounded circuit path of the holding wire of transmission line structure.
In step 620, the second grounded circuit structure and the earth potential electricity that are integrated in the identical traffic line structure disconnect.The second grounded circuit structure can be similar to the grounded circuit structure of above describing with reference to figure 4-Figure 15 (for example G2), make the delay of transmission line structure according to which grounded circuit grounding structure and difference, and no matter the characteristic impedance of which grounded circuit grounding structure transmission line structure all keeps constant in fact.In execution mode, the disconnection at step 620 place can be carried out with being connected simultaneously of step 610 place, perhaps carried out in the different moment.In addition, the disconnection at step 620 place can use the switch identical with the connection at step 610 place to carry out, and perhaps uses different switches to carry out.
In step 630, signal transmits on the holding wire of transmission line structure.In execution mode, transmission signals can be carried out according to any suitable mode.Because the connection at step 610 place, the delay that transmission has will mainly be determined by the first grounded circuit structure.
In step 640, the first grounded circuit structure and earth potential disconnect, and the second grounded circuit structure is connected to earth potential.This can carry out according to the mode that is similar to step 610 and 620, replaces the second grounded circuit structure with the first grounded circuit structure, and vice versa.As the result of step 640, the second grounded circuit structure is provided as the grounded circuit path of the holding wire of transmission line structure; The first grounded circuit structure is unsettled simultaneously.
In step 650, signal transmits on the holding wire of transmission line structure.This can be according to carrying out with the similar mode of step 630.Because step 640, the delay that transmission has will mainly be determined by the second grounded circuit structure.In execution mode, the delay at step 650 place is different from the delay at step 630 place; Yet the characteristic impedance of transmission line structure is identical in transmitting step 630 and 650.
Figure 17 shows the block diagram of the exemplary design flow process 900 that for example is used for semiconducter IC logical design, emulation, test, layout and manufacturing.Design cycle 900 comprises process and the mechanism that is used for Treatment Design structure or equipment, to generate the above and equivalently represented on the in logic and/or otherwise function of project organization shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15 and/or equipment.The project organization that design cycle 900 is handled and/or generated can be coded in machine readable transmission or the storage medium comprising data and/or instruction, the logic of these data and/or instruction generation nextport hardware component NextPort, circuit, equipment or system when carrying out on data handling system or otherwise handling, structure, machinery or equivalently represented on the function otherwise.Design cycle 900 can change according to the type of the expression that is designing.For example, the design cycle 900 that is used to make up application-specific integrated circuit (ASIC) can be different from the design cycle 900 that is used for the design standard assembly or be used for design exampleization to programmable array (for example by
Inc. or
Inc. programmable gate array that provides (PGA) or field programmable gate array (FPGA)) in design cycle 900.
Figure 17 shows a plurality of these type of project organizations, comprises input project organization 920, and it is preferably handled by design process 910.Project organization 920 can be the logical simulation project organization that is generated and handled by design process 910, to produce the logically equivalent functional representation of hardware device.Project organization 920 can also or alternatively can comprise data and/or program command, when handling these data and/or program command by design process 910, generates the functional representation of the physical structure of hardware device.Whether no matter presentation function and/or structural design features, project organization 920 can use such as the electronic computer Aided Design (ECAD) that is realized by core developer/designer and generate.In the time of on being coded in machine-readable data transmission, gate array or storage medium, project organization 920 can be visited and be handled by one or more hardware and/or the software modules in the design process 910, with emulation or otherwise represent electronic building brick, circuit, electronics or logic module, device, equipment or system shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15 functionally.Thus, project organization 920 can comprise file or other data structures, it comprises human and/or machine-readable source code, compiling structure and computer-executable code structure, when handling by design or emulated data treatment system, its emulation functionally or the otherwise hardware logic design of indication circuit or other layers.This type of data structure can comprise and meeting and/or hardware description language (HDL) design entity or other data structures of compatible rudimentary HDL design language (such as Verilog and VHDL) and/or high-level design languages (such as C or C++).
Term only is used to describe the purpose of specific implementations as used herein, is not to be intended to as restriction of the present invention.As used herein, singulative " a kind of ", " one " and " being somebody's turn to do " are intended to also comprise plural form, unless context spells out.It is also understood that, term " comprises " and/or " comprising ", when using in this manual, specify feature, integral body, step, operation, element and/or the assembly stated, but do not get rid of the existence of one or more other features, integral body, step, operation, element, assembly and/or its combination or additional.
The equivalent (if present) that corresponding structure, material, behavior and all devices or step add functional element in the claims is intended to comprise and is used to carry out as institute's specific requirement protection and any structure, material or the action combined function of other claimed elements.Specification of the present invention proposes for the purpose of illustration and description, and has more than in the present invention exhaustive or that be limited to disclosed form.Under situation about not departing from the scope of the present invention with spirit, multiple modification and variant will become to those of ordinary skills and easily see.Select and described execution mode, and make other those of ordinary skill of this area to understand the present invention at having the various execution modes that are suitable for the various modifications that particular desired uses so that explain principle of the present invention and practical application best.
Claims (44)
1. transmission line structure comprises:
Holding wire;
The first grounded circuit structure, it causes first to postpone and first characteristic impedance in transmission line structure; And
The second grounded circuit structure, it causes second to postpone and second characteristic impedance in described transmission line structure;
Wherein said first delay and described second postpones different, and described first characteristic impedance is identical in fact with described second characteristic impedance.
2. structure as claimed in claim 1, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are formed in the semiconductor structure.
3. structure as claimed in claim 2, wherein:
Described holding wire is formed in first wiring layer of described semiconductor structure,
The described first grounded circuit structure is formed in second wiring layer of described semiconductor structure, and
The described second grounded circuit structure is formed in the 3rd layer of described semiconductor structure.
4. structure as claimed in claim 3, wherein:
Described first wiring layer is different with described second wiring layer, and
The part of the described first grounded circuit structure also is formed in described first wiring layer.
5. structure as claimed in claim 4, wherein:
Described holding wire is formed in first wiring layer of described semiconductor structure,
The described first grounded circuit structure is formed in described first wiring layer, and
The part of the described second grounded circuit structure is formed in described first wiring layer and second wiring layer of described semiconductor structure.
6. structure as claimed in claim 2, wherein switching manipulation in order to respectively with a ground connection in described first grounded circuit structure and the described second grounded circuit structure, and in described second grounded circuit structure and the described first grounded circuit structure another is unsettled.
7. structure as claimed in claim 2, wherein:
The described first grounded circuit structure comprises the first grounded circuit rail and first capacitance structure, and
The described second grounded circuit structure comprises the second grounded circuit rail and second capacitance structure.
8. structure as claimed in claim 7, wherein:
The described first grounded circuit rail than the described second grounded circuit rail further from described holding wire, and
Described first capacitance structure is than the more close described holding wire of described second capacitance structure.
9. structure as claimed in claim 1, it is the delay of signal in the described holding wire that wherein said first delay and described second postpones.
10. semiconductor structure comprises:
Holding wire,
The first grounded circuit rail and first capacitance structure; And
The second grounded circuit rail and second capacitance structure,
The wherein said first grounded circuit rail than the described second grounded circuit rail further from described holding wire,
Described first capacitance structure is than the more close described holding wire of described second capacitance structure, and
The ground connection of described holding wire can optionally be switched between described first grounded circuit rail and the described second grounded circuit rail.
11. structure as claimed in claim 10, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are included in the transmission line structure.
12. structure as claimed in claim 11, wherein:
The described first grounded circuit structure is created first and is postponed and first characteristic impedance in described transmission line structure,
The described second grounded circuit structure is created with described first and is postponed the second different delays, and second characteristic impedance that equates in fact with described first characteristic impedance.
13. structure as claimed in claim 12 also comprises the 3rd grounded circuit structure, is used to create the 3rd and postpones and the 3rd characteristic impedance,
The wherein said the 3rd postpones to postpone to be different in essence with described first delay and described second, and described the 3rd characteristic impedance equates in fact with described first characteristic impedance and described second characteristic impedance.
14. structure as claimed in claim 11, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are formed in the wiring layer on the substrate.
15. a project organization that visibly is included in the machine readable media is used for design, manufacturing or testing integrated circuits, described project organization comprises:
Holding wire;
The first grounded circuit structure, it causes first to postpone and first characteristic impedance in transmission line structure; And
The second grounded circuit structure, it causes second to postpone and second characteristic impedance in described transmission line structure;
Wherein said first delay and described second postpones different, and described first characteristic impedance is identical in fact with described second characteristic impedance.
16. project organization as claimed in claim 15, wherein said project organization comprises the net table.
17. project organization as claimed in claim 15, wherein said project organization resides on the storage medium, as the data format of the topology data exchange that is used for integrated circuit.
18. project organization as claimed in claim 15, wherein said project organization resides in the programmable gate array.
19. hardware description language (HDL) project organization that is coded on the machine-readable data storage media, described HDL project organization is included in the element that the machine that generates transmission line structure in the computer aided design system when processed can be carried out expression, and wherein said HDL project organization comprises:
Holding wire;
The first grounded circuit rail and first capacitance structure; And
The second grounded circuit rail and second capacitance structure,
The wherein said first grounded circuit rail than the described second grounded circuit rail further from described holding wire,
Described first capacitance structure is than the more close described holding wire of described second capacitance structure.
20. a method of making transmission line structure comprises:
Form the holding wire of described transmission line structure;
Form the first grounded circuit structure, the described first grounded circuit structure causes first to postpone and first characteristic impedance in described transmission line structure; And
Form the second grounded circuit structure, the described second grounded circuit structure causes second to postpone and second characteristic impedance in described transmission line structure;
Wherein said first delay and described second postpones different, and described first characteristic impedance is identical in fact with described second characteristic impedance.
21. method as claimed in claim 20, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are formed in the semiconductor structure.
22. method as claimed in claim 21, wherein:
Described holding wire is formed in first wiring layer of described semiconductor structure,
The described first grounded circuit structure is formed in second wiring layer of described semiconductor structure, and
The described second grounded circuit structure is formed in the 3rd layer of described semiconductor structure.
23. method as claimed in claim 22, wherein:
Described first wiring layer is different with described second wiring layer, and
The part of the described first grounded circuit structure also is formed in described first wiring layer.
24. method as claimed in claim 23, wherein:
Described holding wire is formed in first wiring layer of described semiconductor structure,
The described first grounded circuit structure is formed in described first wiring layer, and
The part of the described second grounded circuit structure is formed in described first wiring layer and second wiring layer of described semiconductor structure.
25. method as claimed in claim 21, wherein switching manipulation in order to respectively with a ground connection in described first grounded circuit structure and the described second grounded circuit structure, and in described second grounded circuit structure and the described first grounded circuit structure another is unsettled.
26. method as claimed in claim 21, wherein:
The described first grounded circuit structure comprises the first grounded circuit rail and first capacitance structure, and
The described second grounded circuit structure comprises the second grounded circuit rail and second capacitance structure.
27. method as claimed in claim 26, wherein:
The described first grounded circuit rail than the described second grounded circuit rail further from described holding wire, and
Described first capacitance structure is than the more close described holding wire of described second capacitance structure.
28. method as claimed in claim 20, it is the delay of signal in the described holding wire that wherein said first delay and described second postpones.
29. method as claimed in claim 20, wherein said first postpones to be about 16% with described second difference that postpones.
30. method as claimed in claim 29, the difference of wherein said first characteristic impedance and described second characteristic impedance is less than about 5%.
31. method as claimed in claim 30, wherein said first characteristic impedance is about 50ohm.
32. a method of making semiconductor structure comprises:
Form holding wire,
Form the first grounded circuit rail and first capacitance structure; And
Form the second grounded circuit rail and second capacitance structure,
The wherein said first grounded circuit rail than the described second grounded circuit rail further from described holding wire,
Described first capacitance structure is than the more close described holding wire of described second capacitance structure, and
The ground connection of described holding wire is optionally switched between described first grounded circuit rail and the described second grounded circuit rail.
33. method as claimed in claim 32, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are included in the transmission line structure.
34. method as claimed in claim 33, wherein:
The described first grounded circuit structure is created first and is postponed and first characteristic impedance in described transmission line structure,
The described second grounded circuit structure is created with described first and is postponed the second different delays, and second characteristic impedance that equates in fact with described first characteristic impedance.
35. method as claimed in claim 34 comprises also forming the 3rd grounded circuit structure that described the 3rd grounded circuit structure is created the 3rd and postponed and the 3rd characteristic impedance,
The wherein said the 3rd postpones to postpone to be different in essence with described first delay and described second, and described the 3rd characteristic impedance equates in fact with described first characteristic impedance and described second characteristic impedance.
36. method as claimed in claim 33, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are formed in the wiring layer on the substrate.
37. the method for a transmission signals in transmission line structure comprises:
With the first grounded circuit grounding structure, the described first grounded circuit structure causes first to postpone and first characteristic impedance in described transmission line structure;
The second grounded circuit structure is unsettled, and the described second grounded circuit structure causes postponing the second different delays with described first, and second characteristic impedance identical in fact with described first characteristic impedance; And
Transmission signals on the holding wire of described transmission line structure.
38. method as claimed in claim 37, wherein said holding wire, the described first grounded circuit structure and the described second grounded circuit structure are formed in the semiconductor structure.
39. method as claimed in claim 38, wherein said ground connection and described unsettled at least one switch that comprises in the described semiconductor structure of operation.
40. method as claimed in claim 37 also comprises:
The described first grounded circuit structure is unsettled;
With the described second grounded circuit grounding structure; And
Another signal of transmission on described holding wire.
41. method as claimed in claim 37, wherein:
Described first postpones to be at least about 16% with described second difference that postpones, and
The difference of described first characteristic impedance and described second characteristic impedance is less than about 5%.
42. a method comprises:
In (i) first grounded circuit structure and (ii) switch transmission line structure between the second grounded circuit structure, the wherein said first grounded circuit structure causes first to postpone and first characteristic impedance in described transmission line structure, and the described second grounded circuit structure is created second of described transmission line structure and is postponed and second characteristic impedance
Wherein said first postpones to be different in essence with described second delay, and described first characteristic impedance equates in fact with described second characteristic impedance.
43. method as claimed in claim 42, wherein said first grounded circuit structure and the described second grounded circuit structure are formed in the wiring layer of single semiconductor structure.
44. method as claimed in claim 42, wherein said switching is carried out by in computer program and the computing equipment at least one.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/144,684 | 2008-06-24 | ||
| US12/144,682 US8138857B2 (en) | 2008-06-24 | 2008-06-24 | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
| US12/144,684 US8193878B2 (en) | 2008-06-24 | 2008-06-24 | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
| US12/144,682 | 2008-06-24 | ||
| PCT/US2009/047598 WO2010008742A1 (en) | 2008-06-24 | 2009-06-17 | Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102027633A true CN102027633A (en) | 2011-04-20 |
| CN102027633B CN102027633B (en) | 2014-11-05 |
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|---|---|---|---|
| CN200980117714.8A Active CN102027633B (en) | 2008-06-24 | 2009-06-17 | Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR20110031277A (en) |
| CN (1) | CN102027633B (en) |
| MX (1) | MX2010013267A (en) |
| WO (1) | WO2010008742A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914583A (en) * | 2013-01-02 | 2014-07-09 | 国际商业机器公司 | Semiconductor device and method for reducing differences in path delays thereof |
| CN103972212A (en) * | 2013-01-25 | 2014-08-06 | 台湾积体电路制造股份有限公司 | Methods and apparatus for transmission lines in packages |
| CN105025663A (en) * | 2014-04-30 | 2015-11-04 | 日月光半导体制造股份有限公司 | Packaging structure with line type electronic component, and manufacturing method thereof |
| CN106257834A (en) * | 2015-06-22 | 2016-12-28 | 特克特朗尼克公司 | Electronic variable analog delay line |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8988166B2 (en) | 2011-10-02 | 2015-03-24 | International Business Machines Corporation | Structure and compact modeling of variable transmission lines |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4706177A (en) * | 1985-11-14 | 1987-11-10 | Elliot Josephson | DC-AC inverter with overload driving capability |
| US5723908A (en) * | 1993-03-11 | 1998-03-03 | Kabushiki Kaisha Toshiba | Multilayer wiring structure |
| JP2000067595A (en) * | 1998-06-09 | 2000-03-03 | Mitsubishi Electric Corp | Semiconductor memory |
| US6674174B2 (en) * | 2001-11-13 | 2004-01-06 | Skyworks Solutions, Inc. | Controlled impedance transmission lines in a redistribution layer |
| US6816031B1 (en) * | 2001-12-04 | 2004-11-09 | Formfactor, Inc. | Adjustable delay transmission line |
| US7332983B2 (en) * | 2005-10-31 | 2008-02-19 | Hewlett-Packard Development Company, L.P. | Tunable delay line using selectively connected grounding means |
| US7689962B2 (en) * | 2006-02-08 | 2010-03-30 | Roberto Suaya | Extracting high frequency impedance in a circuit design using an electronic design automation tool |
-
2009
- 2009-06-17 KR KR1020107026828A patent/KR20110031277A/en not_active Application Discontinuation
- 2009-06-17 CN CN200980117714.8A patent/CN102027633B/en active Active
- 2009-06-17 MX MX2010013267A patent/MX2010013267A/en active IP Right Grant
- 2009-06-17 WO PCT/US2009/047598 patent/WO2010008742A1/en active Application Filing
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914583A (en) * | 2013-01-02 | 2014-07-09 | 国际商业机器公司 | Semiconductor device and method for reducing differences in path delays thereof |
| CN103972212A (en) * | 2013-01-25 | 2014-08-06 | 台湾积体电路制造股份有限公司 | Methods and apparatus for transmission lines in packages |
| US10269746B2 (en) | 2013-01-25 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
| US10840201B2 (en) | 2013-01-25 | 2020-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
| CN105025663A (en) * | 2014-04-30 | 2015-11-04 | 日月光半导体制造股份有限公司 | Packaging structure with line type electronic component, and manufacturing method thereof |
| CN105025663B (en) * | 2014-04-30 | 2019-05-10 | 日月光半导体制造股份有限公司 | Encapsulating structure and its manufacturing method with circuit type electronic component |
| CN106257834A (en) * | 2015-06-22 | 2016-12-28 | 特克特朗尼克公司 | Electronic variable analog delay line |
| CN106257834B (en) * | 2015-06-22 | 2021-11-09 | 特克特朗尼克公司 | Electronically variable analog delay line |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20110031277A (en) | 2011-03-25 |
| WO2010008742A1 (en) | 2010-01-21 |
| CN102027633B (en) | 2014-11-05 |
| MX2010013267A (en) | 2011-02-25 |
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