CN102027633B - Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance - Google Patents
Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance Download PDFInfo
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- CN102027633B CN102027633B CN200980117714.8A CN200980117714A CN102027633B CN 102027633 B CN102027633 B CN 102027633B CN 200980117714 A CN200980117714 A CN 200980117714A CN 102027633 B CN102027633 B CN 102027633B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P9/00—Delay lines of the waveguide type
- H01P9/006—Meander lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P9/00—Delay lines of the waveguide type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A transmission line structure includes a signal line (50) (e.g. S), a first ground return structure (55) (e.g. G1) that causes a first delay (t1) and a first characteristic impedance (ZoI) in the transmission line structure, and a second ground return structure (75) (e.g. G2) that causes a second delay (t2) and a second characteristic impedance (Zo2) in the transmission line structure. The first delay (t1) is different from the second delay (t2), and the first characteristic impedance (Zo1) is substantially the same as the second characteristic impedance (Zo2).
Description
Technical field
The present invention relates to transmission line, and more specifically, relate to project organization, structure and method for variable delay transmission line on the sheet with fixed characteristic impedance is provided.
Background technology
On traditional sheet, transmission line structure generally has blocked impedance and fixed delay.Conventionally,, for given transmission line, cannot select arbitrarily to postpone and impedance.On the contrary, delay and impedance are subject to the impact of electric capacity and inductance, and wherein electric capacity and the inductance distance based between holding wire and grounded circuit line reciprocally changes.Therefore, be possible although change the delay of transmission line, changing the cost postponing is to increase loss of signal, change characteristic impedance and/or increase the required area (for example area occupied) of transmission-line device.
But for a lot of application, the delay that changes transmission line is expected.For example, in signal processing operations, use delay line, to regulate the time of advent of a signal with respect to secondary signal.Can carry out manufacturing delay line for digital circuit or analog circuit, and delay can be that fix or variable.Have sine-shaped signal (this is common situation in microwave applications) for postponing, the effect of delay line is to give phase shift; Thus, in this case, delay line can be considered phase shifter.
In phased array, can use multiple phase place adjustable lines.Generally speaking, phased array is one group of antenna, and wherein the relative phase of the corresponding signal of feed antenna changes as follows: the effective radiation pattern that makes array is at the orientation enhancement of expecting and suppressed in less desirable direction.Determined effective radiation pattern of array by the relative amplitude between the signal of single antenna radiation and constructive interference and destructive interference effect.Phased array is used to control electronically the peak response direction of receiver, and the higher antenna gain of spatial selectivity or equivalence is provided.Phased array can be used for, in multiple different wireless application, including but not limited to RADAR and data communication.Wave beam control realizes like this: first with progressive amount, the phase place of each reception signal is offset, to compensate the successive difference arriving between phase place.Then combine these signals, wherein for the direction superposed signal constructively of expecting, for superposed signal destructively of other directions.
The traditional approach of controlling the phase place of each element in phased array is: for each element provides multiple transmission lines, each transmission line has known delay.Switch in the signal path of each element is used for selecting the specific transmission line of this element, thereby gives element known delay.But such system has multiple shortcomings.For example,, for each element provides multiple transmission lines for example, in the cost of the aspects such as usage space (, area occupied), manufacture higher.And the switch in the signal path of each element will cause signal attenuation, this is less desirable in this type of application.
In addition, as mentioned above, traditional system cannot be not increasing loss of signal, do not change characteristic impedance and/or do not increase the delay that for example, changes transmission line in the situation of the needed area of transmission-line device (, area occupied).Use the system (for example, phased array antenna system) postponing to there is these shortcomings.
Therefore, in this area, there are the needs that overcome above-mentioned defect and restriction.
Summary of the invention
In a first aspect of the present invention, a kind of transmission line structure, comprising: holding wire; The first grounded circuit structure, it causes the first delay and the first characteristic impedance in transmission line structure; And the second grounded circuit structure, it causes the second delay and the second characteristic impedance in transmission line structure.The first delay and second postpones different, and the first characteristic impedance is identical in fact with the second characteristic impedance.
In execution mode, holding wire, the first grounded circuit structure and the second grounded circuit structure are formed at semiconductor structure.Holding wire can be formed at first wiring layer (wiring level) of semiconductor structure, and the first grounded circuit structure can be formed at the second wiring layer of semiconductor structure, and the second grounded circuit structure can be formed at the 3rd layer of semiconductor structure.In addition, the first wiring layer can be different from the second wiring layer, and the part of the first grounded circuit structure also can be formed at the first wiring layer.In other execution mode, holding wire is formed at the first wiring layer of semiconductor structure, and the first grounded circuit structure is formed at the first wiring layer, and the part of the second grounded circuit structure is formed at the first wiring layer and second wiring layer of semiconductor structure.
The each side according to the present invention, switch operates respectively in order to by a ground connection in the first grounded circuit structure and the second grounded circuit structure, and makes another in the second grounded circuit structure and the first grounded circuit structure unsettled.In addition, the first grounded circuit structure can comprise the first grounded circuit rail and the first capacitance structure, and the second grounded circuit structure can comprise the second grounded circuit rail and the second capacitance structure.In addition, the first grounded circuit rail can be than the second grounded circuit rail further from holding wire, and the first capacitance structure can be than the more close holding wire of the second capacitance structure.It can be the delay of signal in holding wire that the first delay and second postpones.
In a second aspect of the present invention, a kind of semiconductor structure, comprising: holding wire; The first grounded circuit rail and the first capacitance structure; And second grounded circuit rail and the second capacitance structure.The first grounded circuit rail is than the second grounded circuit rail further from holding wire, and the first capacitance structure is than the more close holding wire of the second capacitance structure, and the ground connection of holding wire can optionally be switched between the first grounded circuit rail and the second grounded circuit rail.
In a third aspect of the present invention, a kind of for designing, manufacture or project organization testing integrated circuits, that be visibly included in machine readable media, this project organization comprises: holding wire; The first grounded circuit structure, it causes the first delay and the first characteristic impedance in transmission line structure; And the second grounded circuit structure, it causes the second delay and the second characteristic impedance in transmission line structure.The first delay and second postpones different, and the first characteristic impedance is identical in fact with the second characteristic impedance.
In a fourth aspect of the present invention, a kind of hardware description language (HDL) project organization being coded in machine-readable data storage media, described HDL project organization comprises element, in the time that this element is processed in computer aided design system, the machine that generates transmission line structure can be carried out expression, and wherein this HDL project organization comprises: holding wire; The first grounded circuit rail and the first capacitance structure; And second grounded circuit rail and the second capacitance structure.The first grounded circuit rail is than the second grounded circuit rail further from holding wire, and the first capacitance structure is than the more close holding wire of the second capacitance structure.
Brief description of the drawings
According to the mode of the non-limiting example of illustrative embodiments of the present invention, multiple accompanying drawings of reference marker are described the present invention in embodiment below.
Fig. 1-Fig. 5 shows the structure of the each side according to the present invention;
Fig. 6-Fig. 8 shows intermediate structure and the processing step of the each side according to the present invention;
Fig. 9-Figure 14 shows the structure of the each side according to the present invention;
Figure 15 shows the block diagram of the each side according to the present invention;
Figure 16 is the flow chart of drawing the technique of each side according to the present invention;
Figure 17 is the flow chart of the design process of use in semiconductor design, manufacture and/or test.
Embodiment
The present invention relates to transmission line, and more specifically, relate to project organization, structure and method for variable delay transmission line on the sheet with fixed characteristic impedance is provided.In execution mode, transmission line structure has multiple selectable grounded circuits path.More specifically, each grounded circuit path is formed with different geometries, and different from the distance of holding wire, makes each grounded circuit path cause transmission line structure to have different delays.In addition, grounding path designs like this, makes no matter use which grounding path, and it is constant in fact that the characteristic impedance of transmission line structure all keeps.In this way, by controlling which grounded circuit grounding structure, and which is unsettled, can substantially not change the delay that changes transmission line structure in the situation of characteristic impedance of transmission line structure.Therefore, realization of the present invention provides single microstrip structure, wherein postpone to change, and characteristic impedance maintenance is relatively constant.
Fig. 1 shows the schematic diagram of the structure of each side according to the present invention.This structure comprises holding wire 10 and grounded circuit line 15, and it can be formed in the wiring layer of semiconductor device, as detailed below.Semiconductor device for example can comprise transmission line structure.
The characteristic impedance of transmission line structure can be similar to the square root of the ratio of inductance (" L ") and electric capacity (" C "), for example SQRT (L/C), and this is known, therefore thinks without further explanation.In addition, the delay of transmission line structure can be similar to the square root of the product of inductance and electric capacity, for example SQRT (L*C).And the electric capacity of transmission line structure reduces along with the distance between holding wire and grounded circuit line conventionally, and the inductance of transmission line structure increases along with the distance between holding wire and grounded circuit line conventionally.
Therefore, if grounded circuit line 15 moves near holding wire 10, the electric capacity of transmission line structure will increase, and the inductance of transmission line structure will reduce.Alternatively, along with grounded circuit line 15 moves away from holding wire 10, the electric capacity of transmission line structure reduces, and the inductance of transmission line structure increases.Because electric capacity and inductance are with respect to this relativeness of distance between holding wire and grounded circuit line, can not change that transmission line structure postpones and the characteristic impedance that do not change transmission line structure by traditional structure.
But, the each side according to the present invention, the structure shown in Fig. 1 comprises capacitance shield (shield) 20, it,, in the case of significantly not changing the inductance of transmission line structure, optionally changes the electric capacity of transmission line structure.As shown in Figure 1, capacitance shield 20 is formed between holding wire 10 and grounded circuit line 15, for example, is formed in the wiring layer between holding wire 10 and the corresponding wiring line layer of grounded circuit line 15.In the execution mode shown in Fig. 1, capacitance shield 20 comprises the trace 25 forming with snakelike form, between trace 25 parts, has the interval vertical with holding wire 10 30.In this way, capacitance shield 20 can be for affecting the electric capacity of transmission line structure, and induction is invisible in fact.
Still with reference to figure 1, in the time that capacitance shield 20 is grounded to grounded circuit line 15, the electric capacity of transmission line structure will be the first value, and when capacitance shield 20 unsettled (for example, be not grounded to grounded circuit line 15) time, the electric capacity of transmission line structure will be second value different from the first value.In this way, by the switch in use grounded circuit path (for example, in semi-conductive active area), capacitance shield 20 can be optionally ground connection and unsettled between switch, to optionally change the capacitance of transmission line structure, keep the inductance of transmission line structure relatively constant simultaneously.
The difference of electric capacity between ground connection and the vacant state of capacitance shield 20 will depend on such as following parameter: for example, and the vertical range between holding wire 10 and the plane of capacitance shield 20, the width of trace 25, and the width at interval 30.In execution mode, these parameters can be used any suitable value.For example, table 1 shows the comparison of the ground connection of two exemplary arrangement and the electric capacity of vacant state and inductance value.In the first layout, the width of trace 25 is approximately 1 μ m, and the width at interval 30 is approximately 1 μ m.In the second layout, the width of trace 25 is approximately 2 μ m, and the width at interval 30 is approximately 2 μ m.
Table 1
| Arrange | The state of capacitance shield | Electric capacity (millimicro microfarad) | Inductance (Pi Heng) |
| First | Unsettled | 15.009 | 11.627 |
| First | Ground connection | 20.186 | 11.615 |
| Second | Unsettled | 14.797 | 11.678 |
| Second | Ground connection | 19.293 | 11.656 |
Fig. 2 shows another structure of the each side according to the present invention.Similar with Fig. 1, this structure comprises holding wire 10, grounded circuit line 15 and capacitance shield 20, and it can be formed by the metal in the wiring layer of the semiconductor device such as transmission line.The structure of Fig. 2 comprises the second capacitance shield 35, and it is arranged between the first capacitance shield 20 and grounded circuit line 15.At least one switch (not shown) may be operably coupled to grounded circuit line 15, the first capacitance shield 20 and the second capacitance shield 35, make a shielding can be grounded to grounded circuit line, and another shielding is unsettled.
Table 2 shows according to the electric capacity of the transmission line structure of Fig. 2 and inductance value.The value of table 2 is for following transmission line, and wherein the width of the trace 25 of each capacitance shield 20,35 is approximately 2 μ m, and the width at interval 30 between the part of trace is approximately 2 μ m.Easily see according to table 2, can be by optionally by one of capacitance shield 20,35 or the two ground connection, to control the electric capacity of transmission line structure, inductance keeps relatively constant simultaneously.
Table 2
Fig. 3 shows another transmission line structure of the each side according to the present invention.This transmission line structure comprises holding wire 50, and it can be the metal wire being for example formed in the wiring layer of semiconductor device, as detailed below.Transmission line structure also comprises grounded circuit structure 55, and it can comprise the metal structure in wiring layer under the layer that is for example formed at holding wire 50, in semiconductor device, as detailed below.
In execution mode, grounded circuit structure 55 comprises grounded circuit rail 60, and it is parallel in fact holding wire 50.And grounded circuit structure 55 comprises electric capacity carding element 65, it is formed between grounded circuit rail 60, and is orthogonal in fact holding wire 50.In such transmission line structure, the electric capacity of transmission line structure equals the electric capacity of the plane from holding wire to electric capacity carding element 65, and the inductance of transmission line structure is formed in the current loop path of grounded circuit rail 60 and holding wire 50.
Fig. 4 shows another transmission line structure of the each side according to the present invention.Be similar to the transmission line structure of Fig. 3, the transmission line structure of Fig. 4 comprises holding wire 50 and grounded circuit structure 55 (being called " G1 " in this figure and other accompanying drawings), and it has grounded circuit rail 60 and carding element 65.In addition, the transmission line structure in Fig. 4 comprises the second grounded circuit structure 75 (being called " G2 " in this figure and other accompanying drawings), and it has grounded circuit rail 80 and carding element 85.The second grounded circuit structure 75 for example can comprise the metal structure in wiring layer under the layer that is formed at the first grounded circuit structure 55, semiconductor device, as detailed below.Can provide at least one switch (not shown) for switch the first grounded circuit structure 55 and the second grounded circuit structure 75 between ground connection and vacant state, to make the grounded circuit path of transmission line structure follow the first grounded circuit structure or the second grounded circuit structure.
In execution mode, electric capacity comb 65,85 forms perpendicular to holding wire 50, and has that to make it be sightless size and dimension for holding wire 50 in fact in induction.Thus, the grounded circuit rail that the inductance of transmission line structure is formed at holding wire 50 and any one grounded circuit structure being grounded (for example, 60 or 80) in current loop path, and hanging structure very little or not impact on the inductive impact of transmission line structure.So, for example, in the state of and the second grounded circuit structure 75 ground connection unsettled in the first grounded circuit structure 55, the inductance of transmission line structure is formed in the current loop path of grounded circuit rail 80 and holding wire 50, the very little or not impact of the impact of the inductance of the first grounded circuit structure 55 on transmission line structure.
Similarly, the electric capacity of the transmission line structure shown in Fig. 4 mainly for example, is driven by one (, 55 or 75) of ground connection in grounded circuit structure.That is to say, in the state of and the second grounded circuit structure 75 ground connection unsettled in the first grounded circuit structure 55, the electric capacity of transmission line structure equals in fact the electric capacity of the plane from holding wire to comb 85 upper surfaces.But different from inductance, the electric capacity of unsettled grounded circuit structure influence transmission line structure, although the capacity effect of hanging structure is compared little with the capacity effect of ground structure.
In execution mode, the first grounded circuit structure 55 and the second grounded circuit structure 75 are formed as having geometry and the distance with holding wire 50, thus, depend on which in two grounded circuit structures is grounded, transmission line structure will have different delay (for example, SQRT (L*C)).But, geometry and the relative position of the first grounded circuit structure 55 and the second grounded circuit structure 75 also design like this, which make no matter the ground connection in two grounded circuit structures, the characteristic impedance (for example, SQRT (L/C)) of transmission line structure is constant in fact.In this way, for example, by controlling which grounded circuit structure (, 55 or 75) ground connection and which is unsettled, can substantially not change the delay that changes transmission line structure in the situation of characteristic impedance of transmission line structure.Therefore, realization of the present invention provides a kind of single microstrip structure, wherein postpone can change and characteristic impedance keep relatively constant.
For example, still with reference to the example arrangement shown in figure 4, in embodiments of the present invention, size and the interval of regulated ground loop rail 60, make its than grounded circuit rail 80 further from holding wire 50.This causes inductance that the first grounded circuit structure 55 (for example, G1) provides for example, higher than the second grounded circuit structure 75 (, G2).In addition, the size of regulation comb 65 and interval, make it than comb 85 more close holding wires 50, makes electric capacity that the first grounded circuit structure 55 provides higher than the second grounded circuit structure 75.For example, by suitably selecting size and the position of feature (, 50,60,65,80,85), can realize following relation:
t1＝SQRT(L1*C1)＞t2＝SQRT(L2*C2)
Wherein:
Transmission line structure when t1 ≡ G1 ground connection and G2 are unsettled postpones;
Transmission line structure when t2 ≡ G2 ground connection and G1 are unsettled postpones;
Transmission line structure characteristic impedance when Zo1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure characteristic impedance when Zo2 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure inductance when L1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure electric capacity when C1 ≡ G1 ground connection and G2 are unsettled;
Transmission line structure inductance when L2 ≡ G2 ground connection and G1 are unsettled;
Transmission line structure electric capacity when C2 ≡ G2 ground connection and G1 are unsettled.
Fig. 5 shows another structure of the each side according to the present invention.The structure that Fig. 5 paints is similar to the structure shown in Fig. 4, and it comprises holding wire 50, has the first grounded circuit structure 55 of grounded circuit rail 60 and comb 65 and have grounded circuit rail 80 and the second grounded circuit structure 75 of comb 85 in the figure.
In the example arrangement shown in Fig. 5, what holding wire 50 was formed at analog semiconductor structure goes up wiring layer (for example, N layer) most, and has the width of about 10 μ m in " x " direction, and has the length of about 50 μ m in " y " direction.In execution mode, the first grounded circuit structure 55 is formed in N-1 wiring layer, and has the length identical with holding wire 50 in " y " direction.Comb 65 each length in " x " direction with about 100 μ m, and the each width in " x " direction with about 8 μ m of grounded circuit rail 60.And the second grounded circuit structure 75 is formed in N-4 wiring layer, and there is the length identical with holding wire 50 in " y " direction.Comb 85 each length in " x " direction with about 50 μ m, and the each width in " x " direction with about 12 μ m of grounded circuit rail 80.
Table 3 shows the value of transmission line structure electric capacity, transmission line structure inductance, transmission line structure characteristic impedance and the transmission line structure delay of the example arrangement shown in Fig. 5.
Table 3
As shown in table 3, between two states, realized about 16.1% transmission line structure delay change, and the characteristic impedance of transmission line structure only changes about 5.5% between two identical states.Although described specific dimensions, size and geometry, the invention is not restricted to these specific examples.But, by using different semiconductor structures, can obtain about 30% to 40% delay difference, still keep nearly about 5% characteristic impedance difference simultaneously.More specifically, can in realization of the present invention, use the structure (for example, 50,55,75) of any expectation size and shape.For example, (for example can use within the scope of the invention the structure of different size and shapes, 50,55,75), there are the different transmission line structures that postpone still to have identical or identical in fact characteristic impedance for example to provide, for different grounded circuits path (, G1, G2).
Fig. 6-Fig. 8 shows the intermediate structure and the respective handling step that are used to form the each side according to the present invention.Particularly, Fig. 6 shows the sectional view of exemplary semiconductor structure, and it comprises substrate 100 and wiring layer 105 formed thereon.Substrate 100 can use traditional treatment technology to form, and can comprise for example having the silicon substrate that is formed at semiconductor device wherein (for example, grid, source/drain regions).Wiring layer 105 can use traditional handicraft to form, and can be made up of any applicable material, includes but not limited to high k value dielectric, low k value dielectric, ultralow k value dielectric etc.
Still with reference to figure 6, grounded circuit structure 110 is formed in wiring layer 105.Grounded circuit structure 75 can be made up of any applicable conductive material, includes but not limited to: copper, aluminium, alloy etc., and can use traditional handicraft to form.Grounded circuit structure 110 can be similar to above in shape with reference to figure 4 and the described grounded circuit structure 75 of Fig. 5, or can have different shapes.For example, grounded circuit structure 110 can comprise that grounded circuit rail part 115 (for example, being similar to grounded circuit rail 80) and comb section divide 120 (for example, being similar to comb 85).
Fig. 7 shows the structure of Fig. 6, has formed additional wiring layer 130,135 and 140 thereon.In wiring layer 140, be formed with grounded circuit structure 145, it can use the material similar to grounded circuit structure 110 and technique to form.Grounded circuit structure 145 can be similar to above in shape with reference to figure 4 and the described grounded circuit structure 55 of Fig. 5, or can have different shapes.For example, grounded circuit structure 145 can comprise that grounded circuit rail part 150 (for example, being similar to grounded circuit rail 60) and comb section divide 155 (for example, being similar to comb 65).
Fig. 8 shows the structure of Fig. 7, for example uses traditional material and technology to form other wiring layer 160 thereon.In addition, holding wire 165 is formed in wiring layer 160.Holding wire 165 can be similar to above with reference to figure 4 and the described holding wire 50 of Fig. 5, or can have different shapes.Holding wire 165 can be made up of any applicable electric conducting material, includes but not limited to: copper, aluminium, alloy etc., and can use traditional handicraft to form.
The feature (for example, 100,105,110,130,135,140,145,160,165) of Fig. 6-Fig. 8 can be used conventional art (such as standard rear end operation (BEOL) technique) to form.For example, these features can be used manufacturing process to form, manufacturing process includes but not limited to: photo etched mask and exposure, etching are (for example, reactive ion etching (RIE) etc.), metallization (for example, chemical vapor deposition (CVD) etc.) and planarization and polishing (for example, chemico-mechanical polishing (CMP) etc.).In addition, the supplementary features shown in Fig. 6-Fig. 8 can be used together with realization of the present invention.For example, barrier material can be used as liner, cap etc.In addition, can between any wiring layer, insert via layer.
In addition, wiring layer can have applicable thickness arbitrarily, and thickness can be relative to each other different.For example, wiring layer 105,130,135 can have the thickness of about 0.5 μ m to 0.6 μ m, and wiring layer 140 can be that about 3 μ m are thick, and wiring layer 160 can be that about 4 μ m are thick.But, the invention is not restricted to these values, but can utilize applicable thickness arbitrarily.In addition, the wiring layer number shown in the invention is not restricted to.But each side of the present invention can for example, be used together with the semiconductor device (, analogue device, digital device etc.) with arbitrary number wiring layer.
In addition, grounded circuit structure 110,145 and holding wire 165 can be any applicable size and dimensions.For example, and grounded circuit structure 110,145 (, G1, G2) is not limited to single-phase and answers wiring layer, but can across multiple wiring layers, (for example via layer, if present), hereinafter with reference Fig. 9-Figure 12 describes in detail.In addition, the invention is not restricted to two the grounded circuit structures 110,145 shown in Fig. 8.But, can use the grounded circuit structure 110,145 of arbitrary number to postpone for transmission line structure provides the difference of any desirable number.
In execution mode, can in the device area of substrate 100, provide at least one switch 170.Switch 170 can operate optionally arbitrary grounded circuit structure (for example, 110 or 145) is connected to ground, makes the grounded circuit structure (for example, 110 or 145) of ground connection become the grounded circuit path of holding wire 165.Switch 170 can comprise any applicable switching device, such as PIN diode, FET etc.In execution mode, switch 170 is arranged in the grounded circuit path of transmission line structure instead of in signal path, to avoid the signal attenuation in signal path.
Said method is used to the manufacture of integrated circuit (IC) chip.The integrated circuit (IC) chip obtaining can be distributed as nude film with undressed wafer form (, as the single wafer with multiple unpackaged chips) by producer, or distributes with packing forms.In the later case, chip is arranged in one chip encapsulation (such as having the plastic carrier that is attached to the lead-in wire on motherboard or other higher level carriers), or is arranged in multi-chip package (such as having or the ceramic monolith of the two in surface interconnection or buried interconnects).In any situation, chip is then integrated with other chips, discrete circuit element and/or other signal processors, using the intermediate products as (a) such as motherboard or (b) part of any in final products.Final products can be any products that comprises integrated circuit (IC) chip.
Fig. 9 and Figure 10 show the alternative transmission line structure of the each side according to the present invention.Particularly, Fig. 9 shows the transmission line structure that comprises holding wire 200, the first grounded circuit structure 205 (for example, G1) and the second grounded circuit structure 225 (for example, G2), and all these structures form according to above-described mode.The first grounded circuit structure 205 comprises single grounded circuit rail 210, and it can be similar to grounded circuit rail for example 60,80 etc. in material and manufacturer.The first grounded circuit structure 205 also comprises electric capacity comb 215, and it extends from grounded circuit rail 210, upwards extends through multiple wiring layer (not shown), and ends at holding wire 200 and be formed at the capacity cell 220 in identical wiring layer.
Still comprise single grounded circuit rail 230 with reference to figure 9, the second grounded circuit structures 225, it can be similar to grounded circuit rail 210.The second grounded circuit structure 225 also comprises electric capacity comb 235, and it extends from grounded circuit rail 230, upwards extends through multiple wiring layer (not shown), and ends at holding wire 200 and be formed at the capacity cell 240 in identical wiring layer.At least one switch (not shown) can be provided, and to be optionally placed in ground state by one in corresponding grounded circuit structure 205 and 225, and another is unsettled.
Figure 10 shows the cross-sectional view of Fig. 9 structure.The electric capacity of the first grounded circuit structure 205 is contributed mainly from element 220, is labeled as " C1 " in Figure 10.The electric capacity of the second grounded circuit structure 225 is contributed mainly from element 240, is labeled as " C2 " in Figure 10.The main inductance contributor of the first grounded circuit structure 205 is grounded circuit rails 210, is labeled as " L1 " in Figure 10.The main inductance contributor of the second grounded circuit structure 225 is grounded circuit rails 230, is labeled as " L2 " in Figure 10.
Figure 11 and Figure 12 show the alternative transmission line structure of the each side according to the present invention.Particularly, Figure 11 shows and (for example comprises holding wire 300, the first grounded circuit structure 305, the transmission line structure of G1) and the second grounded circuit structure 325 (for example, G2), all these structures can form according to above-described mode.The first grounded circuit structure 305 comprises single grounded circuit rail 310, and it can be similar to grounded circuit rail 205 (for example, in Fig. 9).The first grounded circuit structure 305 also comprises comb 315, and it extends from grounded circuit rail 310, upwards extends through multiple wiring layer (not shown), and ends at holding wire 300 and be formed at the capacity cell 320 in identical wiring layer.
Still with reference to Figure 11, the second grounded circuit structure 325 comprises two grounded circuit rails 330, and it can be similar to grounded circuit rail 310.Grounded circuit rail 330 is formed in identical wiring layer with holding wire 300, forms coplanar transmission.The second grounded circuit structure 325 does not comprise electric capacity comb.At least one switch (not shown) can be provided, and for being optionally placed in ground state by one in corresponding grounded circuit structure 305 and 325, and another is unsettled.
Figure 12 shows the sectional view of the structure of Figure 11.The electric capacity of the first grounded circuit structure 305 is contributed mainly from element 320, is labeled as " C1 " in Figure 12.The electric capacity of the second base loop structure 325 is contributed mainly from grounded circuit rail 330, is labeled as " C2 " in Figure 12.The main inductance contributor of the first grounded circuit structure 305 is grounded circuit rails 310, is labeled as " L1 " in Figure 10.The main inductance contributor of the second grounded circuit structure 325 is grounded circuit rails 330, is labeled as " L2 " in Figure 10.
Figure 13 and Figure 14 show the alternative transmission line structure of the each side according to the present invention.Particularly, Figure 13 shows the transmission line structure that comprises holding wire 400, the first grounded circuit structure 405 (for example G1) and the second grounded circuit structure 425 (for example G2), and all these structures can form according to above-described mode.The first grounded circuit structure 405 comprises two parallel grounded circuit rails 410, and it can be formed in identical wiring layer with holding wire 400.The first grounded circuit structure 405 also comprises comb 415, between the grounded circuit rail 410 in its wiring layer under holding wire 400, extends.
Still with reference to Figure 13, the second grounded circuit structure 425 comprises two parallel grounded circuit rails 430, and it is formed in identical wiring layer with holding wire 400.The second grounded circuit structure 425 also comprises comb 435, between the grounded circuit rail 430 in its wiring layer under holding wire 400, extends.At least one switch (not shown) can be provided, and for being optionally placed in ground state by one in corresponding grounded circuit structure 405 and 425, and another is unsettled.
Figure 14 shows the cross-sectional view of the structure of Figure 13.The electric capacity contribution of the first grounded circuit structure 405, mainly from comb 415, is labeled as " C1 " in Figure 14.The electric capacity contribution of the second grounded circuit structure 425, mainly from comb 435, is labeled as " C2 " in Figure 14.The main inductance contributor of the first grounded circuit structure 405 is grounded circuit rails 410, is labeled as " L1 " in Figure 14.The main inductance contributor of the second grounded circuit structure 425 is grounded circuit rails 430, is labeled as " L2 " in Figure 14.
In execution mode, the feature of the corresponding grounded circuit structure shown in Fig. 9-Figure 14 can form according to any applicable size and shape, and can for example, form according to any suitable spatial relationship with respect to holding wire (, 200,300,400).Especially, corresponding grounded circuit structure (for example, G1 and G2) feature can form like this, transmission line structure according to which grounded circuit structure (is for example postponed, G1 or G2) be grounded and difference, and no matter which grounded circuit structure is grounded, it is constant that transmission line structure characteristic impedance all keeps in fact.In execution mode, characteristic impedance is set to about 50ohm, but the invention is not restricted to this value, and any characteristic impedance can be used together with the present invention.
Up to the present described transmission line structure is each has comprised two switchable grounded circuit structures.But, the invention is not restricted to only have the transmission line structure of two changeable grounded circuit structures.For example, but more than two changeable grounded circuit structures such as (, three, four) can be used to transmission line structure that larger adjustability is provided.
In other execution mode, can be by forming multiple adjustable delaies, blocked impedance part along transmission line series connection, for transmission line provides additional adjustability.For example, Figure 15 shows the block diagram of the each side according to the present invention, and wherein transmission line 500 extends between two points 501,502.Transmission line 500 provides three corresponding parts 510,515,520 of adjustable delay, blocked impedance, and it can form with being similar to the structure of describing with reference to figure 1-Figure 14.
More specifically, Part I 510 can comprise such transmission line structure, and it has three and selects controlled length of delay t1, t2, t3, and relatively constant characteristic impedance Zo.Similarly, Part II can comprise such transmission line structure, and it has three and selects controlled length of delay t4, t5, t6, and relatively constant characteristic impedance Zo.Similarly, Part III 520 can comprise such transmission line structure, and it has three and selects controlled length of delay t7, t8, t9, and relatively constant characteristic impedance Zo.
According to an aspect of the present invention, part 510,515 and 520 is identical, makes t1=t4=t7, and t2=t5=t8, and t3=t6=t9.In such execution mode, transmission line 500 exists ten kinds of different delays to arrange, and every kind of arrangement has identical in fact characteristic impedance Zo.According to a further aspect in the invention, part 510,515 and 520 is all different, makes t1 ≠ t2 ≠ t3 ≠ t4 ≠ t5 ≠ t6 ≠ t7 ≠ t8 ≠ t9.In such execution mode, transmission line 500 exists 20 kinds of different delays to arrange, and every kind of arrangement has identical in fact characteristic impedance Zo.
Figure 16 is the flow chart of realizing the step of each side according to the present invention.Flow chart can represent high level block diagram of the present invention equivalently.In client-server relation, the step of flow chart can be by the computing equipment in ad hoc (self-organizing) network by server controls and execution, or it can utilize and is sent to the operation information of teller work station and moves on teller work station.And, the present invention can use the execution mode of devices at full hardware, completely software execution mode or comprise that the two execution mode of hardware and software element controls.In one embodiment, software element comprises firmware, resident software, microcode etc.
In addition, the present invention can be used or the addressable computer program control of computer-readable medium by computer, uses or connected code to provide by computer or any instruction execution system.For the object of this specification, computer can with or computer-readable medium can be comprise, any device of storage, communication, propagation or convey program, this program is used or is connected with it by instruction execution system, device or equipment.Medium can be electronics, magnetic, optical, electrical magnetic, infrared or semiconductor system (or device or equipment) or propagation medium.The example of computer-readable medium comprises semiconductor or solid-state memory, tape, movable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disc and CD.The current example of CD comprises compact disk-read-only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD.
More specifically, Figure 16 shows the flow chart of the control step of the method for drawing the delay for regulating transmission line structure.In step 610, the first grounded circuit structure of transmission line structure is electrically connected to earth potential.In execution mode, transmission line structure and grounded circuit structure can be similar to transmission line structure and the grounded circuit structure (for example G1) described with reference to figure 4-Figure 15 above.In execution mode, the switch being integrated in by operation in the semiconductor device region of transmission line structure creates connection.The operation of switch can be carried out according to any applicable mode, such as, computer control.As the result of step 610, the first grounded circuit structure is provided as the grounded circuit path of the holding wire of transmission line structure.
In step 620, the second grounded circuit structure and the earth potential electricity that are integrated in identical traffic line structure disconnect.The second grounded circuit structure can be similar to the grounded circuit structure (for example G2) of describing with reference to figure 4-Figure 15 above, the delay that makes transmission line structure is according to which grounded circuit grounding structure and difference, and no matter the characteristic impedance of which grounded circuit grounding structure transmission line structure all keeps in fact constant.In execution mode, the disconnection at step 620 place can be carried out with being connected simultaneously of step 610 place, or carried out in the different moment.In addition, the disconnection at step 620 place can be used the switch identical with the connection at step 610 place to carry out, or uses different switches to carry out.
In step 630, signal transmits on the holding wire of transmission line structure.In execution mode, signal transmission can be carried out according to any applicable mode.Due to the connection at step 610 place, the delay that transmission has will mainly be determined by the first grounded circuit structure.
In step 640, the first grounded circuit structure and earth potential disconnect, and the second grounded circuit structure is connected to earth potential.This can carry out according to the mode that is similar to step 610 and 620, replaces the second grounded circuit structure by the first grounded circuit structure, and vice versa.As the result of step 640, the second grounded circuit structure is provided as the grounded circuit path of the holding wire of transmission line structure; The first grounded circuit structure is unsettled simultaneously.
In step 650, signal transmits on the holding wire of transmission line structure.This can be according to carrying out with the similar mode of step 630.Due to step 640, the delay that transmission has will mainly be determined by the second grounded circuit structure.In execution mode, the delay at step 650 place is different from the delay at step 630 place; But the characteristic impedance of transmission line structure is identical in transmitting step 630 and 650.
Figure 17 for example shows the block diagram for the exemplary design flow process 900 of semiconducter IC logical design, emulation, test, layout and manufacture.Design cycle 900 comprises for the treatment of the process of project organization or equipment and mechanism, to generate the above and equivalently represented in the in logic and/or otherwise function of the project organization shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15 and/or equipment.The project organization that design cycle 900 is processed and/or generated can be coded in machine readable transmission or storage medium to comprise data and/or instruction, and these data and/or instruction generate the logic, structure, machinery of nextport hardware component NextPort, circuit, equipment or system or equivalently represented in function otherwise when execution in data handling system or while otherwise processing.Design cycle 900 can change according to the type of the expression designing.For example, for build the design cycle 900 of application-specific integrated circuit (ASIC) can be different from for the design cycle 900 of design standard assembly or with for by design exampleization to programmable array (for example by
inc. or
inc. the programmable gate array (PGA) providing or field programmable gate array (FPGA)) in design cycle 900.
Figure 17 shows multiple these type of project organizations, comprises In-put design structure 920, and it is preferably processed by design process 910.Project organization 920 can be the logical simulation project organization that is generated and processed by design process 910, to produce the logically equivalent functional representation of hardware device.Project organization 920 can also or alternatively can comprise data and/or program command, in the time processing these data and/or program command by design process 910, generates the functional representation of the physical structure of hardware device.No matter whether presentation function and/or structural design features, project organization 920 can use such as the Computer Aided Design (ECAD) of being realized by core developer/designer and generate.In the time being coded on machine-readable data transmission, gate array or storage medium, project organization 920 can be visited and be processed by the one or more hardware in design process 910 and/or software module, with emulation or otherwise represent functionally electronic building brick, circuit, electronics or logic module, device, equipment or the system shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15.Thus, project organization 920 can comprise file or other data structures, it comprises the mankind and/or machine-readable source code, Compiler Structure and computer-executable code structure, when by designing or when emulated data treatment system processes, the hardware logic design of its emulation functionally or otherwise indication circuit or other layers.This type of data structure can comprise and meeting and/or hardware description language (HDL) design entity or other data structures of compatible rudimentary HDL design language (such as Verilog and VHDL) and/or high-level design languages (such as C or C++).
Design process 910 preferably adopts and comprises for the hardware of comprehensive, translation or otherwise Treatment Design/emulation and/or software module to generate the net table 980 that can comprise the project organization such as project organization 920, is equivalent to the assembly shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15, circuit, equipment or logical construction on this design/copying.Net table 980 can comprise such as wiring, discreet component, gate, control circuit, I/O device, model etc. list through compiling or treated data structure otherwise, its describe with other elements be connected and integrated circuit (IC) design in circuit.Can carry out comprehensive network table 980 by iterative process, wherein according to the design specification of device and parameter by comprehensive net table 980 one or many.Identical with other project organization types described here, net table 980 can be recorded in machine-readable data storage media or be programmed in programmable gate array.Medium can be non-volatile memory medium, such as disk or CD drive, programmable gate array, compression-type flash memory or other flash memories.Additionally or alternatively, medium can be system or cache memory, spatial cache or electricity or light transmissive device and material, packet can be transmitted or intermediate storage thereon via the appropriate device of internet or other networkings.
Design process 910 can comprise for the treatment of the hardware and software module of multiple input data structure type that comprises net table 980.This type of type of data structure for example can reside in storehouse element 930, and for example can comprise, for given manufacturing technology (different technologies node, 32nm, 45nm, 90nm etc.) one group of common component, circuit and device, comprise that module, layout and symbol represent.Type of data structure can also comprise design specification 940, characterization data 950, verification msg 960, design rule 970 and test data file 985, and it can comprise input testing mode, output test result and other detecting informations.Design process 910 can also comprise for example standard mechanical design technology, and such as stress analysis, hot analysis, mechanical event simulation, operating procedure emulation, operating procedure such as casting, die casting and tube core are pressed formation etc.The those of ordinary skill of mechanical design field can be without departing from the scope and spirit of the present invention, understands the scope of the application of possible Machine Design instrument and design process 910.Design process 910 can also comprise the module for operative norm circuit design process (such as Time-Series analysis, checking, Design Rule Checking, placement and wiring operations etc.).
Design process 910 adopts and inclusive disjunction physical design tool (such as HDL compiler and simulation model member instrument), with some or all and any additional Machine Design or data (if can apply) in Treatment Design structure 920 and the supported data structure drawn, to generate the second project organization 990.Project organization 990 for example, resides in storage medium or programmable gate array for the data format of the exchange of the data of plant equipment and structure (, be stored as IGES, DXF, parametrization entity XT, JT, DRF or for storing or present the information of other any applicable forms of this type of mechanical design structure).Be similar to project organization 920, project organization 990 preferably includes one or more file, data structure or other computer code data or the instruction that reside on transmission or data storage medium, and when processed by ECAD system, generates the logic of the one or more execution modes of the present invention shown in Fig. 1-Fig. 5 and Fig. 8-Figure 15 or equivalent form in function otherwise.In one embodiment, project organization 990 can comprise that it is the device shown in analogous diagram 1-Figure 15 functionally through compiling executable HDL simulation model.
Project organization 990 for example can also adopt, for the data format of the topology data exchange of integrated circuit and/or symbol data form (be stored as GDSII (GDS2), GL1, OASIS, mapped file or for storing the information of any other applicable form of this type of design data structure).Project organization 990 can comprise for example following information: symbol data, mapped file, test data file, design content file, the data of manufacturing data, layout parameter, circuit, metal level, through hole, shape, connecting up by manufacturing process, and producer or other designer/developers are for the production of device or needed any other data of structure shown in the above and Fig. 1-Fig. 5 and Fig. 8-Figure 15.Project organization 990 can proceed to the stage 995 then, wherein for example, and project organization 990: proceed to flow, be published to manufacture, be published to mask chamber, be sent to another design office, send it back client etc.
Term, only for describing the object of specific implementations, is not intended to as restriction of the present invention as used herein.As used herein, singulative " one ", " one " and " being somebody's turn to do " are intended to also comprise plural form, unless context explicitly points out.It is also understood that, term " comprises " and/or " comprising ", in the time using in this manual, specify feature, entirety, step, operation, element and/or the assembly of stating, but do not get rid of the existence of one or more other features, entirety, step, operation, element, assembly and/or its combination or add.
The equivalent (if present) that in claims, corresponding structure, material, behavior and all devices or step add functional element is intended to comprise for carrying out as institute's specific requirement protection and any structure, material or the action combined function of other claimed elements.Specification of the present invention proposes for the purpose of illustration and description, and has more than in the present invention exhaustive or that be limited to disclosed form.Without departing from the scope and spirit of the present invention, multiple amendment and variant will become easily and see those of ordinary skill in the art.Select and described execution mode to explain best principle of the present invention and practical application, and making other those of ordinary skill of this area to understand the present invention for thering are the various execution modes that are suitable for the various amendments that particular desired uses.
Claims (29)
1. a transmission line structure, comprising:
Holding wire;
The first grounded circuit structure, it causes the first delay and the first characteristic impedance in transmission line structure; And
The second grounded circuit structure, it causes the second delay and the second characteristic impedance in described transmission line structure;
Wherein said the first delay and described second postpones different, and described the first characteristic impedance is identical in fact with described the second characteristic impedance,
Wherein, the first grounded circuit structure provides the inductance that is different from the second grounded circuit structure,
Wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are formed in semiconductor structure,
Wherein switching manipulation in order to respectively by a ground connection in described the first grounded circuit structure and described the second grounded circuit structure, and by unsettled another in described the second grounded circuit structure and described the first grounded circuit structure.
2. structure as claimed in claim 1, wherein:
Described holding wire is formed in the first wiring layer of described semiconductor structure,
Described the first grounded circuit structure is formed in the second wiring layer of described semiconductor structure, and
Described the second grounded circuit structure is formed in the 3rd layer of described semiconductor structure.
3. structure as claimed in claim 2, wherein:
Described the first wiring layer is different from described the second wiring layer, and
The part of described the first grounded circuit structure is also formed in described the first wiring layer.
4. structure as claimed in claim 3, wherein:
Described holding wire is formed in the first wiring layer of described semiconductor structure,
Described the first grounded circuit structure is formed in described the first wiring layer, and
The part of described the second grounded circuit structure is formed in described first wiring layer and the second wiring layer of described semiconductor structure.
5. structure as claimed in claim 1, wherein:
Described the first grounded circuit structure comprises the first grounded circuit rail and the first capacitance structure, and
Described the second grounded circuit structure comprises the second grounded circuit rail and the second capacitance structure.
6. structure as claimed in claim 5, wherein:
Described the first grounded circuit rail than described the second grounded circuit rail further from described holding wire, and
Described the first capacitance structure is than the more close described holding wire of described the second capacitance structure.
7. structure as claimed in claim 1, it is the delay of signal in described holding wire that wherein said the first delay and described second postpones.
8. a semiconductor structure, comprising:
Holding wire,
The first grounded circuit structure, it comprises the first grounded circuit rail and the first capacitance structure; And
The second grounded circuit structure, it comprises the second grounded circuit rail and the second capacitance structure,
Wherein said the first grounded circuit rail than described the second grounded circuit rail further from described holding wire,
Described the first capacitance structure is than the more close described holding wire of described the second capacitance structure, and
The ground connection of described holding wire can optionally be switched between described the first grounded circuit rail and described the second grounded circuit rail,
Wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are included in transmission line structure, and,
Described the first grounded circuit structure creates the first delay and the first characteristic impedance in described transmission line structure,
Described the second grounded circuit Structure Creating and described first postpones the second different delays, and the second characteristic impedance equating in fact with described the first characteristic impedance.
9. structure as claimed in claim 8, also comprises the 3rd grounded circuit structure, postpones and the 3rd characteristic impedance for creating the 3rd,
The wherein said the 3rd postpones to postpone to be different in essence with described the first delay and described second, and described the 3rd characteristic impedance equates in fact with described the first characteristic impedance and described the second characteristic impedance.
10. structure as claimed in claim 8, wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are formed in the wiring layer on substrate.
Manufacture the method for transmission line structure, comprising for 11. 1 kinds:
Form the holding wire of described transmission line structure;
Form the first grounded circuit structure, described the first grounded circuit structure causes the first delay and the first characteristic impedance in described transmission line structure; And
Form the second grounded circuit structure, described the second grounded circuit structure causes the second delay and the second characteristic impedance in described transmission line structure;
Wherein said the first delay and described second postpones different, and described the first characteristic impedance is identical in fact with described the second characteristic impedance,
Wherein, the first grounded circuit structure provides the inductance that is different from the second grounded circuit structure,
Wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are formed in semiconductor structure,
Wherein switching manipulation in order to respectively by a ground connection in described the first grounded circuit structure and described the second grounded circuit structure, and by unsettled another in described the second grounded circuit structure and described the first grounded circuit structure.
12. methods as claimed in claim 11, wherein:
Described holding wire is formed in the first wiring layer of described semiconductor structure,
Described the first grounded circuit structure is formed in the second wiring layer of described semiconductor structure, and
Described the second grounded circuit structure is formed in the 3rd layer of described semiconductor structure.
13. methods as claimed in claim 12, wherein:
Described the first wiring layer is different from described the second wiring layer, and
The part of described the first grounded circuit structure is also formed in described the first wiring layer.
14. methods as claimed in claim 13, wherein:
Described holding wire is formed in the first wiring layer of described semiconductor structure,
Described the first grounded circuit structure is formed in described the first wiring layer, and
The part of described the second grounded circuit structure is formed in described first wiring layer and the second wiring layer of described semiconductor structure.
15. methods as claimed in claim 11, wherein:
Described the first grounded circuit structure comprises the first grounded circuit rail and the first capacitance structure, and
Described the second grounded circuit structure comprises the second grounded circuit rail and the second capacitance structure.
16. methods as claimed in claim 15, wherein:
Described the first grounded circuit rail than described the second grounded circuit rail further from described holding wire, and
Described the first capacitance structure is than the more close described holding wire of described the second capacitance structure.
17. methods as claimed in claim 11, it is the delay of signal in described holding wire that wherein said the first delay and described second postpones.
18. methods as claimed in claim 11, wherein said the first delay is 16% with the described second difference postponing.
19. methods as claimed in claim 18, the difference of wherein said the first characteristic impedance and described the second characteristic impedance is less than 5%.
20. methods as claimed in claim 19, wherein said the first characteristic impedance is 50ohm.
Manufacture the method for semiconductor structure, comprising for 21. 1 kinds:
Form holding wire,
Form the first grounded circuit structure, it comprises the first grounded circuit rail and the first capacitance structure; And
Form the second grounded circuit structure, it comprises the second grounded circuit rail and the second capacitance structure,
Wherein said the first grounded circuit rail than described the second grounded circuit rail further from described holding wire,
Described the first capacitance structure is than the more close described holding wire of described the second capacitance structure, and
The ground connection of described holding wire is optionally switched between described the first grounded circuit rail and described the second grounded circuit rail,
Wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are included in transmission line structure, and,
Described the first grounded circuit structure creates the first delay and the first characteristic impedance in described transmission line structure,
Described the second grounded circuit Structure Creating and described first postpones the second different delays, and the second characteristic impedance equating in fact with described the first characteristic impedance.
22. methods as claimed in claim 21, also comprise and form the 3rd grounded circuit structure, and described the 3rd grounded circuit Structure Creating the 3rd postpones and the 3rd characteristic impedance,
The wherein said the 3rd postpones to postpone to be different in essence with described the first delay and described second, and described the 3rd characteristic impedance equates in fact with described the first characteristic impedance and described the second characteristic impedance.
23. methods as claimed in claim 21, wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are formed in the wiring layer on substrate.
The method of 24. 1 kinds of signal transmissions in transmission line structure, comprising:
By the first grounded circuit grounding structure, described the first grounded circuit structure causes the first delay and the first characteristic impedance in described transmission line structure;
By unsettled the second grounded circuit structure, described the second grounded circuit structure causes postponing the second different delays from described first, and second characteristic impedance identical in fact with described the first characteristic impedance, wherein, the first grounded circuit structure provides the inductance that is different from the second grounded circuit structure; And
Signal transmission on the holding wire of described transmission line structure,
Wherein said holding wire, described the first grounded circuit structure and described the second grounded circuit structure are formed in semiconductor structure.
25. methods as claimed in claim 24, wherein said ground connection and described unsettled at least one switch comprising in the described semiconductor structure of operation.
26. methods as claimed in claim 24, also comprise:
By unsettled described the first grounded circuit structure;
By described the second grounded circuit grounding structure; And
On described holding wire, transmit another signal.
27. methods as claimed in claim 24, wherein:
Described first postpones to be at least 16% with the described second difference postponing, and
The difference of described the first characteristic impedance and described the second characteristic impedance is less than 5%.
28. 1 kinds operate the method for transmission line structure, comprising:
Between the second grounded circuit structure, switch transmission line structure in (i) first grounded circuit structure and (ii), wherein said the first grounded circuit structure causes the first delay and the first characteristic impedance in described transmission line structure, and described in described the second grounded circuit Structure Creating, second of transmission line structure postpones and the second characteristic impedance
Wherein said first postpones to postpone to be different in essence with described second, and described the first characteristic impedance equates in fact with described the second characteristic impedance, and wherein, the first grounded circuit structure provides the inductance that is different from the second grounded circuit structure,
Wherein said the first grounded circuit structure and described the second grounded circuit structure are formed in the wiring layer of single semiconductor structure.
29. methods as claimed in claim 28, wherein said switching is carried out by least one in computer program and computing equipment.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/144,684 | 2008-06-24 | ||
| US12/144,682 | 2008-06-24 | ||
| US12/144,684 US8193878B2 (en) | 2008-06-24 | 2008-06-24 | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
| US12/144,682 US8138857B2 (en) | 2008-06-24 | 2008-06-24 | Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
| PCT/US2009/047598 WO2010008742A1 (en) | 2008-06-24 | 2009-06-17 | Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102027633A CN102027633A (en) | 2011-04-20 |
| CN102027633B true CN102027633B (en) | 2014-11-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980117714.8A Active CN102027633B (en) | 2008-06-24 | 2009-06-17 | Design structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR20110031277A (en) |
| CN (1) | CN102027633B (en) |
| MX (1) | MX2010013267A (en) |
| WO (1) | WO2010008742A1 (en) |
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| US8988166B2 (en) | 2011-10-02 | 2015-03-24 | International Business Machines Corporation | Structure and compact modeling of variable transmission lines |
| US9082624B2 (en) * | 2013-01-02 | 2015-07-14 | International Business Machines Corporation | Signal path of a multiple-patterned semiconductor device |
| US9171798B2 (en) * | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
| CN105025663B (en) * | 2014-04-30 | 2019-05-10 | 日月光半导体制造股份有限公司 | Encapsulating structure and its manufacturing method with circuit type electronic component |
| US9559663B2 (en) * | 2015-06-22 | 2017-01-31 | Tektronix, Inc. | Electronically variable analog delay line |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723908A (en) * | 1993-03-11 | 1998-03-03 | Kabushiki Kaisha Toshiba | Multilayer wiring structure |
| US6816031B1 (en) * | 2001-12-04 | 2004-11-09 | Formfactor, Inc. | Adjustable delay transmission line |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4706177A (en) * | 1985-11-14 | 1987-11-10 | Elliot Josephson | DC-AC inverter with overload driving capability |
| JP2000067595A (en) * | 1998-06-09 | 2000-03-03 | Mitsubishi Electric Corp | Semiconductor memory |
| US6674174B2 (en) * | 2001-11-13 | 2004-01-06 | Skyworks Solutions, Inc. | Controlled impedance transmission lines in a redistribution layer |
| US7332983B2 (en) * | 2005-10-31 | 2008-02-19 | Hewlett-Packard Development Company, L.P. | Tunable delay line using selectively connected grounding means |
| US7689962B2 (en) * | 2006-02-08 | 2010-03-30 | Roberto Suaya | Extracting high frequency impedance in a circuit design using an electronic design automation tool |
-
2009
- 2009-06-17 KR KR1020107026828A patent/KR20110031277A/en not_active Application Discontinuation
- 2009-06-17 MX MX2010013267A patent/MX2010013267A/en active IP Right Grant
- 2009-06-17 CN CN200980117714.8A patent/CN102027633B/en active Active
- 2009-06-17 WO PCT/US2009/047598 patent/WO2010008742A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5723908A (en) * | 1993-03-11 | 1998-03-03 | Kabushiki Kaisha Toshiba | Multilayer wiring structure |
| US6816031B1 (en) * | 2001-12-04 | 2004-11-09 | Formfactor, Inc. | Adjustable delay transmission line |
Also Published As
| Publication number | Publication date |
|---|---|
| MX2010013267A (en) | 2011-02-25 |
| KR20110031277A (en) | 2011-03-25 |
| WO2010008742A1 (en) | 2010-01-21 |
| CN102027633A (en) | 2011-04-20 |
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