CN102024752B - Method for improving chip cutting - Google Patents
Method for improving chip cutting Download PDFInfo
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- CN102024752B CN102024752B CN 200910195970 CN200910195970A CN102024752B CN 102024752 B CN102024752 B CN 102024752B CN 200910195970 CN200910195970 CN 200910195970 CN 200910195970 A CN200910195970 A CN 200910195970A CN 102024752 B CN102024752 B CN 102024752B
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- chip
- chip cutting
- cutting technique
- weld pad
- layer
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Abstract
The invention discloses a method for improving a chip cutting process. The method comprises the following steps of: coating photoresist on a passivation layer on the surface of a chip to be cut; etching the passivation layer on the surface of the chip to expose the surface of a solder pad, and peeling the photoresist; and oxidizing an exposed metal layer to produce a metal oxide layer. The method also comprises the steps of: performing an electric acceptance test on the chip; checking the appearance of the chip; and cutting the chip. According to the method of the invention, the cutting of the chip is improved, thus the pollution of silicon dust on the solder pad, especially pollution on a surface Al layer is reduced, and the galvanic effect is inhibited.
Description
Technical field
The present invention relates to a kind of integrated circuit (IC) chip cutting method, particularly a kind of chip cutting method that reduces the pollution of AlCu weld pad.
Background technology
The cutting of chip (Die) is the very important technique of semiconductor industry always.Semiconductor wafer (wafer) need to be divided into several circuit small pieces, namely chip after having gone through complicated manufacturing process.If can't keep the rate of good quality rate or because chip separation method affect the original characteristic of chip in the stage that chip separates, also or the speed of cutting cause excessively slowly high cost, all can cause quite the production of whole chip to seriously influence.
Fig. 1 shows the flow process of traditional die cutting.In step 101, cover the figuratum photoresist of one deck tool at chip surface, the passivation layer that is positioned at the chip outmost surface is carried out etching.In step 102, make up with photoresist liquid and photoresist is peeled off and decomposed.In step 103, carry out electrical Acceptance Test (WAT), mainly the electrical characteristic of test chip, general element characteristic go bad on measurement circuit, such as gate oxide dielectric puncture voltage (BVGO), P-N junction leakage etc.In step 104, carry out visual examination, the defective of foreign substance and cut on the degree of conformity of the pattern on the detection chip and the described pattern.In step 105, carry out chip cutting, can use blade cutting.
In the process of aforesaid chip cutting, cutting operation can produce very thin silica soot, and these silica soot can precipitate or be splashed on the chip and cover electrode on weld pad (Pad) (being generally the AlCu weld pad) or the chip.Along with dwindling of integrated circuit, the sensitiveness increase that reduces to cause the butt welding pad from pollution of incident weld pad size, weld pad pollutes may cause relatively poor weld pad tensile strength and relatively poor bond strength uniformity.In present technique, usually adopt cooling water and clean water to wash the silica soot that removes on the weld pad, but this developing result and bad.This is because chip needs the long-time water that exposes to annotate in the cutting, can make between AlCu composition in the weld pad and the water and react, cause AlCu weld pad surface to be corroded, cause cavitation, be Jafani effect (Galvanic effect), and residual silica soot can be aggravated this Jafani effect.The cavity appears in the surface at weld pad, and is distributed with silica soot around the hole.The Jafani effect of silica soot aggravation, shown in following chemical formula,
Si+OH
-→SiO
3 2-+2H
2O+4e
-→H
2SiO
3orSiO
2.H
2O
H
2The appearance of O has formed a kind of high viscosity jelly, and this jelly will stick on the surface of weld pad, is difficult to be cleaned.The equation of reaction of formation thing is as follows:
Other SiO
3 2-Also can form the Al-Si-O compound according to following reaction equation and Al reaction, such as Al
2(SiO
3)
3:
Si+OH
-→SiO
3 2-+2H
2O+4e
-
Al→Al
3++3e
SiO
3 2-+Al
3+→Al
2(SiO
3)
3
Jafani effect has brought erosion effect to AlCu weld pad surface, and silica soot has been aggravated this effect.The high viscosity jelly that reaction generates sticks to the weld pad surface to be difficult to be rinsed, and therefore the characteristic of chip is impacted, and can cause chip failure when serious.
Fig. 2 A shows the profile that splashes weld pad is corroded of silica soot.Fig. 2 B shows the TEM photo on the weld pad surface after silica soot is splashed erosion.Shown in Fig. 2 A, weld pad down is respectively Al layer 201, TaN layer 202 and copper wiring layer 203 from outer surface successively.By transmission electron microscope (TEM) the weld pad section that is subject to the silica soot erosion is observed, find that silica soot only can corrode Al layer 201 usually, form the defective (such as pit) 204 that corrodes, and usually can not corrode following TaN layer 202 and copper wiring layer 203.
Therefore, need a kind of improved chip cutting method, to reduce silica soot to the pollution, the particularly pollution of effects on surface Al layer of weld pad, suppress Jafani effect, thereby improve the Quality and yield of semiconductor device.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to improve the cutting method of chip, to reduce silica soot to the pollution of weld pad, the particularly pollution of effects on surface Al layer, suppress Jafani effect, the present invention proposes a kind of method of improving chip cutting technique, described method comprises the steps: to apply photoresist at the passivation layer of chip surface to be cut, carries out exposure imaging; The passivation layer on etched wafer surface exposes the weld pad surface, stripping photoresist; The metal level that exposes is carried out oxidation, generate metal oxide layer.Described method also comprises carries out electrical Acceptance Test to chip; The chip outward appearance is checked; And the step of carrying out chip cutting.
According to an aspect of the present invention, described metal level is Al, and described metal oxide layer is Al
2O
3The thickness of described metal oxide layer preferably is about 8～9 dusts less than 80 dusts.
According to improvement chip cutting method of the present invention, reduced the pollution of silica soot to weld pad, suppressed Jafani effect, improved the Quality and yield of semiconductor device.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the process chart of traditional die cutting.
Fig. 2 A shows the profile that splashes weld pad is corroded of silica soot, and Fig. 2 B shows the TEM photo on the weld pad surface after silica soot is splashed erosion.
Fig. 3 is the process chart according to chip cutting of the present invention.
Fig. 4 A and Fig. 4 B are without Al
2O
3Chip after the cutting of protective layer with Al is arranged
2O
3Chip surface photo contrast after the cutting of protective layer.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention reduces pollution to weld pad by the improvement chip cutting method in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
With reference to Fig. 3, illustrate according to chip cutting of the present invention and make flow process.
After wafer fabrication was finished, the surface of wafer can cover one deck passivation layer to prevent from being subject to pollution and the erosion of external environment.Therefore before carrying out the method that weld pad is processed of the present invention, need at first open the passivation layer that covers the weld pad surface, in order to expose the metal surface of weld pad.Here can open passivation layer by the method for etching passivation layer.In step 301, cover the figuratum photoresist of one deck tool at chip surface, carry out exposure imaging.In step 302, the passivation layer of wafer surface is carried out etching, expose the Al layer on weld pad surface, then make up with photoresist liquid and photoresist is peeled off and decomposed.In step 303, adopt pure oxygen that chip surface is processed, so that the Al layer is carried out oxidation, generate one deck Al
2O
3Protective layer.Described process of surface treatment adopts is that oxidation mechanism in the cineration technics carries out oxidation reaction to the Al layer.Process conditions are: discharge pressure is 500-800mtorr, and discharge frequency is 2500W, and temperature is 235-285 ℃, and gas flow is 5000-15000sccm, and be 60-120s discharge time.Preferably, discharge pressure is 650mtorr, and discharge frequency is 2500W, and temperature is 250 ℃, and gas flow is 9500sccm, and be 60s discharge time.After the pure oxygen processing procedure, generate the Al that thickness is about 8～9 dusts
2O
3Protective layer.In step 304, carry out electrical Acceptance Test, mainly the electrical characteristic of test chip, general element characteristic go bad on measurement circuit, such as gate oxide dielectric layer puncture voltage, P-N junction leakage etc.In step 305, carry out visual examination, on the degree of conformity of the pattern on the detection chip and the described pattern such as the defective of foreign substance and cut.In step 306, carry out chip cutting, can use blade cutting.
Owing to pass through the as mentioned above Al of technique formation
2O
3Protective layer thickness is preferably 8～9 dusts, as long as but satisfy thickness less than 80 dusts, because this thickness can not affect the effect of wire-bonded (wirebonding) technique afterwards.The Al on weld pad surface
2O
3Protective layer can stop Si to the particularly erosion of surface A l layer of weld pad, has reduced empty formation, thereby has protected weld pad, has improved the rate of finished products of semiconductor device.
Fig. 4 A and 4B show without Al
2O
3Chip surface figure after the cutting of protective layer with Al is arranged
2O
3The contrast of chip surface figure after the cutting of protective layer.Shown in Fig. 4 A, without the chip that peroxide is processed, through 28 hours cutting, 47 weld pads had 19 places to be etched.Circle among the figure has marked the weld pad that is etched.And the chip after oxygen is processed, shown in Fig. 4 B, through 28 hours cutting, 47 weld pads only had 3 places to be etched.This shows, through the Al that generates after the oxidation processes of the present invention
2O
3Layer has been protected weld pad effectively, thereby has suppressed Jafani effect.
In addition, also to without Al
2O
3Chip after the cutting of protective layer with Al is arranged
2O
3Chip after the cutting of protective layer has carried out reliability testing.Detect through fail-safe analysis, the reliability of the chip after the chip after the process oxidation processes of the present invention and not oxidised are processed is almost without any difference.Thereby as can be known, can't any impact be arranged to other operating characteristic of semiconductor device according to oxidation processes of the present invention.
Method of the present invention is not limited to that the Al layer is carried out oxidation processes and forms Al
2O
3Protective layer.Other metal materials beyond Al also can be suitable for the present invention as in the situation of bonding pad materials.
The semiconductor device that has oxide protective layer according to the weld pad surface of aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).For example be memory circuitry according to IC of the present invention, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, such as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio frequency (RF) device or any other circuit devcies.
IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera.
In sum, only be preferred embodiment of the present invention, be not the present invention is done any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art are not breaking away from the technical solution of the present invention scope situation, all can utilize the method for above-mentioned announcement and technology contents that technical solution of the present invention is made possible change and modification, or be revised as the embodiment that is equal to of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. method of improving chip cutting technique, described method comprises the steps:
Passivation layer at chip surface to be cut applies photoresist, carries out exposure imaging;
The passivation layer on etched wafer surface exposes the weld pad surface, stripping photoresist;
Adopt pure oxygen that the metal level that exposes is carried out oxidation, generate metal oxide layer, to reduce silica soot to the pollution of weld pad, suppress Jafani effect;
Chip is carried out electrical Acceptance Test;
The chip outward appearance is checked;
Carry out chip cutting.
2. the method for improvement chip cutting technique as claimed in claim 1, described metal level is Al, described metal oxide layer is Al
2O
3
3. the method for improvement chip cutting technique as claimed in claim 1, the oxidation processes that wherein said metal level carries out adopts cineration technics.
4. the method for improvement chip cutting technique as claimed in claim 3, the discharge pressure of wherein said cineration technics is 500-800mtorr, and discharge frequency is 2500W, and temperature is 235-285 ℃, and gas flow is 5000-15000sccm, be 60-120s discharge time.
5. the method for improvement chip cutting technique as claimed in claim 4, the discharge pressure of wherein said cineration technics is 650mtorr, and discharge frequency is 2500W, and temperature is 250 ℃, and gas flow is 9500sccm, be 60s discharge time.
6. the method for improvement chip cutting technique as claimed in claim 1, the thickness of wherein said metal oxide layer is 8 ~ 9 dusts.
7. the method for improvement chip cutting technique as claimed in claim 1, the thickness of wherein said metal oxide layer is less than 80 dusts.
8. integrated circuit that comprises the semiconductor device of making by the method for claim 1, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and radio circuit.
9. electronic equipment that comprises the semiconductor device of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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|---|---|---|---|
| CN 200910195970 CN102024752B (en) | 2009-09-17 | 2009-09-17 | Method for improving chip cutting |
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|---|---|---|---|
| CN 200910195970 CN102024752B (en) | 2009-09-17 | 2009-09-17 | Method for improving chip cutting |
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| CN102024752A CN102024752A (en) | 2011-04-20 |
| CN102024752B true CN102024752B (en) | 2013-02-20 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137567B (en) * | 2011-11-30 | 2016-05-25 | 和舰科技(苏州)有限公司 | A kind of crystal circle structure and layout design method that alleviates wafer cutting stress rupture |
| CN102637580B (en) * | 2012-03-31 | 2014-09-17 | 上海华力微电子有限公司 | Method for preventing aluminium pad from being corroded |
| CN103594335B (en) * | 2013-11-21 | 2016-04-27 | 中国电子科技集团公司第四十一研究所 | A kind of cutting-up method of capacity plate antenna |
| CN103928360A (en) * | 2014-04-11 | 2014-07-16 | 武汉新芯集成电路制造有限公司 | Technology for improving performance of welding gasket |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375871A (en) * | 2001-03-01 | 2002-10-23 | 株式会社东芝 | Semiconductor device and mfg. method for same |
| CN1476072A (en) * | 2002-08-12 | 2004-02-18 | ������������ʽ���� | Semiconductor device |
| JP2006165018A (en) * | 2004-12-02 | 2006-06-22 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1375871A (en) * | 2001-03-01 | 2002-10-23 | 株式会社东芝 | Semiconductor device and mfg. method for same |
| CN1476072A (en) * | 2002-08-12 | 2004-02-18 | ������������ʽ���� | Semiconductor device |
| JP2006165018A (en) * | 2004-12-02 | 2006-06-22 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
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| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130110 |
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Effective date of registration: 20130110 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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