CN100527403C - Wafer metal lead wire and its manufacture method - Google Patents
Wafer metal lead wire and its manufacture method Download PDFInfo
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- CN100527403C CN100527403C CN 200610148089 CN200610148089A CN100527403C CN 100527403 C CN100527403 C CN 100527403C CN 200610148089 CN200610148089 CN 200610148089 CN 200610148089 A CN200610148089 A CN 200610148089A CN 100527403 C CN100527403 C CN 100527403C
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- lead wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The invention relates to a wafer metal lead wire and a making method thereof. The present wafer metal lead wire is subject to defects generated in the wafer which causes the lead wire short circuit or has hidden trouble of short circuit in process of making. The wafer metal lead wire of the invention is arranged on the wafer, which comprises bottom-up in sequence a connection layer, a metal layer, a second protection layer and a first protection layer; wherein, the second protection layer is denser than the first protection layer; after the metal lead wire is generated, photoresist is coated on the first protection layer and lithography as well as development are carried out; then the metal lead wire of preset shape is formed through etching. By adopting the invention, the defects which causes the metal lead wire short circuit or has the hidden trouble of short circuit generated in the process of making the metal lead wire can be effectively avoided, which greatly increases rate of good product of the wafer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of wafer metal lead wire and preparation method thereof.
Background technology
In semiconductor fabrication; when after generating complicated integrated circuit pattern on the wafer; need through encapsulation to form the device that can directly use; encapsulation is except that the use shell protects naked crystalline substance; the more important thing is the metal lead wire that formation can directly be connected with other devices, this metal lead wire is arranged on the wafer, and it comprises articulamentum, metal level, protective layer from bottom to up successively; usually this articulamentum and protective layer are titanium nitride, and metal level is an aluminium copper.The making step of this metal lead wire is a titanium nitride for the method for at first using chemical vapour deposition (CVD) generates articulamentum on wafer substrates; using the method for metal sputtering to generate metal level then on articulamentum is aluminium copper; then using the method for chemical vapour deposition (CVD) to generate protective layer on wafer substrates is titanium nitride; on protective layer, apply photoresist afterwards; carry out photoetching again to form metal electrode; and photoetching needs to use developer solution and photoresist to react so that electrode pattern develops after generating mask graph on the mask.
But; because the protective layer of the superiors is that the compactness of titanium nitride is relatively poor; there are a lot of lattice crackles on its surface; when using developer solution and photoresist to react so that metal electrode is developed out; developer solution is except that reacting with the photoresist that is exposed the zone; the lattice crack and the metal level that also pass on the protective layer react; generate subsequent etching and all be difficult to the defective removed; when this defective is just between overlap joint two metal lead wires, can make device become defective products; and when this fault location regional between two metal electrodes; easily cause metal electrode electric leakage or puncture in follow-up test or the use, so exist great potential safety hazard.
Summary of the invention
The object of the present invention is to provide a kind of wafer metal lead wire, generate the defective that causes the metal lead wire short circuit or have short circuit hidden danger in the time of can avoiding making metal electrode by wafer metal lead wire of the present invention.
The object of the present invention is achieved like this: a kind of wafer metal lead wire; it is arranged on the wafer; it comprises an articulamentum, a metal level and one first protective layer from bottom to up successively; this metal lead wire comprises that also one is arranged on second protective layer between the metal level and first protective layer; wherein; this second protective layer is a titanium layer, and this first protective layer is a titanium nitride layer.
In above-mentioned wafer metal lead wire, this articulamentum is a titanium nitride layer.
In above-mentioned wafer metal lead wire, this metal level is an aluminum-copper alloy layer.
In above-mentioned wafer metal lead wire, this second protective layer (titanium layer) thickness is 150 dusts.
The present invention also provides a kind of wafer metal lead wire manufacture method; it comprises at first generate articulamentum, metal level, first protective layer successively on wafer; on this first protective layer, apply photoresist then and carry out photoetching and development; then form the metal lead wire of preset shape by etching; wherein; on wafer substrates, generate successively in articulamentum, metal level, the first protective layer step; also be included in and generate second protective layer between the metal level and first protective layer; wherein; this second protective layer is a titanium layer, and this first protective layer is a titanium nitride layer.
In above-mentioned wafer metal lead wire manufacture method, this articulamentum is a titanium nitride layer.
In above-mentioned wafer metal lead wire manufacture method, this metal level is an aluminum-copper alloy layer.
In above-mentioned wafer metal lead wire manufacture method, this second protective layer (titanium layer) thickness is 150 dusts.
Have only layer protective layer to compare with wafer metal electrode in the prior art; wafer metal electrode of the present invention is because of adding second protective layer of one deck than the first protective layer densification between first protective layer and metal level; avoided in wafer metal manufacturing process developer solution to pass protective layer and generated the defective that causes the metal lead wire short circuit or have short circuit hidden danger, greatly improved the yields of wafer with metal reaction.
Description of drawings
Wafer metal lead wire of the present invention and preparation method thereof is provided by following embodiment and accompanying drawing.
Fig. 1 is the cutaway view of wafer metal lead wire of the present invention;
Fig. 2 is a wafer metal lead wire manufacture method schematic flow sheet of the present invention.
Embodiment
Below will be described in further detail wafer metal lead wire of the present invention and preparation method thereof.
Referring to Fig. 1, wafer metal lead wire 1 of the present invention is arranged on the wafer (not shown), and it comprises articulamentum 10, metal level 11, second protective layer 12 and first protective layer 13 from bottom to up successively.
In the present embodiment, articulamentum 10 is a titanium nitride layer, and its thickness is 375 dusts; Metal level 11 is an aluminum-copper alloy layer, and its thickness is 9000 dusts; Second protective layer 12 is a titanium layer, and its thickness is 150 dusts, and first protective layer 13 is a titanium nitride layer, and its thickness is 250 dusts.
Referring to Fig. 2, wafer metal lead wire manufacture method of the present invention is at first carried out step S20, generates articulamentum, metal level, second protective layer and first protective layer on wafer successively, and wherein, second protective layer is than the first protective layer densification.In the present embodiment, this articulamentum, metal level, second protective layer and first protective layer are respectively titanium nitride layer, aluminum-copper alloy layer, titanium layer and titanium nitride layer, and its thickness is respectively 375 dusts, 9000 dusts, 150 dusts and 250 dusts.Carry out step S21 then.
In step S21, on this first protective layer, apply photoresist and carry out photoetching and development.Carry out step S22 then.
In step S22, form the metal lead wire of preset shape by etching.
In sum; wafer metal lead wire of the present invention and preparation method thereof can be avoided in wafer metal manufacturing process developer solution to pass protective layer and generate the defective that causes the metal lead wire short circuit or have short circuit hidden danger with metal reaction, has greatly improved the yields of wafer.
Claims (8)
1, a kind of wafer metal lead wire; be arranged on the wafer; it comprises an articulamentum, a metal level and one first protective layer from bottom to up successively; it is characterized in that; this metal lead wire comprises that also one is arranged on second protective layer between the metal level and first protective layer; wherein, this second protective layer is a titanium layer, and this first protective layer is a titanium nitride layer.
2, wafer metal lead wire as claimed in claim 1 is characterized in that, this articulamentum is a titanium nitride layer.
3, wafer metal lead wire as claimed in claim 1 is characterized in that, this metal level is an aluminum-copper alloy layer.
4, wafer metal lead wire as claimed in claim 1 is characterized in that, this titanium layer thickness is 150 dusts.
5, a kind of wafer metal lead wire manufacture method; it comprises at first generate articulamentum, metal level, first protective layer successively on wafer; on this first protective layer, apply photoresist then and carry out photoetching and development; then form the metal lead wire of preset shape by etching; it is characterized in that; on wafer substrates, generate successively in articulamentum, metal level, the first protective layer step; also be included in and generate second protective layer between the metal level and first protective layer; wherein; this second protective layer is a titanium layer, and this first protective layer is a titanium nitride layer.
6, wafer metal lead wire manufacture method as claimed in claim 5 is characterized in that, this articulamentum is a titanium nitride layer.
7, wafer metal lead wire manufacture method as claimed in claim 5 is characterized in that, this metal level is an aluminum-copper alloy layer.
8, wafer metal lead wire manufacture method as claimed in claim 5 is characterized in that, this titanium layer thickness is 150 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610148089 CN100527403C (en) | 2006-12-27 | 2006-12-27 | Wafer metal lead wire and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610148089 CN100527403C (en) | 2006-12-27 | 2006-12-27 | Wafer metal lead wire and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101211875A CN101211875A (en) | 2008-07-02 |
| CN100527403C true CN100527403C (en) | 2009-08-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610148089 Active CN100527403C (en) | 2006-12-27 | 2006-12-27 | Wafer metal lead wire and its manufacture method |
Country Status (1)
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| CN (1) | CN100527403C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103426750B (en) * | 2012-05-24 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | Metal wet etching method without metal wire cut problem |
| CN108417528B (en) * | 2018-02-05 | 2021-06-15 | 武汉新芯集成电路制造有限公司 | Method for improving residues on aluminum pad |
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- 2006-12-27 CN CN 200610148089 patent/CN100527403C/en active Active
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| CN101211875A (en) | 2008-07-02 |
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| C14 | Grant of patent or utility model | ||
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Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20111118 Address after: 201203 No. 18 Zhangjiang Road, Shanghai Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |