CN102023948B

CN102023948B - Direct interface method of USB 3.0 bus and high speed intelligent unified bus

Info

Publication number: CN102023948B
Application number: CN2010105779606A
Authority: CN
Inventors: 史忠科; 王闯; 贺莹
Original assignee: Northwestern Polytechnical University
Current assignee: Northwestern Polytechnical University
Priority date: 2010-12-02
Filing date: 2010-12-02
Publication date: 2012-05-30
Anticipated expiration: 2030-12-02
Also published as: CN102023948A

Abstract

The invention discloses a direct interface method of a USB (universal serial bus) 3.0 bus and a high speed intelligent unified bus which is used for solving the technical problem of low interconnection speed between the existing USB 3.0 bus and other buses. The technical scheme comprises the following steps: analyzing the standard of USB 3.0 through designing a USB 3.0 controller, receiving the effective data on the USB 3.0 bus correctly and completely, and receiving and transmitting the intelligent bus data at a high speed by utilizing a fiber channel through the high-speed transceiver SerDes; using a high-speed buffer storage to realize buffer storage of bidirectional data; and using a clock control module to realize clock exchange of buses with different speeds, thus high-speed reliable and effective transmission of two kinds of bus data is realized.

Description

The direct interface method of USB3.0 bus and high-speed intelligent unibus

Technical field

The present invention relates to a kind of EBI method, the direct interface method of particularly a kind of USB3.0 bus and high-speed intelligent unibus.

Background technology

The USB interface technology is after having passed through USB1.0 version, USB1.1 version, USB2.0 version, and the USB3.0 tissue had been issued USB3.0 official standard white paper in 2008.The USB3.0 version has proposed more advanced standard and application fields more on the basis of several versions in the past.The target of USB3.0 technology is to adopt the architecture design identical with existing USB to realize than the fast transmission speed (its transfer rate can reach 5Gbps) more than 10 times of present USB2.0 interface, and has the ease for use and the plug-and-play feature of traditional USB technology concurrently.New standard is optimized realizing lower energy consumption and the protocol efficiency of Geng Gao the USB3.0 specification, and can support copper and two kinds of cables of optical fiber.The speed of using optical fiber to connect can reach 20 times even 30 times of USB2.0, and its application comprises personal computer, consumption and moves the instantaneous transmission synchronously fast of series products.

Development along with avionics system; The integrated scale of system is increasing; Sharing out the work and helping one another of each subsystem embodies a concentrated reflection of in EBI communication and the function computing; Thereby require magnanimity sensor information, image information to realize that the high speed of information is shared through the high-speed intelligent unibus, then the high-speed intelligent unibus of an urgent demand USB3.0 bus and ten thousand megabits can be realized information sharing, and USB3.0 bus itself can't directly be connected with at a high speed unified intelligent bus at present.

In the document of publishing, there is not document that the interface conversion method of USB3.0 bus and other bus forms is studied.According to usb protocol; USB3.0 equipment can backward compatibility USB1.0, USB1.1 and USB2.0 standard; Though can the data stream of USB3.0 agreement be converted to the USB2.0 standard; Realize the conversion of USB3.0 interface more indirectly through the interface of USB2.0 bus and other bus forms, but like this advantage of USB3.0 transmission speed will weaken greatly, and the data number of turnover increase the reliability and the integrality that must reduce transmission; If mandatory unified transmission medium, will cause signal to noise ratio (S/N ratio) weak of signal, worsen sharing of information.

Summary of the invention

In order to overcome prior USB 3.0 buses and the low deficiency of other bus transfer rates; The present invention proposes the direct interface method of a kind of USB3.0 bus and high-speed intelligent unibus; Realize parsing through design USB3.0 controller to the USB3.0 standard; Valid data on the correct complete reception USB3.0 bus utilize optical-fibre channel to realize the intelligent bus data in high speed is received and dispatched through high-speed transceiver SerDes; Realize the buffer-stored of bi-directional data through cache memory; The clock of realizing the different rates bus through clock control module switches, and can realize the reliable effectively transmission of high speed of two kinds of bus datas.

The technical solution adopted for the present invention to solve the technical problems: the direct interface method of a kind of USB3.0 bus and high-speed intelligent unibus is characterized in may further comprise the steps:

(a) be the basis with the store-and-forward mechanism, the read-write clock through buffer zone switches realizes the interconnected of two kinds of different transmission rates buses.Open up the transmitting-receiving buffer memory in high speed logic array inside, automatically switch according to Data Source and receive and dispatch the read-write clock of buffer memory; Through different priorities is set USB 3.0 is managed with the high-speed intelligent bus resource; Regulation is higher than the priority of write data from the priority of bus reception data; When the USB3.0 bus has data arrives; Status register USB3.0 zone bit set in the bus scheduler, shielding is to the transmission request of data of this end bus; At this moment, the data that receive from high-speed transceiver SerDes will all deposit USB3.0 in and send buffer zone, USB3.0 bus free time, zone bit zero clearing.Vice versa.Thereby effectively avoided the generation of bus collision and loss of data phenomenon.

(b) encode these parts address and signal to be sent through the intelligent bus coding unit when intelligent bus sends in the USB3.0 unit according to the bus code rule, and it is to be sent under low frequency synchronisation signal control, transmission information to be sent into two-way memory etc. then; Receive and send the instruction back to bus and close low frequency synchronisation signal through SS and open high frequency synchronization signal, through data and change string and control is sent address and signal to intelligent bus.

(c) the USB3.0 unit sends signal and the address signal that comes to other unit through continuous automatic reception of high speed logic array and judgement from the permission of intelligent bus, to judge to bus transmission signal or to read the required information of USB3.0 from bus; If send signal, then send according to the flow process of (b) to bus; If need read bus signals, then under the bus synchronous signal controlling, write two-way memory, preserve required bus signals; After receiving, close the bus synchronous signal through SS and open low frequency synchronisation signal, the bus signals that reads is sent into intelligent decoding unit decode, stored data is in order to using.

(d) the design frame format realizes that bus ID identification, data route, shielding receive.

(e) adopt high capacity dual-port HSM avoiding the situation of high-speed intelligent bus, and realize read-write duplex operation storer to the big loss of data of USB3.0 bus transfer data amount; High speed logic array internal module adopts parallel block, The pipeline design, makes the time delay of data transmission of USB3.0 bus and intelligent bus minimize.

The invention has the beneficial effects as follows: realized the interface of USB3.0 bus and intelligent bus, can realize effective reliable interconnect of USB3.0 bus and other bus forms through the intelligent bus interface; Adopt the priority setting that clock switches and Data Receiving is sent; And the characteristics of high speed logic array concurrency reconfigurability have been made full use of; Realize the bidirectional data interaction of low speed USB3.0 bus and high-speed intelligent bus, improved the data rate of USB3.0 bus; Just at the memory cell that joins with bus and change string, SS and high speed logic array and use the very high frequency(VHF) device; And the device that remainder only needs to satisfy this unit requirement gets final product; Thereby reduced the requirement of docking port hardware performance; Increase the fiduciary level of data transmission, and reduced cost.

Below in conjunction with accompanying drawing and embodiment the present invention is elaborated.

Description of drawings

Fig. 1 is the direct interface method interface schema of USB3.0 bus of the present invention and high-speed intelligent unibus.

Fig. 2 is bus arbitration mechanism Control on Communication figure of the present invention.

Fig. 3 is the state machine schematic diagram of both-end bus of the present invention two-way communication.

Fig. 4 is USB3.0 data transmission flow figure of the present invention.

Fig. 5 is a USB3.0 Data Receiving process flow diagram of the present invention.

Fig. 6 is intelligent bus data frame format figure of the present invention.

Embodiment

With reference to Fig. 1～6, specify the present invention.

The present invention is the interface method of a kind of USB3.0 bus and intelligent bus, has realized that USB3.0 equipment carries out the high speed fibre transmission through the high-speed intelligent bus and the high speed fibre data are carried out Data Receiving based on the USB3.0 bus.Hardware configuration of the present invention comprises USB3.0 bus controller, intelligent bus controller, central bus arbitration controller and high-speed large capacity memory.

The control of the scheduling of two kinds of buses and interface is mainly accomplished in high speed logic array FPGA in the present embodiment, and FPGA adopts the EP1C12 chip of the Cyclone series of U.S. altera corp.This chip closeness reaches 12060 LE unit, can satisfy the needs of image processing algorithm and analyzing logic control fully; 169 users can satisfy a plurality of chip connection requests that system realizes IMAQ and storage with the I/O port.The UPD720200 chip of NEC Corporation is adopted in USB3.0 protocol-decoding and Frame encapsulation, and this chip is first the USB3.0 main control chip in the whole world; High-speed transceiver SerDes adopts BCM8152, can reach the data transmit-receive speed of ten thousand megabits; It is the chip of IDT70V3079 that the high speed dual port RAM adopts model, and its read or write speed can reach 4ns the soonest.FPGA mainly carries out the bidirectional buffering of data and the work that scheduling, bus arbitration and clock switch, and to realize the duplex communication of two kinds of buses, the communication capacity of maximum using bus is also avoided losing of data.

The transfer rate of USB3.0 bus is lower than the high-speed intelligent bus; Data from the USB3.0 transmission; Buffer memory in high-speed buffer at first, when being buffered to when a certain amount of, bus scheduler is sent request msg to the high-speed intelligent bus and is sent signal; And distribute the timeslice of sending data, control clock handover module switchable memory synchronous clock simultaneously; At this moment, the high-speed intelligent bus controller sends reads the buffer zone signal, and to the signal that reads from buffer zone with intelligent bus Frame coding, coding back Frame is delivered to the transmission buffer memory of high-speed transceiver SerDes, and sends at a high speed when arriving at clock.Import the data of high-speed transceiver SerDes into through optical-fibre channel; Buffer memory in the intelligent bus send buffer equally; When having detected data arrives, bus scheduler carries out bus arbitration; When the USB3.0 bus is idle, send request to send signal to it immediately, distribute the timeslice of sending data, control the clock handover module simultaneously memory read/write is switched to low-speed mode; At this moment, the USB3.0 controller sends reads the buffer zone signal, and the data of reading are sent after encoding through USB3.0.

This instance adopts the method based on the control and management of priority in bus management.In buffer zone, have data etc. to be sent, data arrives is also arranged simultaneously, this moment, bus arbitration mechanism let data send to get into waiting status, abdicate the reception work that bus is carried out data, after reception finishes, wake data up and send process, the transmission of restore data.

The realization of the interface of USB3.0 bus and intelligent bus makes each be articulated in that low speed bus exclusively enjoys this bus maximum bandwidth on the intelligent bus.Can realize the interconnected of USB3.0 bus and other buses based on the present invention, and the route of bus data has intelligent.Have a plurality of low speed bus interfaces on the intelligent bus, the USB3.0 that therefore realizes based on intelligent bus and other buses interconnected has advantages such as volume is little, cost is low, power consumption is little, and transmitting high speed is reliable.

Claims

1. the direct interface method of USB3.0 bus and high-speed intelligent unibus is characterized in that may further comprise the steps:

(a) be the basis with the store-and-forward mechanism, the read-write clock through buffer zone switches realizes the interconnected of two kinds of different transmission rates buses; Open up the transmitting-receiving buffer memory in high speed logic array inside, automatically switch according to Data Source and receive and dispatch the read-write clock of buffer memory; Through different priorities is set USB3.0 bus and high-speed intelligent unibus resource are managed; Regulation is higher than the priority of write data from the priority of high-speed intelligent unibus reception data; When the USB3.0 bus has data arrives; Status register USB3.0 bus zone bit set in the high-speed intelligent unibus scheduler, shielding is to the transmission request of data of this end bus; At this moment, the data that receive from high-speed transceiver SerDes will all deposit the USB3.0 bus in and send buffer zone, USB3.0 bus free time, zone bit zero clearing; When the USB3.0 bus is sent data, status register USB3.0 bus zone bit set in the high-speed intelligent unibus scheduler, shielding is to the reception request of data of this end bus; All deposit data to be sent in USB3.0 bus send buffer, SerDes outwards sends through high-speed transceiver, the zone bit zero clearing; Thereby effectively avoided the generation of bus collision and loss of data phenomenon;

(b) the USB3.0 bus is when the high-speed intelligent unibus sends; Through high-speed intelligent unibus coding unit encoded according to the bus code rule in these parts address and signal to be sent, it is to be sent under low frequency synchronisation signal control, transmission information to be sent into two-way memory etc. then; Receive and send the instruction back to the high-speed intelligent unibus and close low frequency synchronisation signal through SS and open high frequency synchronization signal, through data and change string and control module is sent address and signal to the high-speed intelligent unibus;

(c) the USB3.0 bus is through the continuous automatic reception of high speed logic array and judge from the permission of high-speed intelligent unibus and send signal and from the address signal of other unit, send signal or read the required information of USB3.0 bus from the high-speed intelligent unibus to judge to the high-speed intelligent unibus; If send signal, then send according to the flow process of (b) to the high-speed intelligent unibus; If need read high-speed intelligent unibus signal, then under the bus synchronous signal controlling, write two-way memory, preserve required high-speed intelligent unibus signal; After receiving, close the bus synchronous signal through SS and open low frequency synchronisation signal, the high-speed intelligent unibus signal that reads is sent into intelligent decoding unit decode, stored data is in order to using;

(d) the design frame format realizes that bus ID identification, data route, shielding receive;

(e) adopt high capacity dual-port HSM avoiding the situation of high-speed intelligent unibus, and realize read-write duplex operation storer to the big loss of data of USB3.0 bus transfer data amount; High speed logic array internal module adopts parallel block, The pipeline design, makes the time delay of data transmission of USB3.0 bus and high-speed intelligent unibus minimize.