CN101997033B - Shielded gate trench mosfet device - Google Patents

Shielded gate trench mosfet device Download PDF

Info

Publication number
CN101997033B
CN101997033B CN201010255667.8A CN201010255667A CN101997033B CN 101997033 B CN101997033 B CN 101997033B CN 201010255667 A CN201010255667 A CN 201010255667A CN 101997033 B CN101997033 B CN 101997033B
Authority
CN
China
Prior art keywords
raceway groove
grid
polysilicon
groove
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201010255667.8A
Other languages
Chinese (zh)
Other versions
CN101997033A (en
Inventor
陈军
李一宽
常虹
李文军
安荷·叭剌
哈姆扎·依玛兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US12/583,191 external-priority patent/US8193580B2/en
Priority claimed from US12/583,192 external-priority patent/US8236651B2/en
Application filed by Alpha and Omega Semiconductor Ltd filed Critical Alpha and Omega Semiconductor Ltd
Priority to CN201410376659.7A priority Critical patent/CN104134696B/en
Publication of CN101997033A publication Critical patent/CN101997033A/en
Application granted granted Critical
Publication of CN101997033B publication Critical patent/CN101997033B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a shielded gate trench metal oxide semiconductor field effect device and a method of making the same, the method comprising forming a plurality of trenches, including using a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a polysilicon spacer dielectric region and a termination protection region, including using a second mask, forming a second polysilicon region in at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region, forming a second electrical contact to the second polysilicon region, including using a third mask, depositing a metal layer, and forming a source metal region and a gate metal region, including using a fourth mask.

Description

Shielded gate trench metallic oxide semiconductor field effect tube
Technical field
The present invention relates to shielded gate trench metallic oxide semiconductor field effect tube and preparation method thereof.
Background technology
Nowadays a lot of design of electronic circuits all have strict requirement to the performance parameter such as conversion performance and on-state resistance of device.In these circuit, often use power metal oxide semiconductor apparatus.Shielded gate trench metal oxide semiconductor field effect tube is exactly so a kind of power metal oxide semiconductor apparatus, and it has good high frequency conversion performance, and very low on-state resistance.The existing technique of preparing dhield grid metal oxide semiconductor field effect tube is all extremely complicated, expensive, conventionally need to use six or six above masks when processing.
Summary of the invention
The object of this invention is to provide a kind of shielded gate trench metal oxide semiconductor field effect tube, it has good high frequency conversion performance, and very low on-state resistance.And preparation method's technique of this shielded gate trench metal oxide semiconductor field effect tube is simple, production cost is low.
In order to achieve the above object, the invention provides a kind of semiconductor device, comprising:
A substrate;
An active grid groove in substrate; And
An asymmetric raceway groove in substrate; Wherein:
Asymmetric raceway groove has first channel walls and second channel walls;
First channel walls liner has the oxide of the first thickness; And
Second channel walls liner has the oxide of the second thickness, is different from the first thickness.
Above-mentioned semiconductor device, wherein, described semiconductor device is a kind of metal oxide semiconductor field effect tube.
Above-mentioned semiconductor device, wherein, described asymmetric raceway groove is a termination raceway groove, isolates a high potential energy district from a low-potential energy district.
Above-mentioned semiconductor device, wherein, described asymmetric raceway groove also, as a grid slideway, links together with the grid in active grid groove.
Above-mentioned semiconductor device, wherein:
The first described thickness is greater than the second thickness; And
First described channel walls is than second more close terminator of channel walls.
Above-mentioned semiconductor device, wherein:
The first described thickness is greater than the second thickness; And
Second described channel walls is than the more close active grid groove of first channel walls.
Above-mentioned semiconductor device, wherein, described active grid groove liner oxide, the second thickness of the thickness of this active gate oxide and asymmetric raceway groove is basic identical.
Above-mentioned semiconductor device, wherein, described asymmetric raceway groove comprises a top grid electrode and a bottom source electrode.
Above-mentioned semiconductor device, wherein, described top grid electrode width is less than the width of bottom source electrode.
Above-mentioned semiconductor device, wherein, described active gate electrode comprises a top grid electrode and a bottom source electrode; The width of top grid electrode is greater than the width of bottom source electrode.
Above-mentioned semiconductor device, wherein, also comprises a near terminator asymmetric raceway groove.
Above-mentioned semiconductor device, also comprises a source electrode polysilicon contact raceway groove that is arranged in substrate; Wherein:
Described source electrode polysilicon contact raceway groove contains a polysilicon electrode; And
The end face of described polysilicon electrode is positioned at the below, bottom surface in this tagma.
Above-mentioned semiconductor device, wherein, also comprises a gate contact hole, is set directly at first top grid electrode top in asymmetric raceway groove.
Above-mentioned semiconductor device, wherein, described asymmetric raceway groove is wider than active grid groove.
The present invention also provides a kind of semiconductor device, comprising:
A substrate;
An active grid groove in substrate; And
A source electrode polysilicon in substrate connects raceway groove; Wherein:
Described source electrode polysilicon connects raceway groove and contains a polysilicon electrode; And
The end face of described polysilicon electrode is positioned at the below, bottom surface in this tagma.
Above-mentioned semiconductor device, wherein, described semiconductor device also comprises a contact hole of filling with metallic conductor, extends to from polysilicon electrode the source metal being deposited on semiconductor device end face.
Above-mentioned semiconductor device, wherein, described contact hole width is less than the width of polysilicon electrode.
Above-mentioned semiconductor device, wherein, the degree of depth of described source electrode polysilicon connection raceway groove is greater than the degree of depth of active grid groove.
Above-mentioned semiconductor device, wherein, it is narrower than active grid groove that described source electrode polysilicon connects raceway groove.
The present invention also provides a kind of semiconductor device, comprising:
A substrate;
An active grid groove in substrate, comprises a first top grid electrode and a first bottom source electrode; And
A grid slideway raceway groove, comprises a second top grid electrode and a second bottom source electrode; Wherein:
The second described top grid electrode is narrower than the second bottom source electrode.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove, for stopping raceway groove, leaves low-potential energy district and high potential energy differentiation.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove around and connect multiple active grid grooves.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove contains a part that connects raceway groove as grid.
Above-mentioned semiconductor device, wherein, the end face of described second grid electrode is positioned at the end face below of Semiconductor substrate.
Above-mentioned semiconductor device, wherein, the second described top grid electrode, also, by a gate contact hole being set directly at above the second top grid electrode, is connected on gate metal.
Above-mentioned semiconductor device, wherein, also comprises a near nitride spacers of top side wall that is positioned at grid slideway raceway groove.
Above-mentioned semiconductor device, wherein, the end face of the second described top grid electrode is positioned at below, nitride spacers bottom surface.
Above-mentioned semiconductor device, wherein, the end face of source area aligns substantially with the bottom surface of nitride spacers.
Above-mentioned semiconductor device, wherein, active grid groove has the active grid groove wall of a liner oxide, and the first thickness of oxide is at the top of active grid groove, and the second thickness is in the bottom of active grid groove, and the second thickness is greater than the first thickness.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove has the grid slideway channel walls of a liner oxide, and the 3rd thickness of oxide is on the top of grid slideway raceway groove, the 4th thickness is in the bottom of grid slideway raceway groove, and the 3rd thickness is greater than the 4th thickness.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove is wider than active grid groove.
Above-mentioned semiconductor device, wherein, described grid slideway raceway groove has first channel walls and second channel walls;
First described channel walls liner has the oxide of the first thickness, between first sidewall and second top grid electrode; And
Second described channel walls liner has the oxide of the second thickness, and the second thickness is different from the first thickness.
Above-mentioned semiconductor device, wherein:
The first described thickness is greater than the second thickness; And
First described channel walls is than second more close terminator of channel walls.
The present invention also provides a kind of method for the preparation of semiconductor device, comprising:
Prepare multiple raceway grooves, comprise and use first mask;
In at least several raceway grooves in multiple raceway grooves, form first multi-crystal silicon area;
Form a polysilicon spacer dielectric area and a termination protection zone, comprise and use second mask;
In at least several raceway grooves in multiple raceway grooves, form second multi-crystal silicon area;
First that is formed into the first multi-crystal silicon area electrically contacts, and second that is formed into the second multi-crystal silicon area electrically contacts, and comprises and uses the 3rd mask;
Deposit a metal level; And
Form a source metal district and a gate metal district, comprise and use the 4th mask.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes one and stops raceway groove.
Above-mentioned method, wherein, is also included in and stops forming asymmetric sidewall in raceway groove.
Above-mentioned method, wherein, forms asymmetric sidewall and comprises, a part for an oxide layer of etching, and owing to having used second mask, therefore at least a portion oxide layer has been capped.
Above-mentioned method, wherein, described asymmetric sidewall comprises first sidewall and second sidewall, the oxide layer of first sidewall is thicker than second sidewall.
Above-mentioned method, wherein, in the forming process of polysilicon spacer dielectric area and termination protection zone, second mask covered termination raceway groove.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes an active cell raceway groove.
Above-mentioned method, wherein:
At least one raceway groove in multiple raceway grooves becomes one and stops raceway groove; And
Stop raceway groove wider than active cell raceway groove.
Above-mentioned method, wherein, second described multi-crystal silicon area is included in and stops in raceway groove, and as grid slideway, is electrically connected with grid.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes a grid slideway, and is electrically connected with second multi-crystal silicon area.
Above-mentioned method, wherein, described grid slideway raceway groove also works to stop raceway groove.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves is gate contact raceway groove.
Above-mentioned method, wherein, described gate contact raceway groove comprises the oxide layer of a liner in gate contact raceway groove, and this oxide layer is positioned at the top area of gate contact raceway groove, and its thickness is greater than the oxidated layer thickness in the bottom section of gate contact raceway groove.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes a source electrode polysilicon contact raceway groove.
Above-mentioned method, wherein, also comprises and forms a source electrode polysilicon contact opening, from source electrode polysilicon contact raceway groove top, extends to below the intermediate cross-section of source electrode polysilicon contact raceway groove.
Above-mentioned method, wherein, prepares multiple raceway grooves and comprises the multiple raceway groove openings of preparation.
Above-mentioned method, wherein, is also included in multiple raceway groove around openings and prepares multiple partitions.
Above-mentioned method, wherein, also comprises the multiple described raceway groove openings of etching.
Above-mentioned method, wherein, described multiple raceway groove openings are with self-alignment mode etching.
Above-mentioned method, wherein, after being also included in the formation of second multi-crystal silicon area, removes described partition.
Above-mentioned method, also comprises implantation bulk material, and wherein, terminator is terminated protection zone protection, does not implant bulk material.
Preparation process of the present invention adopts self calibration contact system, only needs four masks; The dhield grid metallic oxide semiconductor field effect tube production cost of making is lower, has higher puncture voltage, has improved device performance.
Brief description of the drawings
The following detailed description and the accompanying drawings are used for setting forth various embodiment of the present invention.
Figure 1A represents the vertical view of a kind of dhield grid metal oxide semiconductor field effect tube structure embodiment.
Figure 1B represents for example, flow chart for the preparation of the process example of a kind of dhield grid metal oxide semiconductor field effect tube (100).
Fig. 2 is illustrated in the example of the first mask using in an embodiment of device preparation technology.
Fig. 3 is illustrated in the example of the second mask using in an embodiment of device preparation technology.
Fig. 4 is illustrated in the example of the 3rd mask using in an embodiment of device preparation technology.
Fig. 5 is illustrated in the example of the 4th mask using in an embodiment of device preparation technology.
Fig. 6 AA '-32AA ' is the AA ' district of the 100 structures viewgraph of cross-section in preparation process.
Fig. 6 BB '-32BB ' is the BB ' district of the 100 structures viewgraph of cross-section in preparation process.
Fig. 6 CC '-32CC ' is the CC ' district of the 100 structures viewgraph of cross-section in preparation process.
Fig. 6 LL '-32LL ' is the LL ' district of the 100 structures viewgraph of cross-section in preparation process.
Figure 33 AA ' represents a kind of viewgraph of cross-section of AA ' cross section of example device.
Figure 33 BB ' represents a kind of viewgraph of cross-section of BB ' cross section of example device.
Figure 33 CC ' represents a kind of viewgraph of cross-section of CC ' cross section of example device.
Figure 33 LL ' represents a kind of viewgraph of cross-section of LL ' cross section of example device.
Figure 34 represents the viewgraph of cross-section in the AA ' cross section of another embodiment of device.
Figure 35 still represents the viewgraph of cross-section in the AA ' cross section of another embodiment of device.
embodiment
The present invention can implement by variety of way, comprise by the computer program in a kind of technique, a kind of device, system, a kind of component, an embeddeding computer readable memory, and/or processing unit (for example for the instruction carrying out to be stored on internal memory/or the processing unit of the instruction that provided by internal memory, and Memory linkage is to processing unit).In the present note, these embodiment, or adoptable any one other forms of the present invention, can serve as technical method.Generally speaking, the preparation of described technique order can be adjusted within the scope of the invention.Unless stated otherwise, otherwise the described element for executing the task such as processing unit or internal memory, the at the appointed time interim common components as executing the task, or professional component for executing the task.Therefore, " processing unit " as herein described refers to one or more devices, circuit and/or the processing core for the treatment of data such as computer program instructions.
Below introduce the detailed description of one or more embodiment of the present invention, and for the accompanying drawing of purport of the present invention is described.Although these embodiment are relevant with the present invention, the present invention is not limited to any embodiment.Scope of the present invention only limits to claims, and variation and the correction of various equivalences are contained in the present invention.Below also elaborate various detail of the present invention, so that complete understanding and grasp.These details, only for illustrating, without part or all of detail, just can be implemented the present invention according to claims.Statement hereby, relates to the technologic material that the industry in the technology of the present invention field knows and does not repeat them here, in order to avoid obscure.
Introduce embodiment and the preparation process thereof of shielding gate mos field effect transistor device below.Preparation process adopts self calibration contact system, only needs four masks.The dhield grid metallic oxide semiconductor field effect tube production cost of making is lower, has higher puncture voltage, has improved device performance.
Figure 1A represents the vertical view of an a kind of embodiment of dhield grid metal oxide semiconductor field effect tube structure.In this example, 100 structures are positioned in Semiconductor substrate 102.The active area of this structure comprises the active grid grooves such as 104, and grid is just formed in these raceway grooves.This active area also comprises the source/body contact openings such as 106, and the joint forming in these openings is electrically connected to He Zhe tagma, source area on source metal 116.Active area also comprises 108 jointings such as polysilicon such as source electrode such as grade.In a source electrode polysilicon jointing, polysilicon source electrode is deposited in source electrode contact raceway groove 118, and through source electrode contact joint opening 108, be electrically connected on source metal 116 source metal 116 then be electrically connected to source electrode and this tagma of device.Why 110 raceway grooves such as grade surround active area, its object is, as stopping raceway groove, high potential energy district (for example drain electrode) for example, separated from low-potential energy district (source electrode), and be used to form and being electrically connected of gate electrode in active grid groove as grid slideway.As shown in Figure 1A, the overwhelming majority of termination/grid slideway raceway groove 110 is all covered by source metal 116, and shown in viewgraph of cross-section below, source metal 116 is by the gate electrode insulation in a dielectric layer and raceway groove 104 and 110.Termination/grid slideway raceway groove 110 also comprises the part that forms grid slideway epi channels 120.Grid slideway epi channels extends in gate metal district 114, connects raceway groove as grid, and grid jointing opening 112 is deposited on grid and connects in raceway groove, to grid slideway is electrically connected on gate metal 114.Grid slideway epi channels 120 is also interconnected at grid slideway in zones of different, for example 116-1 and 116-2.In this example, grid slideway/termination raceway groove 110 is connected raceway groove 118 with source electrode polysilicon, wider than active grid groove 104.
Figure 1B represents for example, flow chart for the preparation of the process example of a kind of dhield grid metal oxide semiconductor field effect tube (100).Technique 150 has been used four masks.At 152 places, use first mask to form multiple raceway grooves.At 154 places, first set multi-crystal silicon area, namely source electrode polysilicon, shielding polysilicon or polysilicon 1, be formed in multiple raceway grooves.At 156 places, use second mask, form one or more polysilicon spacers dielectric area and one or more terminations protection zone.At 158 places, in deposit spathic silicon some raceway grooves therein, form the second cover multi-crystal silicon area, namely grid polycrystalline silicon or polysilicon 2.At 160 places, use the 3rd mask, make first electrically contact opening towards grid polycrystalline silicon, second electrically contacts opening towards source electrode polysilicon.At 162 places, deposit a metal level.At 164 places, use the 4th mask, form a source metal district and a gate metal district.
Below discuss preparation technology 150 in detail, the vertical view that represents four masks that this technique uses together with Fig. 2-Fig. 5, Fig. 6 AA '-32AA ', 6BB '-32BB ', 6CC '-32CC ' and 6LL '-32LL ' represent respectively along the viewgraph of cross-section of the AA ' of Figure 1A, BB ', CC ' and LL ' face.AA ' is through the source/body joint in active grid groove and active area, and stopped active area and surrounded termination/grid slideway raceway groove of active area.BB ' extends along a set of source/body joint, and passes across the source electrode polysilicon jointing raceway groove between source/body joint.CC ' extends along a set of active grid groove, and passes across at this and overlap the source electrode polysilicon jointing raceway groove between active grid groove.LL ' passes terminator, and is connected raceway groove (in this example, this raceway groove is the extension of termination/grid slideway raceway groove) and grid jointing intersection with grid.Figure 32 AA ', 32BB ', 32CC ' and 32LL ' represent the viewgraph of cross-section of device, and these accompanying drawings have elaborated the cross section of device.
In the following discussion, N-type device is only for illustrating.Can prepare P type device by similar technique.In Fig. 6 AA ', 6BB ', 6CC ' and 6LL ', N-type substrate 602 (one deck N-epitaxial loayer of growing on N+ silicon chip) is as the drain electrode of device.In certain embodiments, the doping content of epitaxial loayer is about 3E16-1E17 alloy/cm 3, thickness is 2-4um, the resistivity of substrate is 0.5-3mohm*cm.
By deposition or thermal oxidation, on substrate, form a silicon dioxide layer 604.Nitration case 606 is deposited on silicon dioxide layer top.In certain embodiments, the thickness of silicon dioxide layer be about 500～ the thickness of nitration case is about
Above nitration case, deposit a photoresist layer (PR), utilize first mask to form pattern.Fig. 2 represents the vertical view of first mask example, i.e. raceway groove mask.Raceway groove mask 200 is used to form the pattern of photoresist layer.The photoresist region in corresponding mask shadow region is not what expose, and the photoresist region of corresponding mask nonshaded area exposes.In following discussion, in order to explain, if use positive photoresist, retain unexposed region, remove the region of exposure.Also can use negative photoresist, as long as according to circumstances revise mask.Raceway groove mask has defined active grid groove 204, source electrode polysilicon and has connected raceway groove (for example 208) and grid slideway/termination raceway groove (for example 210).In this example, dissimilar raceway groove has different width: active grid groove is the narrowest, and the width of source electrode polysilicon connection raceway groove is placed in the middle, and the width of grid slideway/termination raceway groove is the widest.In certain embodiments, the width of active grid groove, source electrode polysilicon connection raceway groove and grid slideway/termination raceway groove is about respectively 0.6um, 1.0um and 2.0um.The rudimentary mask that for example critical dimension is 0.35um can be used for preparing this device, has reduced the mask cost using.
On AA ' cross section in Fig. 7 AA ', remaining photoresist layer has formed termination raceway groove opening 702 and active grid groove opening 704.On BB ' cross section in Fig. 7 BB ', remaining photoresist layer has formed source electrode polysilicon jointing opening 706.On CC ' cross section in Fig. 7 CC ', all photoresist layers have all been removed.On LL ' cross section in Fig. 7 LL ', remaining photoresist layer has formed grid jointing opening 708.
Next, by dura mater etching, the partial etching of nitration case and silicon dioxide layer exposure is fallen.Till etching into silicon chip surface always.Then remove remaining photoresist.In Fig. 8 AA ', 8BB ' and 8LL ', raceway groove opening is all formed in exposed region.In Fig. 8 CC ', remove all nitration cases and silicon dioxide layer along CC ' cross section.
Then carry out channel etching.In Fig. 9 AA ', 9BB ' and 9LL ', raceway groove opening is etched deeplyer.In certain embodiments, the target depth of raceway groove is about 0.3um～0.5um.In Fig. 9 CC ', remove disilicide layer along CC ' cross section.
In raceway groove opening, along at the bottom of raceway groove and channel walls, deposition or a very thin oxide layer of heat growth.In certain embodiments, the thickness of oxide layer is about once after oxide layer forms, just deposit an additional nitration case, and along horizontal plane back etching.In certain embodiments, the thickness of nitration case is about as shown in Figure 10 AA ', 10BB ' and 10CC ', after the etching of back, will form nitride spacers 1000,1002 and 1004 along channel walls completely.Because oxide and the nitride of the inside are etched away, therefore CC ' cross section does not change.
Then,, except the inner oxide layer that the open bottom of dechannelling exposes, by complete silicon etching, further deepen the raceway groove in Figure 11 AA ', 11BB ' and 11LL '.The final channel depth forming is about 1.5um～2.5um, specifically depends on the device that will apply, and the inclination angle of channel walls is about 87 °～88 °.Nitride spacers can be used self-alignment etching technics, does not need the calibration process such as the calibration mask adding, and has therefore realized raceway groove bevel etched.Due to the character of the etching load coefficient of silicon, raceway groove opening is wider, and the channel depth of acquisition is darker.For example, because grid slideway joint opening 702 is wider than active gate connection opening 704, therefore, as shown in Figure 11 AA ', the grid slideway raceway groove 1102 of formation is darker than active grid groove 1104.The degree of depth of raceway groove can change between hundreds of dust is to several microns.Pass through circular hole etching, make the turning of raceway groove more level and smooth, can avoid the high electric field causing due to acute corners.
In Figure 12 AA-12LL ', there is the oxide layer of one or more depositions or heat growth.In certain embodiments, can cultivate one approximately sacrificial oxide layer, then remove, to improve silicon face.First cultivate one approximately grid oxic horizon, and then cultivate one approximately high temperature thermal oxidation compound layer.
As shown in Figure 13 AA '-13LL ', deposit spathic silicon.In certain embodiments, the thickness of polysilicon is about go back large than 1/2 of the widest channel width.Therefore, the polysilicon on sidewall can mix, and fills all raceway grooves completely.This polysilicon layer also finger source electrode polysilicon, shielding polysilicon or polysilicon 1 sometimes.
As shown in Figure 14 AA '-14LL ', by dry etching, source electrode polysilicon is carried out to back etching.In this example, remaining polysilicon thickness is about
Then deposit high-density plasma oxide, and thickening.In certain embodiments, thickening temperature is about 1150 DEG C, continues about 30 seconds.The thickness that makes the oxide in trench sidewalls uniformity (as the t1 in Figure 15 AA '-15LL ' marks) completely all on whole device.In certain embodiments, t1 is about this can only fill narrow raceway groove (for example active grid groove contacts raceway groove with source electrode) completely, and for example, can only realize and being partially filled for wider raceway groove (grid slideway raceway groove 1502 is connected raceway groove 1504 with grid).Therefore, wider raceway groove is not filled completely, makes the gate electrode of follow-up formation, is deposited on the place of not filled completely by the high-density plasma oxide in this wide raceway groove.For example, in narrow raceway groove (active channel 1506), the thickness t 1 of oxide layer is gone back large than 1/2 of channel width, and therefore raceway groove is also filled in the mixing of the oxide of the inside completely.
Carry out oxide chemistry mechanical polishing.As shown in Figure 16 AA '-16LL ', chemico-mechanical polishing is used for the oxide of polishing, until the end face of oxide is equal with nitride surface, at this moment etching finishes.
Figure 17 AA '-17LL ' represents additional another oxide layer.In certain embodiments, the thickness of oxide layer is about the thickness of this oxide layer can be controlled at the wet etching of second mask below and lose sagging angle.Nitride in all non-active area of all right protection device of this oxide layer.Protected nitride contributes to next silicon to be carried out without the complete etching of mask.
At this body structure surface spin coating one deck photoresist layer, and use second mask.Fig. 3 represents the vertical view of second mask.Dotted line represents the profile of a mask and raceway groove mask.Use polysilicon overlay film, be conducive to the formation of inner polysilicon oxidation region and termination protection zone.Photoresist in the region 302 (shadow region) of polysilicon overlay film does not expose, and therefore, the region covering below it just can the erosion of oxide wet etching.And photoresist in the regions such as 304 of overlay film exposes, will be removed.Photoresist does not have chlamydate region to be just etched away.In 304 openings such as grade, can form active metal oxide semiconductor field effect tube unit.As below will introduce in detail ground like that, the edge of these openings is very near the termination raceway grooves such as 306 and 308, this is conducive to the asymmetric etching to these raceway grooves.
Figure 18 AA ', 18BB ', 18CC ' and 18LL ' represent to remove the pattern of the photoresist mask after expose portion.Photoresist mask in AA ' transverse cross-sectional area extends in terminator at 1802 places, fills and stops raceway groove, and continue to extend in active area at 1806 places at 1804 places.Shown in figure below 19AA ', by etching, a part of oxide of photoresist below will be removed.The sinking of overlapping and wet etching erosion of mask determined final pattern jointly.Therefore, the distance of extending in active area of photoresist mask, has determined that etching removes the number of oxide to a certain extent.The scope of the sagging degree of depth of oxide is 0.6um～1.5um.In Figure 18 BB ', photoresist mask has shielded source electrode polysilicon and has connected raceway groove 1806, and it is not etched.In Figure 18 CC ', photoresist mask, in required joint, has shielded a part of nitride.In Figure 18 LL ', grid connects contact raceway groove and peripheral region is all covered by photoresist.
Then, carry out wet etching erosion, after etching as shown in Figure 19 AA '-19LL '.Oxide in the region not covered by photoresist is removed, and remaining oxide still remains on required height.Near some oxide photoresist edge is also removed.In Figure 19 AA ', be positioned at photoresist below, near a part of oxide in the grid slideway raceway groove 1902 at photoresist edge, be also removed.The amount of the oxide of etching can be controlled by the position of adjusting photoresist layer edge 1904.Extension edge 1904 is the closer to active area, and the oxide being etched is fewer, and extension edge is more from active area, and what be etched is more.In different embodiment, the amount of the oxide being etched is also different.In this example, fully, after etching oxide, the thickness that is attached in vertical direction the residual oxide in channel walls is basically identical.The oxide layer of polysilicon top, for example oxide layer 1906 and 1908, is called as polysilicon spacer medium, and its scope arrives between several thousand dusts at hundreds of.In Figure 19 BB ' and 19CC ', near partial oxide photoresist mask edge is removed.
Then remove photoresist, deposition or heat growth one deck gate oxide.In certain embodiments, the thickness of additional oxide layer is about therefore,, in Figure 20 AA ', the channel walls such as 2002,2004,2006 and 2008 are all lined with oxide.Stop raceway groove 2010 and have asymmetric sidewall, wherein the oxide layer of sidewall 2008 is than the oxidation bed thickness of sidewall 2002.
Carry out another polysilicon deposition and back etching.In Figure 21 AA '-21LL ', in various raceway grooves, deposition approximately polysilicon.The grid polycrystalline silicons such as the polysilicon to deposition carries out back etching, formation 2102,2104,2106 and 2108.In this example, polysilicon surface is about 500- under the reference grade of nitride spacers bottom.Deposit the metal level of a titanium or cobalt, and annealing.In the place of metal and polysilicon contact, can form a polysilicon compound layer.Titanium or cobalt above oxide or nitride are removed, and can not form silicide.As shown in the figure, above grid polycrystalline silicon electrode 2110,2112.2114,2116 and 2118 places form polysilicon compound.
In Figure 22 AA ', the nitride spacers exposing in slideway grid groove and active grid groove, goes by wet etching ablation.In Figure 22 BB ', remove the nitride layer of exposure, and oxide 2202 a part of nitration case below.Protect oxide layer nitride spacers 2204 and 2206 is not etched.In Figure 22 LL ', oxide layer 2212 is protected nitration case 2208.
In Figure 23 AA '-23LL ', carry out body implantation.With adulterating, ion bombards device at a certain angle.In the active area that is not nitrided thing protection, implant forms 2304 these tagmas such as grade.In certain embodiments, in the time of 60KEV～180KeV, using dosage is about the boron ion of 1.8e13, forms N-channel device.Also can use the ion of other types, for example, use phosphonium ion to prepare P-channel device.
In Figure 24 AA '-24LL ', in the time of zero inclination angle, carry out source electrode implantation.Again with doping Ions Bombardment device.In certain embodiments, in the time of 40KeV～80KeV, using dosage is about the arsenic ion of 4e15.In 2304 these tagmas such as grade, form the source areas such as 2402.
Without using extra mask, the body of implant devices and source electrode.In the terminators such as 2402, the barrier of oxide-nitride thing-oxide stops implanting ions, avoids forming source electrode and this tagma, and this has just improved closing or device performance when cut-off state.
In Figure 25 AA '-25LL ', deposition oxide, fill raceway groove opening, and stop source electrode and grid polycrystalline silicon region.In certain embodiments, use chemical gaseous phase depositing process deposit thickness to be about low temperature oxide and the silex glass that contains boron phosphorus.
In Figure 26 AA '-26LL ', by dry etching method, oxide is carried out to back etching, etch into the terminal on active cell silicon face downwards.
As shown in Figure 27 AA '-27LL ', carry out the complete etching of silicon.Etching depth is according to device instructions for use, between 0.6um～0.9um.The silicon area exposing is etched, and the region of oxide and/or protecting nitride will not be etched.Because etching process does not need extra mask, therefore this is also referred to as self calibration contact process.
Use another layer of photoresist and the 3rd mask.Fig. 4 represents the 3rd mask, and it is also referred to as polysilicon and connects mask or contact mask.In this example, comprise grid polycrystalline silicon jointing (for example 402) with the function of mask, and source electrode polysilicon jointing (for example 404)
In Figure 28 AA '-28LL ', remove the photoresist of exposure, form joint pattern.Above source electrode polysilicon jointing, form the joint opening as shown in Figure 28 BB ' and 28CC ', and the source electrode polysilicon jointing shown in Figure 28 LL '.
In Figure 29 AA '-29LL ', carry out contact etching, then remove photoresist.Carrying out body contact implants.In this example, use P-shaped material (for example, in the time of 40KeV, the BF that dopant dose is 1.0e15 2ion) form body contact and implant, for example 2902.After implantation, contact to implant and activate.In certain embodiments, contact is implanted and is activated as rapid thermal treatment, in the time of about 1000 DEG C, continues 30 seconds.Also can select, drive to activate contact with activation heat and implant.In Figure 29 BB ' and 29CC ', due to source electrode polysilicon, for example 2904 and 2906, carry out heavy doping by source dopant, the impact that therefore they can not be implanted.
In Figure 30 AA '-30LL ', deposition barrier metal, for example titanium and titanium nitride by rapid thermal treatment, form Titanium silicide subsequently near contact zone.In certain embodiments, the titanium using and the thickness of titanium nitride are respectively with then deposits tungsten.In certain embodiments, deposition tungsten.Tungsten to deposition carries out back etching, upwards etches into oxide surface always, forms independently tungsten plug, and for example 3002,3004,3006 and 3008.
Use the 4th mask to form source metal district and gate metal district, and make joint in suitable position.Fig. 5 represents the 4th mask, also referred to as metal mask.Shadow region 502 and 504 corresponding source metal and gate metal respectively.The corresponding metal part of part that does not add shade, etches away this metal part, so that separated source metal area and gate metal district.
In Figure 31 AA '-31LL ', deposit a metal level.In certain embodiments, use AlCu to form a metal level of thick about 3um～6um.Then deposit photoresist, and come out with metal mask.Metal in the exposed regions such as 3102 and 3104 is etched away.
Remove residual photoresist layer, and metal is annealed.In certain embodiments, at 450 DEG C, metal is annealed 30 minutes.Figure 32 AA '-32LL ' represents the viewgraph of cross-section of resulting devices.
Figure 33 AA ' represents a kind of AA ' viewgraph of cross-section of example device.In this example, the source electrode of device, body and metal area are as shown in the figure.Device 3300 contains an asymmetric raceway groove 3306 and active grid groove 3302 and 3304.Asymmetric raceway groove 3306 stops raceway groove as one, from low-potential energy district (being source electrode), isolates high potential energy district (i.e. drain electrode).In raceway groove 3306, sidewall 3308 is near terminator, and sidewall 3310 is near active area.The oxide layer 3328 of liner between sidewall 3308 and top grid polysilicon 3316, the oxide layer 3328 than liner between sidewall 3310 and top grid polysilicon 3316 is thicker.Thicker oxide layer can for example,, from high potential energy district (drain electrode), shield low-potential energy district (for example source electrode), and improve the puncture voltage of device preferably.Shown in figure below 33LL ', raceway groove 3306 also plays the effect of grid slideway raceway groove in addition, surrounds active area, interconnects active grid groove.
All asymmetric raceway grooves and active grid groove all contain a top polysilicon electrode (for example polysilicon 3316,3312 or 3314), and because this electrode plays grid, therefore it is called as gate electrode; Because it is that second polysilicon place in preparation process forms, therefore it is also referred to as polysilicon 2 again.Each top polysilicon electrode also comprises a polysilicon compound layer 3340 being deposited on gate electrode end face, to promote the conductivity along grid.Each raceway groove also comprises a bottom polysilicon electrode (for example polysilicon 3318,3320 and 3322), and because this electrode is connected on source electrode, therefore it is called as source electrode polysilicon; Because it is that first polysilicon place in preparation process forms, therefore it is also referred to as polysilicon 1 again.Separate grid polycrystalline silicon from source electrode polysilicon the polysilicon spacer dielectric area being formed by oxide.In active grid groove in this example, be enclosed in around grid polycrystalline silicon and the oxide layer (for example oxide layer in region 3324) of liner in the sidewall of raceway groove top, than being enclosed in source electrode/shielding polysilicon, around also the oxide layer of liner in trench bottom sidewall is thinner.In addition,, because oxide layer 3328 and active gate oxide 3324 form in same process, therefore their thickness is basic identical.In active area, source metal 3334 is for example, by dielectric layer (oxide 3309), with gate electrode 3312,3314 and 3316 insulation.Source metal 3334 for example, by a conductor 3330 (tungsten plug), be electrically connected on source area 3332 and this tagma 3348, this conductor has filled up source-body joint opening, from source metal, through source area, extend in this tagma.Body contact implantation region 3346 has strengthened the ohmic contact between this tagma and conductor 3330.In terminator, oxide 3338 extends along nitride spacers 3336, until with the end face of nitration case 3342 substantially at grade.Nitration case 3342 and nitride spacers 3336 have sealed and have been deposited on the oxide layer 3344 on epitaxial loayer end face in terminator.Be deposited on the bottom of the oxide layer 3344 on epitaxial loayer end face in terminator, substantially align with the end face of oxide layer in active area 3309.And the bottom of nitride spacers 3336 is as benchmark, the end face of source area 3332 is calibrated with it.The end face of top polysilicon gate electrode 3321,3314 and 3316 is recessed to this reference mark, and is positioned at the end face below of source area 3332.As shown in Figure 33 LL ', the gate metal 3335 that is deposited on nitration case 3342 tops separates with source metal, powers on and touches on gate electrode in other positions.
Figure 33 BB ' represents a kind of BB ' viewgraph of cross-section of example device.In this example, source electrode connects raceway groove 3352 and has a source electrode polysilicon electrode 3354, and this electrode for example, is electrically connected on source metal 3356 by metallic conductor (in raceway groove 3352, fill up the tungsten plug of contact hole 3358).The width of contact hole is less than polysilicon electrode, and contact hole extends vertically up to from source electrode polysilicon electrode the source metal 3356 being deposited on end face.The end face of source electrode polysilicon electrode is positioned at the below, bottom surface (bulk junction) in this tagma 3350.In certain embodiments, as shown in Figure 33 AA ', source electrode connects raceway groove 3352 may be wider, darker than active grid groove 3302 and 3304.In some other embodiment, source electrode connects raceway groove may be narrower, more shallow than active grid groove.Because nitride spacers 3353 is deposited near the top of source electrode connection trench sidewalls, and extend on the end face of nitride material region 3355, stopped body implantation, therefore body is separated from the sidewall of source electrode connection raceway groove.
Figure 33 CC ' represents a kind of CC ' viewgraph of cross-section of example device.As shown in the figure, source electrode polysilicon 3360, by tungsten plug 3362, is connected in source metal 3356, and tungsten plug has filled up contact hole within source electrode polysilicon connects raceway groove, and extends to source metal 3356 from source electrode polysilicon electrode.Source electrode polysilicon 3360 is also along active grid groove, extend in the space of active gate electrode 3364 belows, thereby form a bucking electrode (source electrode/shielding polysilicon), gate electrode is shielded out from be deposited on the drain region 3366 Semiconductor substrate (conventionally connecting high voltage).
Figure 33 LL ' represents a kind of LL ' viewgraph of cross-section of example device.Different from the asymmetric raceway groove 3306 in Figure 33 AA ', the grid in Figure 33 LL ' connects raceway groove 3370 (that is grid slideway raceway groove 3306 is extended raceway groove) and has a structure about the center line almost symmetry of raceway groove.In this example, source electrode/shielding polysilicon 3372 is embedded in grid with grid polycrystalline silicon 3374 and is connected in raceway groove 3370.The thickness that is deposited on the oxide layer 3373 between partial sidewall on grid polycrystalline silicon 3374 and raceway groove is substantially even, this than be enclosed in around source electrode/shielding polysilicon and the oxide layer (for example oxide layer 3378) of liner in two sidewalls of trench bottom want thick many.The recessed end face to epitaxial substrate 3366 of end face of grid polycrystalline silicon, and it has a polysilicon compound layer 3375, to improve the grid conductance rate along grid groove.Within grid connects raceway groove, the tungsten plug of filling contact hole 3376 openings, extends to from the top of grid polycrystalline silicon the gate metal layer 3378 being deposited on nitration case 3384 end faces, and grid polycrystalline silicon electrode 3374 and gate metal 3378 are electrically connected.Grid connects near the nitride spacers 3382 trench sidewalls, extends on the end face of nitration case 3384.Nitration case 3384 and nitride spacers have sealed the oxide layer 3386 on the epitaxial substrate end face being deposited in terminator.The end face of gate electrode 3374 is positioned at the below of nitride spacers 3382.It is wider than active grid groove that grid connects raceway groove 3370.
Above-described embodiment has proposed a kind of metallic oxide semiconductor field effect tube with grid slideway raceway groove, it is dissymmetrical structure on some cross section (for example AA '), and on other cross sections, (for example LL ') is but almost symmetry structure.According to mask design, optional embodiment can be prepared according to same process.In an optional embodiment, second mask as shown in Figure 18 AA ' continues to extend to depths, active area at 1806 places, so that photoresist can be protected the oxide of two sidewall liners of raceway groove 1804 completely, in follow-up wet etching process, be not etched, according to the similar method as shown in Figure 18 LL ' and 19LL ', the device architecture of making according to above-mentioned technique device 3400 just as shown in figure 34, with a termination/grid slideway raceway groove 3402, there is one and be similar to the almost symmetry structure shown in Figure 33 LL ', instead of dissymmetrical structure as shown in Figure 33 AA '.Also can select, by rearranging the 3rd the gate connection position in mask, directly termination/grid slideway raceway groove 3402 tops in AA ' cross section form gate contact opening 3376, so that termination/grid slideway raceway groove 3402 also connects raceway groove as grid.In certain embodiments, revise first and the 4th mask, the distance between near the active grid groove 3302 in termination/grid slideway raceway groove 3402 and terminator is increased, to there is enough spaces separated grid metal 3406 from active metal 3408.In other embodiment, gate contact hole can be deposited on asymmetric termination/grid slideway raceway groove top, to gate connection is directly delivered to gate metal.Therefore, termination/grid slideway raceway groove also can be used as grid connection raceway groove.As shown in figure 35, except gate contact hole 3376 is positioned at the top of asymmetric termination/grid slideway raceway groove 3506, and in position, separate grid and source metal, so that outside gate contact, the structure of device 3500 is all similar with the structure of the device 3300 shown in Figure 33 AA '.
Above-mentioned example multilist shows N-type device.After the polarity inversion of various alloys, this technology just can be applicable to P-type device.
The details of above-described embodiment, only for explaining, is not limited to scope of the present invention.The present invention also can realize by many other modes.Above-described embodiment is only as explanation, not restricted.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.Read after foregoing those skilled in the art, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (10)

1. a semiconductor device, comprising:
A substrate;
An active grid groove in substrate; And
An asymmetric raceway groove in substrate; Wherein:
Asymmetric raceway groove has first channel walls and second channel walls;
First channel walls liner has the oxide of the first thickness; And
Second channel walls liner has the oxide of the second thickness;
The first described thickness is greater than the second thickness; And
First described channel walls is than near second more close terminator asymmetric raceway groove of channel walls, nitride spacers (3336) bottom is arranged in the substrate of terminator, and be close near asymmetric raceway groove first channel walls (3308) of terminator above, the top of this nitride spacers (3336) exceeds asymmetric raceway groove and extends upwardly to the end face of nitration case (3342) and flush; As the liner that stops close the terminator in the asymmetric raceway groove of raceway groove between the top grid polysilicon (3316) of the first channel walls (3308) and asymmetric raceway groove along nitride spacers (3336) extension, up to the end face of the nitration case (3342) of terminator end face at grade;
Described asymmetric raceway groove is a termination raceway groove, isolates a high potential energy district from a low-potential energy district;
Described asymmetric raceway groove also, as a grid slideway, links together with the grid in active grid groove.
2. semiconductor device as claimed in claim 1, is characterized in that, described semiconductor device is a kind of metal oxide semiconductor field effect tube.
3. semiconductor device as claimed in claim 1, is characterized in that:
The first described thickness is greater than the second thickness; And
Second described channel walls is than the more close active grid groove of first channel walls.
4. semiconductor device as claimed in claim 3, is characterized in that, the second thickness of the thickness of the oxide of active grid groove liner and asymmetric raceway groove is basic identical.
5. semiconductor device as claimed in claim 1, is characterized in that, described asymmetric raceway groove comprises a top grid electrode and a bottom source electrode.
6. semiconductor device as claimed in claim 5, is characterized in that, the width of described top grid electrode is less than the width of bottom source electrode.
7. semiconductor device as claimed in claim 1, is characterized in that, described active grid groove comprises a top grid electrode and a bottom source electrode; The width of top grid electrode is greater than the width of bottom source electrode.
8. semiconductor device as claimed in claim 1, also comprises a source electrode polysilicon contact raceway groove that is arranged in substrate; It is characterized in that, wherein:
Described source electrode polysilicon contact raceway groove contains a polysilicon electrode; And
The end face of described polysilicon electrode is positioned at the below, bottom surface in this tagma.
9. semiconductor device as claimed in claim 1, is characterized in that, also comprises a gate contact hole, is set directly at first top grid electrode top in asymmetric raceway groove.
10. semiconductor device as claimed in claim 1, is characterized in that, described asymmetric raceway groove is wider than active grid groove.
CN201010255667.8A 2009-08-14 2010-08-11 Shielded gate trench mosfet device Active CN101997033B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410376659.7A CN104134696B (en) 2009-08-14 2010-08-11 Shielded gate trench mosfet device and method of making the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US12/583,191 US8193580B2 (en) 2009-08-14 2009-08-14 Shielded gate trench MOSFET device and fabrication
US12/583,191 2009-08-14
US12/583,192 2009-08-14
US12/583,192 US8236651B2 (en) 2009-08-14 2009-08-14 Shielded gate trench MOSFET device and fabrication

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201410376659.7A Division CN104134696B (en) 2009-08-14 2010-08-11 Shielded gate trench mosfet device and method of making the same

Publications (2)

Publication Number Publication Date
CN101997033A CN101997033A (en) 2011-03-30
CN101997033B true CN101997033B (en) 2014-09-10

Family

ID=43586351

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201010255667.8A Active CN101997033B (en) 2009-08-14 2010-08-11 Shielded gate trench mosfet device
CN201410376659.7A Active CN104134696B (en) 2009-08-14 2010-08-11 Shielded gate trench mosfet device and method of making the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201410376659.7A Active CN104134696B (en) 2009-08-14 2010-08-11 Shielded gate trench mosfet device and method of making the same

Country Status (3)

Country Link
CN (2) CN101997033B (en)
TW (1) TWI492380B (en)
WO (1) WO2011019378A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816431B2 (en) * 2012-03-09 2014-08-26 Fairchild Semiconductor Corporation Shielded gate MOSFET device with a funnel-shaped trench
CN105428241B (en) * 2015-12-25 2018-04-17 上海华虹宏力半导体制造有限公司 The manufacture method of trench-gate power devices with shield grid
CN118077058A (en) * 2022-09-23 2024-05-24 华为数字能源技术有限公司 Semiconductor device, manufacturing method, power conversion circuit and vehicle
CN117393501B (en) * 2023-12-07 2024-03-19 合肥晶合集成电路股份有限公司 Semiconductor structure and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033891B2 (en) * 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
CN101375400A (en) * 2006-02-17 2009-02-25 万国半导体股份有限公司 Shielded gate trench (sgt) mosfet devices and manufacturing processes

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7652326B2 (en) * 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7390717B2 (en) * 2004-02-09 2008-06-24 International Rectifier Corporation Trench power MOSFET fabrication using inside/outside spacers
DE102004057791B4 (en) * 2004-11-30 2018-12-13 Infineon Technologies Ag Trench transistor and method for its production
US7453119B2 (en) * 2005-02-11 2008-11-18 Alphs & Omega Semiconductor, Ltd. Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact
US20060273382A1 (en) * 2005-06-06 2006-12-07 M-Mos Sdn. Bhd. High density trench MOSFET with low gate resistance and reduced source contact space
WO2006135746A2 (en) * 2005-06-10 2006-12-21 Fairchild Semiconductor Corporation Charge balance field effect transistor
TWI400757B (en) * 2005-06-29 2013-07-01 Fairchild Semiconductor Methods for forming shielded gate field effect transistors
US7319256B1 (en) * 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7612407B2 (en) * 2006-08-07 2009-11-03 Force-Mos Technology Corp. Ltd Trenched MOSFET device configuration with reduced mask processes
US8035159B2 (en) * 2007-04-30 2011-10-11 Alpha & Omega Semiconductor, Ltd. Device structure and manufacturing method using HDP deposited source-body implant block
US7687352B2 (en) * 2007-10-02 2010-03-30 Inpower Semiconductor Co., Ltd. Trench MOSFET and method of manufacture utilizing four masks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7033891B2 (en) * 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
CN101375400A (en) * 2006-02-17 2009-02-25 万国半导体股份有限公司 Shielded gate trench (sgt) mosfet devices and manufacturing processes

Also Published As

Publication number Publication date
TWI492380B (en) 2015-07-11
TW201133844A (en) 2011-10-01
WO2011019378A1 (en) 2011-02-17
CN104134696B (en) 2017-12-05
CN104134696A (en) 2014-11-05
CN101997033A (en) 2011-03-30

Similar Documents

Publication Publication Date Title
CN102194699B (en) Shielded gate trench MOS with improved source pickup layout
US10680097B2 (en) MOSFET device and fabrication
US8236651B2 (en) Shielded gate trench MOSFET device and fabrication
JP4975944B2 (en) Double diffusion metal oxide semiconductor transistor with zener diode for electrostatic discharge protection
CN102610568B (en) Trench poly ESD formation for trench MOS and SGT
CN102623501B (en) Shielded gate trench MOSFET with increased source-metal contact
US20120112270A1 (en) Vertical transistor having buried junction and method for manufacturing the same
CN111697081B (en) LDMOS device and manufacturing method thereof
CN102723277A (en) Fabrication of trench dmos device having thick bottom shielding oxide
CN103050407B (en) Embedded Transistor
CN101950735B (en) High voltage device
JP6375176B2 (en) Semiconductor device and manufacturing method of semiconductor device
CN101997033B (en) Shielded gate trench mosfet device
JP4122230B2 (en) Double diffusion field effect transistor with reduced on-resistance
US6777293B1 (en) DMOS transistor structure with gate electrode trench for high density integration and method of fabricating the structure
CN112133750A (en) Deep trench power device and preparation method thereof
CN113113414B (en) Floating gate type split gate flash memory device structure and manufacturing method thereof
CN112530867B (en) Trench type field effect transistor structure and preparation method thereof
US10038088B2 (en) Power MOSFET having improved manufacturability, low on-resistance and high breakdown voltage
JP4992179B2 (en) Semiconductor device and manufacturing method thereof
CN112838118A (en) Manufacturing method of ultra-low on-resistance LDMOS
CN118714848A (en) Semiconductor device and method for manufacturing the same
KR20100078983A (en) Semiconductor device having recess gate and method of fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200703

Address after: Ontario, Canada

Patentee after: World semiconductor International L.P.

Address before: 475 oakmead Park, Sunnyvale, CA 94085, USA

Patentee before: Alpha and Omega Semiconductor Inc.