KR20100078983A - Semiconductor device having recess gate and method of fabricating the same - Google Patents

Semiconductor device having recess gate and method of fabricating the same Download PDF

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Publication number
KR20100078983A
KR20100078983A KR1020080137378A KR20080137378A KR20100078983A KR 20100078983 A KR20100078983 A KR 20100078983A KR 1020080137378 A KR1020080137378 A KR 1020080137378A KR 20080137378 A KR20080137378 A KR 20080137378A KR 20100078983 A KR20100078983 A KR 20100078983A
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KR
South Korea
Prior art keywords
substrate
recess
recess pattern
semiconductor device
gate
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KR1020080137378A
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Korean (ko)
Inventor
유병화
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주식회사 하이닉스반도체
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Priority to KR1020080137378A priority Critical patent/KR20100078983A/en
Publication of KR20100078983A publication Critical patent/KR20100078983A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A semiconductor device with a recess gate and a method for manufacturing the same are provided to form a threshold voltage control layer on substrates of a bottom side and a side of a recess pattern, thereby increasing an effective channel length of the semiconductor device. CONSTITUTION: A recess pattern(104) is formed on a substrate(101). A threshold voltage control layer(111) is formed in a side and a bottom side of the recess pattern. Two gates(108) share the recess pattern. The substrate comprises a plurality of active areas(103) defined with an element isolating film. Source and drain areas(110) are formed on the substrate in both sides of the gate.

Description

A semiconductor device having a recess gate and a method of manufacturing the same {SEMICONDUCTOR DEVICE HAVING RECESS GATE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same, which can increase the effective channel length of a semiconductor device having a recess gate.

As the semiconductor device is highly integrated, the channel length of the transistor becomes shorter and it is difficult to secure the electrical characteristics of the semiconductor device due to the leakage current caused by the increase of the electric field as the doping concentration of the impurity region increases.

In order to overcome this problem, a semiconductor device having a recess gate has been proposed. Here, the recess gate is formed by recessing the substrate to form a recess pattern, and then forming a gate on the recess pattern, thereby increasing the channel length and reducing the doping concentration of the impurity region.

1 is a diagram illustrating a semiconductor device having a recess gate according to the related art.

Referring to FIG. 1, a semiconductor device including a recess gate according to the related art is illustrated in a substrate 11 and a substrate 11 having a plurality of active regions 13 defined by an isolation layer 12. A plurality of recess patterns 14 and a plurality of recess patterns 14 and a gate 18 protruding from the substrate 11, and source and drain regions 19 formed on both substrates 11 of the gate 18. And a threshold voltage adjusting layer 20 formed on the substrate 11 on the bottom surface of the recess pattern 14 through an ion implantation process. In this case, the gate 18 is a stacked structure in which the gate insulating film 15, the gate electrode 16, and the gate hard mask film 17 are stacked.

Here, since the threshold voltage adjusting layer 20 acts as a substantial channel region during the operation of the semiconductor device, the effective channel length L2 may be measured through the region where the threshold voltage adjusting layer 20 is formed.

However, in the related art, as the degree of integration of the semiconductor device increases, the line width W2 of the recess pattern 14 also decreases, so that the ion implantation process margin for forming the threshold voltage control layer 20 decreases, thereby reducing the recess pattern ( 14) The threshold voltage adjusting layer 20 is formed only on the substrate 11 on the bottom surface. As a result, the channel length L1 is set along the surface of the recess pattern 14 between the source and drain regions 19 at design time, but the effective channel length L2 at the time of actual semiconductor device operation is determined by the channel length ( There is a problem that it becomes shorter than L1) (L1> L2).

This problem can be solved by forming the threshold voltage adjusting layer 20 on the side substrate 11 of the recess pattern 14, but the prior art forms the recess pattern 14 to correspond to each gate 18. Therefore, two recess patterns 14 are disposed in the active region 13. In addition, since the recess pattern 14 is formed to have a line width smaller than the line width W1 of the gate 18, the line width W2 of the recess pattern 14 is very fine. Therefore, even when the tilt ion implantation is used, it is substantially impossible to form the threshold voltage adjusting layer 20 on the substrate 11 on the side of the recess pattern 14.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can increase the effective channel length of a semiconductor device having a recess gate.

According to an aspect of the present invention, a semiconductor device includes: a recess pattern formed on a substrate; And a threshold voltage regulating layer formed on the substrate on the sidewalls and the bottom of the recess pattern, and two gates in contact with the sidewalls and the bottom of the recess pattern and sharing the recess pattern. In this case, the threshold voltage adjusting layer may have a 'L' shape.

The substrate may include a plurality of active regions defined by an isolation layer, and one recess pattern may be disposed for each of the active regions.

The semiconductor device may further include a source and a drain region formed on the substrate on both sides of the gate, wherein one of the source and drain regions may contact the bottom surface of the recess pattern, and the other may contact the substrate upper surface.

The two gates sharing the recess pattern may be disposed to be spaced apart from each other by a predetermined interval.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a recess pattern on a substrate; Implanting impurities into the substrate on the sidewalls and bottom of the recess pattern to form a threshold voltage control layer; and forming two gates in contact with the sidewalls and bottom of the recess pattern and sharing the recess pattern. Steps.

The method may further include forming a source and a drain region by implanting impurities into the substrate at both sides of the gate, wherein one of the source and drain regions is in contact with a bottom surface of the recess pattern, and the other is at the top of the substrate. It can be formed in contact with.

The forming of the recess pattern may be performed by selectively etching a substrate on which a plurality of active regions are defined by an isolation layer, so that the recess patterns are disposed one by one for each of the active regions.

The forming of the threshold voltage adjusting layer may be performed by using a gradient ion implantation method, and the threshold voltage adjusting layer may be formed to have an 'L' shape.

In the forming of the two gates sharing the recess pattern, the gates may be formed to be spaced apart from each other by a predetermined interval.

According to the present invention based on the above-described problem solving means, the line width of the recess pattern can be increased by forming two gates to share one recess pattern in the semiconductor device having the recess gate. Through this, the threshold voltage regulating layer is formed on the substrate of the recess pattern bottom surface and the side wall to increase the effective channel length of the semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention described below provides a semiconductor device capable of increasing an effective channel length of a semiconductor device having a recess gate (RG) and a method of manufacturing the same. To this end, in the present invention, two gates share one recess pattern, thereby increasing the line width of the recess pattern, thereby forming a threshold voltage regulating layer that determines the effective channel length on the recess pattern sidewall and bottom substrate. It is a technical principle to do it.

2 is a cross-sectional view illustrating a semiconductor device having a recess gate according to a first embodiment of the present invention.

As shown in FIG. 2, in the semiconductor device of the present invention, the threshold voltage regulating layer 111 formed on the recess pattern 104 formed on the substrate 101, the sidewalls of the recess pattern 104, and the substrate 101 on the bottom surface thereof. ) And two gates 108 abutting the sidewalls and bottom surface of the recess pattern 104 and sharing the recess pattern 104. At this time, the threshold voltage adjusting layer 111 may have an 'L' shape.

The threshold voltage regulating layer 111 is formed through an ion implantation process, in particular, a tilt ion implantation, and serves as a substantial channel region during semiconductor device operation. Therefore, the effective channel length L can be measured through the region where the threshold voltage regulating layer 111 is formed.

In addition, the gate 108 may further include a source and a drain region 110 formed on both substrates 101. In this case, any one of the source and drain regions 110 may be formed to contact the bottom surface of the recess pattern 104, and may be formed to contact the upper surface of the remaining substrate 101. Accordingly, the channel region between the source and drain regions 110 may be formed up and down along the sidewall of the recess pattern 104.

Here, in designing a semiconductor device having a recess gate, a channel length is set along the surface of the recess pattern 104 between the source and drain regions 110. The present invention provides a recess between the source and drain regions 110. Since the threshold voltage regulating layer 111 is formed along the surface of the pattern 104, the effective channel length L may be equal to the channel length set in the design. Therefore, in the highly integrated semiconductor device, it is possible to prevent the deterioration of characteristics of the semiconductor device due to the smaller effective channel length than the channel length set during design.

The substrate 101 may include a plurality of active regions 103 defined by the device isolation layer 102, and one recess pattern 104 may be disposed for each active region 103. For reference, since the recess patterns 104 are conventionally disposed to correspond to the gate 108, two recess patterns 104 are disposed in each active region 103 (see FIG. 1).

The two gates 108 may contact the sidewalls and the bottom surface of the recess pattern 104, respectively, and may be disposed to be spaced apart from each other by a predetermined interval. In this case, the gate 108 may be a stacked structure in which the gate insulating film 105, the gate electrode 106, and the gate hard mask film 107 are sequentially stacked.

The gate insulating layer 105 may be an oxide layer, for example, a silicon oxide layer (SiO 2 ). The gate electrode 106 may be a silicon film, a metal film, or a stacked film in which a silicon film and a metal film are stacked. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. As the metallic film, tungsten (W), titanium (Ti), titanium nitride film (TiN), tungsten silicide (WSi), etc. Can be used. The gate hard mask film 107 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride or a laminated film in which these are stacked.

The gate spacer layer 109 may be further formed on both sidewalls of the gate 108. The gate spacer film 109 may be formed of an oxide film, a nitride film, or a laminated film in which an oxide film and a nitride film are stacked.

As described above, the present invention can increase the line width W of the recess pattern 104 by forming two gates 108 to share one recess pattern 104. As a result, the effective voltage length L of the semiconductor device may be increased by forming the threshold voltage regulating layer 111 on the bottom surface and sidewalls of the recess pattern 104.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to a second embodiment of the present invention.

As shown in FIG. 3A, after the hard mask pattern (not shown) is formed on the substrate 31 on which the plurality of active regions 33 are defined by the device isolation layer 32, the hard mask pattern is formed as an etch barrier ( The recess pattern 34 is formed by etching the substrate 11 with an etch barrier. In this case, the recess pattern 34 may be formed by etching only the active region 33 or by etching both the active region 33 and the device isolation layer 32 to simultaneously cross the active region 33 and the device isolation layer 32. It can also be formed in a line type.

In general, since the recess patterns 34 for the recess gates are formed corresponding to the number of gates, two recess patterns 34 are formed in the active region 33 (see FIG. 1). However, the present invention is characterized in that one recess pattern 34 is disposed in each active region 33. As a result, the line width W of the recess pattern 34 may be significantly increased.

As shown in FIG. 3B, the threshold voltage adjusting layer 35 is formed by ion implanting impurities for adjusting the threshold voltage into the substrate 31 on the sidewalls and bottom of the recess pattern 34. In this case, the threshold voltage adjusting layer 35 may be formed to have an 'L' shape. Here, the threshold voltage adjusting layer 35 serves as a substantial channel region in the operation of the semiconductor device, and thus the effective channel length can be estimated through the region where the threshold voltage adjusting layer 35 is formed.

The threshold voltage regulating layer 35 is inclined in order to ion implant the impurity for adjusting the threshold voltage into the substrate 31 on the sidewalls and bottom of the recess pattern 34, particularly the substrate 31 on the sidewall of the recess pattern 34. It is preferable to form using a tilt ion implant. The gradient ion implantation method refers to an ion implantation technique in which impurity ions are implanted to have a predetermined inclination angle with respect to the upper surface of the substrate 31.

N-type impurities such as phosphorus (P), arsenic (As), or P-type impurities such as boron (B) may be used as the impurity for adjusting the threshold voltage.

Meanwhile, after ion implantation of impurities into the substrate 31 on the sidewalls of the recess pattern 34 through the inclination ion implantation, impurities are continuously implanted into the substrate 31 on the bottom surface of the recess pattern 34. The threshold voltage adjusting layer 35 may be formed in the form of '└┘'.

As shown in FIG. 3C, a gate insulating film 36 is formed on the surface of the recess pattern 34. The gate insulating film 36 may be formed of an oxide film, for example, silicon oxide film SiO 2 , and the silicon oxide film for the gate insulating film 36 may be formed using thermal oxidation.

Next, a gate conductive film 37 is formed on the gate insulating film 36 to fill the recess pattern 34 and cover the upper surface of the substrate 31. The gate conductive film 37 may be formed of a silicon film, a metallic film, or a laminated film in which a silicon film and a metallic film are laminated. As the silicon film, a polysilicon film (poly Si), a silicon germanium film (SiGe), or the like can be used. As the metallic film, tungsten (W), titanium (Ti), titanium nitride film (TiN), tungsten silicide (WSi), or the like Can be used.

Next, a gate hard mask film 38 is formed on the gate conductive film 37. The gate hard mask film 38 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film or a laminated film in which these are laminated.

Next, after the photoresist pattern (not shown) is formed on the gate hard mask layer 38, the gate hard mask layer 38, the gate conductive layer 37, and the gate insulating layer 36 are formed using the photoresist layer pattern as an etch barrier. Etching is sequentially performed to form two gates 39 sharing one recess pattern 34. Hereinafter, the reference numeral of the etched gate insulating film 36 is referred to as '36A', the reference numeral of the etched gate conductive film 37 is referred to as '37A', and the reference numeral of the etched gate hard mask film 38 is referred to as '38A'. Change it to '.

Here, the gate 39 may be in contact with the sidewall and the bottom surface of the recess pattern 34, and may be formed to be spaced apart from each other by a predetermined interval. That is, the gate 39 may be formed to expose the center portion of the bottom surface of the recess pattern 34.

As shown in FIG. 3D, the gate spacer layer 40 is formed on both sidewalls of the gate 39. The gate spacer film 40 may be formed of an oxide film, a nitride film, or a laminated film in which the oxide film and the nitride film are stacked.

Next, impurities are implanted into the substrate 31 using the gate 39 and the gate spacer layer 40 as ion implantation barriers to form source and drain regions 41 on the substrate 31 on both sides of the gate 39. In this case, one of the source and drain regions 41 may be formed to be in contact with the bottom surface of the recess pattern 34, and the other may be formed to be in contact with the top surface of the substrate 31. Accordingly, the channel region between the source and drain regions 41 may be formed up and down along the sidewall of the recess pattern 34.

As described above, the present invention can increase the line width of the recess pattern 34 by forming two gates 39 to share one recess pattern 34. Through this, the threshold voltage control layer 35 may be formed through the ion implantation process of the substrate 31 on the bottom and sidewalls of the recess pattern 34.

In summary, the present invention provides a recess gate by forming the threshold voltage regulating layer 35 on the substrate 31 on the sidewall of the recess pattern 34, which has not been able to form the threshold voltage regulating layer 35. The effective channel length of the semiconductor device can be increased.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view of a semiconductor device having a recess gate according to the prior art.

2 is a cross-sectional view of a semiconductor device having a recess gate according to the first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with a second embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

101 substrate 102 device isolation film

103: active area 104: recess pattern

105: gate insulating film 106: gate electrode

107: gate hard mask film 108: gate

109: gate spacer film 110: source and drain regions

111: threshold voltage control layer

Claims (11)

A recess pattern formed on the substrate; A threshold voltage regulating layer formed on the substrate on sidewalls and bottoms of the recess patterns; And Two gates which contact the recess pattern sidewalls and the bottom surface and share the recess pattern; A semiconductor device comprising a. The method of claim 1, The threshold voltage control layer is a semiconductor device having an 'L' shape. The method of claim 1, The substrate has a plurality of active regions defined by an isolation layer, and the recess patterns are disposed one for each of the active regions. The method of claim 1, And a source and a drain region formed in the substrate on both sides of the gate, wherein one of the source and drain regions is in contact with a bottom surface of the recess pattern, and the other is in contact with the substrate upper surface. The method of claim 1, The two gates sharing the recess pattern may be And a semiconductor device spaced apart from each other by a predetermined interval. Forming a recess pattern in the substrate; Forming a threshold voltage control layer by implanting impurities into the substrate on the sidewalls and the bottom of the recess pattern; And Forming two gates in contact with sidewalls and bottom surfaces of the recess patterns and sharing the recess patterns; Semiconductor device manufacturing method comprising a. The method of claim 6, Implanting impurities into the substrate on both sides of the gate to form source and drain regions, wherein one of the source and drain regions is in contact with the recess pattern bottom surface and the other is in contact with the substrate upper surface. The semiconductor device manufacturing method formed so that. The method of claim 6, Forming the recess pattern, And etching the substrate in which a plurality of active regions are defined by an isolation layer so that the recess patterns are arranged one by one for each of the active regions. The method of claim 6, Forming the threshold voltage control layer, A semiconductor device manufacturing method carried out using a gradient ion implantation method. The method of claim 6, And forming the threshold voltage regulating layer to have an 'L' shape. The method of claim 6, Forming the two gates sharing the recess pattern, And forming a gap between the gates at a predetermined interval.
KR1020080137378A 2008-12-30 2008-12-30 Semiconductor device having recess gate and method of fabricating the same KR20100078983A (en)

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