CN104134696B - Shielded gate trench mosfet device and method of making the same - Google Patents

Shielded gate trench mosfet device and method of making the same Download PDF

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Publication number
CN104134696B
CN104134696B CN201410376659.7A CN201410376659A CN104134696B CN 104134696 B CN104134696 B CN 104134696B CN 201410376659 A CN201410376659 A CN 201410376659A CN 104134696 B CN104134696 B CN 104134696B
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Prior art keywords
raceway groove
polysilicon
gate
electrode
source
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CN104134696A (en
Inventor
陈军
李宽
李一宽
常虹
李文军
安荷·叭剌
哈姆扎·依玛兹
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Ltd
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Priority claimed from US12/583,191 external-priority patent/US8193580B2/en
Priority claimed from US12/583,192 external-priority patent/US8236651B2/en
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Publication of CN104134696A publication Critical patent/CN104134696A/en
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract

The invention relates to a shielded gate trench metal oxide semiconductor field effect device and a method of making the same, the method comprising forming a plurality of trenches, including using a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a polysilicon spacer dielectric region and a termination protection region, including using a second mask, forming a second polysilicon region in at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region, forming a second electrical contact to the second polysilicon region, including using a third mask, depositing a metal layer, and forming a source metal region and a gate metal region, including using a fourth mask.

Description

Shielded gate trench metallic oxide semiconductor field effect tube and preparation method thereof
This case is divisional application
Original bill denomination of invention：Shielded gate trench metallic oxide semiconductor field effect tube and preparation method thereof
Original bill application number：201010255667.8
The original bill applying date：On August 11st, 2010
Technical field
The present invention relates to shielded gate trench metallic oxide semiconductor field effect tube and preparation method thereof.
Background technology
Nowadays the performance parameter such as the conversion performance and on-state resistance of many design of electronic circuits all to device has sternly The requirement of lattice.Power metal oxide semiconductor apparatus is commonly used in these circuits.Shielded gate trench metal oxide Semiconductor field is exactly such a power metal oxide semiconductor apparatus, and it has good high frequency conversion performance, And very low on-state resistance.The existing technique for preparing dhield grid metal oxide semiconductor field effect tube is all extremely It is complicated, expensive, the mask using six or more than six is usually required during processing.
The content of the invention
It is an object of the invention to provide a kind of shielded gate trench metal oxide semiconductor field effect tube, and it has good High frequency conversion performance, and very low on-state resistance.And the shielded gate trench metal oxide semiconductcor field effect Should pipe preparation method technique is simple, production cost is low.
In order to achieve the above object, the present invention provides a kind of semiconductor devices, including：
One substrate；
One active gate raceway groove in the substrate；And
One asymmetric raceway groove in the substrate；Wherein：
Asymmetric raceway groove has first channel walls and second channel walls；
First channel walls liner has the oxide of first thickness；And
Second channel walls liner has the oxide of second thickness, different from first thickness.
Above-mentioned semiconductor devices, wherein, described semiconductor devices is a kind of metal oxide semiconductor field effect tube.
Above-mentioned semiconductor devices, wherein, described asymmetric raceway groove is a termination raceway groove, is separated from a low-potential energy area Go out a high potential energy area.
Above-mentioned semiconductor devices, wherein, described asymmetric raceway groove is also used as a gate runner, with active gate ditch Grid in road links together.
Above-mentioned semiconductor devices, wherein：
Described first thickness is more than second thickness；And
Described than second channel walls of first channel walls are closer to terminator.
Above-mentioned semiconductor devices, wherein：
Described first thickness is more than second thickness；And
Described than first channel walls of second channel walls are closer to active gate raceway groove.
Above-mentioned semiconductor devices, wherein, described active gate raceway groove liner oxide, the active gate oxide The second thickness of thickness and asymmetric raceway groove is essentially identical.
Above-mentioned semiconductor devices, wherein, described asymmetric raceway groove includes a top grid electrode and a bottom Source electrode.
Above-mentioned semiconductor devices, wherein, described top grid electrode width is less than the width of bottom source electrode.
Above-mentioned semiconductor devices, wherein, described active gate electrode includes a top grid electrode and a bottom Portion's source electrode；The width of top grid electrode is more than the width of bottom source electrode.
Above-mentioned semiconductor devices, wherein, in addition to one the terminator near asymmetric raceway groove.
Above-mentioned semiconductor devices, in addition to a source polysilicon contact raceway groove being located in substrate；Wherein：
Described source polysilicon contact raceway groove contains a polysilicon electrode；And
The top surface of described polysilicon electrode is located at the subjacent of body zone.
Above-mentioned semiconductor devices, wherein, in addition to a gate contact hole, be set directly in asymmetric raceway groove Above one top grid electrode.
Above-mentioned semiconductor devices, wherein, described asymmetric raceway groove is wider than active gate raceway groove.
Present invention also offers a kind of semiconductor devices, including：
One substrate；
One active gate raceway groove in the substrate；And
One source polysilicon connection raceway groove in the substrate；Wherein：
Described source polysilicon connection raceway groove contains a polysilicon electrode；And
The top surface of described polysilicon electrode is located at the subjacent of body zone.
Above-mentioned semiconductor devices, wherein, described semiconductor devices also includes a contact filled with metallic conductor Hole, the source metal being deposited on semiconductor devices top surface is extended to from polysilicon electrode.
Above-mentioned semiconductor devices, wherein, described contact hole width is less than the width of polysilicon electrode.
Above-mentioned semiconductor devices, wherein, the depth of described source polysilicon connection raceway groove is more than active gate raceway groove Depth.
Above-mentioned semiconductor devices, wherein, described source polysilicon connection raceway groove is narrower than active gate raceway groove.
Present invention also offers a kind of semiconductor devices, including：
One substrate；
One active gate raceway groove in the substrate, including a first top grid electrode and first bottom source Electrode；And
One gate runner raceway groove, including a second top grid electrode and a second bottom source electrode；Wherein：
The second described top grid electrode is narrower than the second bottom source electrode.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove is terminates raceway groove, by low-potential energy area and high potential energy Differentiation is left.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove surrounds and connects multiple active gate raceway grooves.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove contains the part as grid connection raceway groove.
Above-mentioned semiconductor devices, wherein, the top surface of described second grid electrode is located under the top surface of Semiconductor substrate Side.
Above-mentioned semiconductor devices, wherein, the second described top grid electrode, also it is set directly at second by one Gate contact hole above top grid electrode, is connected on gate metal.
Above-mentioned semiconductor devices, wherein, in addition to a nitridation being located near the top side wall of gate runner raceway groove Thing partition.
Above-mentioned semiconductor devices, wherein, the top surface of the second described top grid electrode is located at nitride spacers bottom surface Lower section.
Above-mentioned semiconductor devices, wherein, the top surface of source area and the bottom surface of nitride spacers are substantially aligned.
Above-mentioned semiconductor devices, wherein, active gate raceway groove has the active gate channel walls of a liner oxide, The first thickness of oxide is big in the bottom of active gate raceway groove, second thickness in the top of active gate raceway groove, second thickness In first thickness.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove has the gate runner of a liner oxide Channel walls, the 3rd thickness of oxide is on the top of gate runner raceway groove, and the 4th thickness is in the bottom of gate runner raceway groove, and the 3rd Thickness is more than the 4th thickness.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove is wider than active gate raceway groove.
Above-mentioned semiconductor devices, wherein, described gate runner raceway groove has first channel walls and second raceway groove Wall；
First described channel walls liner has the oxide of first thickness, positioned at first side wall and second top Between gate electrode；And
Second described channel walls liner has the oxide of second thickness, and second thickness is different from first thickness.
Above-mentioned semiconductor devices, wherein：
Described first thickness is more than second thickness；And
Described than second channel walls of first channel walls are closer to terminator.
Present invention also offers a kind of method for preparing semiconductor devices, including：
Multiple raceway grooves are prepared, including the use of first mask；
In at least several raceway grooves in multiple channels, first multi-crystal silicon area is formed；
A polysilicon spacer dielectric area and a termination protection zone are formed, including the use of second mask；
In at least several raceway grooves in multiple channels, second multi-crystal silicon area is formed；
First electrical contact to the first multi-crystal silicon area is formed, forms second electrical contact to the second multi-crystal silicon area, bag Include and use the 3rd mask；
Deposit a metal level；And
A source metal area and a gate metal area are formed, including the use of the 4th mask.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes a termination raceway groove.
Above-mentioned method, wherein, it is additionally included in termination raceway groove and forms asymmetric side wall.
Above-mentioned method, wherein, forming asymmetric side wall includes, and a part for an oxide layer is etched, due to using Second mask, therefore at least a portion oxide layer is capped.
Above-mentioned method, wherein, described asymmetric side wall includes first side wall and second side wall, first side wall Oxide layer it is thicker than second side wall.
Above-mentioned method, wherein, in the forming process of polysilicon spacer dielectric area and termination protection zone, second mask Cover termination raceway groove.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes an active cell raceway groove.
Above-mentioned method, wherein：
At least one raceway groove in multiple raceway grooves becomes a termination raceway groove；And
It is more wider than active cell raceway groove to terminate raceway groove.
Above-mentioned method, wherein, described second multi-crystal silicon area, which is included in, to be terminated in raceway groove, and is used as gate runner, It is electrically connected with grid.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes a gate runner, and with more than second Crystal silicon area is electrically connected.
Above-mentioned method, wherein, described gate runner raceway groove also plays a part of to terminate raceway groove.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves is gate contact raceway groove.
Above-mentioned method, wherein, described gate contact raceway groove includes a liner oxidation in gate contact raceway groove Layer, the oxide layer are located at the top area of gate contact raceway groove, and its thickness is more than the oxygen in the bottom section of gate contact raceway groove Change thickness degree.
Above-mentioned method, wherein, at least one raceway groove in multiple raceway grooves becomes a source polysilicon contact raceway groove.
Above-mentioned method, wherein, in addition to a source polysilicon contact openings are formed, contact raceway groove from source polysilicon Top, extend to below the intermediate cross-section of source polysilicon contact raceway groove.
Above-mentioned method, wherein, preparing multiple raceway grooves includes preparing multiple raceway groove openings.
Above-mentioned method, wherein, it is additionally included in around multiple raceway groove openings and prepares multiple partitions.
Above-mentioned method, wherein, in addition to the multiple described raceway groove openings of etching.
Above-mentioned method, wherein, described multiple raceway groove openings are etched in a manner of self-alignment.
Above-mentioned method, wherein, it is additionally included in after the formation of second multi-crystal silicon area, removes described partition.
Above-mentioned method, in addition to implantation bulk material, wherein, terminator is terminated protection zone protection, is not implanted into this Body material.
The preparation process of the present invention uses self aligned contact system, it is only necessary to four masks；Manufactured dhield grid metal Oxide semiconductor field effect tube device production cost is lower, has higher breakdown voltage, improves device performance.
Brief description of the drawings
The following detailed description and the accompanying drawings are used for illustrating various embodiments of the present invention.
Figure 1A represents a kind of top view of dhield grid metal oxide semiconductor field effect tube structure embodiment.
Figure 1B represents to be used for the technique reality for preparing a kind of dhield grid metal oxide semiconductor field effect tube (such as 100) Apply the flow chart of example.
Fig. 2 represents the example of the first mask used in one embodiment of device preparation technology.
Fig. 3 represents the example of the second mask used in one embodiment of device preparation technology.
Fig. 4 represents the example of the 3rd mask used in one embodiment of device preparation technology.
Fig. 5 represents the example of the 4th mask used in one embodiment of device preparation technology.
Fig. 6 AA ' -32AA ' are viewgraph of cross-section of the AA ' areas of 100 structures in preparation process.
Fig. 6 BB ' -32BB ' are viewgraph of cross-section of the BB ' areas of 100 structures in preparation process.
Fig. 6 CC ' -32CC ' are viewgraph of cross-section of the CC ' areas of 100 structures in preparation process.
Fig. 6 LL ' -32LL ' are viewgraph of cross-section of the LL ' areas of 100 structures in preparation process.
Figure 33 AA ' represent a kind of viewgraph of cross-section in the AA ' sections of example device.
Figure 33 BB ' represent a kind of viewgraph of cross-section in the BB ' sections of example device.
Figure 33 CC ' represent a kind of viewgraph of cross-section in the CC ' sections of example device.
Figure 33 LL ' represent a kind of viewgraph of cross-section in the LL ' sections of example device.
Figure 34 represents the viewgraph of cross-section in the AA ' sections of another embodiment of device.
Figure 35 still represents the viewgraph of cross-section in the AA ' sections of another embodiment of device.
Embodiment
The present invention can be implemented by various modes, including by a kind of technique, a kind of device, a system, a kind of group Computer program product into material, an embedded computer-readable memory, and/or processing unit (such as one It is individual to be used to performing the processing unit that instruction/on internal memory or the instruction provided by internal memory are provided, and Memory linkage is to handling On device).In the present note, these embodiments, or any one adoptable other forms of the present invention, can serve as technology Method.In general, the preparation order of the technique can be adjusted within the scope of the invention.Unless stated otherwise, it is no The then element for being used to perform task described in processing unit or internal memory etc., can be at the appointed time temporarily as the general of execution task Logical element, or it is performed for the professional component of task.Therefore, " processing unit " as described herein refers to one or more devices Part, circuit and/or the process cores for handling the data such as computer program instructions.
The detailed description of one or more embodiments of the invention is the following describes, and for illustrating present subject matter Accompanying drawing.Although these embodiments are all relevant with the present invention, the invention is not limited in any embodiment.The scope of the present invention is only It is limited to claims, and the present invention covers various changes and amendment of equal value.The each of the present invention is illustrated further below Kind detail, so as to comprehensive understanding and grasp.These details are only used for for example, without part or all of detail, It can implement the present invention according to claims.Hereby give notice that it is related to technologic material known to the industry of technical field It will not be repeated here, in order to avoid obscure.
The embodiment and its preparation process of dhield grid metallic oxide semiconductor field effect tube is described below.Prepare Process uses self aligned contact system, it is only necessary to four masks.Manufactured dhield grid metal oxide semiconductor field effect tube Device production cost is lower, has higher breakdown voltage, improves device performance.
Figure 1A represents a kind of top view of one embodiment of dhield grid metal oxide semiconductor field effect tube structure. In this example, 100 structures are located in Semiconductor substrate 102.The active area of the structure active gate raceway groove such as including 104, grid With regard to being formed in these raceway grooves.Active area source/body contact openings also including 106 etc., formed in these openings Source area and body zone are electrically connected on source metal 116 by joint.Also source polysilicon connects active area including 108 etc. Head.In a source polysilicon jointing, polysilicon source electrode deposition passes through in source contact formula raceway groove 118 Source contact formula joint opening 108, is electrically connected on source metal 116, and source metal 116 transfers to be electrically connected to the source electrode of device And body zone.Why 110 grade raceway grooves surround active area, it is intended that (such as leaking high potential energy area as raceway groove is terminated Pole) separated from low-potential energy area (such as source electrode), and as gate runner be used for formed with active gate raceway groove The electrical connection of gate electrode.As shown in Figure 1A, the overwhelming majority of termination/gate runner raceway groove 110 is all covered by source metal 116 Lid, as shown in following viewgraph of cross-section, source metal 116 passes through the grid electricity in a dielectric layer and raceway groove 104 and 110 Insulate pole.Termination/gate runner raceway groove 110 also includes the part for forming gate runner epi channels 120.Gate runner extension ditch Road is extended in gate metal area 114, and as grid connection raceway groove, grid jointing opening 112 is deposited on grid connection ditch In road, so as to which gate runner is electrically connected on gate metal 114.Gate runner epi channels 120 also interconnect gate runner In different zones, such as 116-1 and 116-2.In this example, gate runner/termination raceway groove 110 and source polysilicon connection ditch Road 118, it is wider than active gate raceway groove 104.
Figure 1B represents to be used for the technique reality for preparing a kind of dhield grid metal oxide semiconductor field effect tube (such as 100) Apply the flow chart of example.Technique 150 has used four masks.At 152, multiple raceway grooves are formed using first mask.154 Place, first set multi-crystal silicon area, that is, source polysilicon, shielding polysilicon or polysilicon 1, are formed in multiple channels.156 Place, using second mask, form one or more polysilicon spacer dielectric areas and one or more termination protection zones. At 158, deposit polycrystalline silicon forms second set of multi-crystal silicon area, that is, grid polycrystalline silicon or polysilicon in some raceway grooves wherein 2.At 160, using the 3rd mask, make first electrical contact opening towards grid polycrystalline silicon, second electrical contact opening court To source polysilicon.At 162, a metal level is deposited.At 164, using the 4th mask, a source metal area is formed With a gate metal area.
Preparation technology 150 has been discussed in detail below, bowing for four masks is represented used in the technique together with Fig. 2-Fig. 5 View, Fig. 6 AA ' -32AA ', 6BB ' -32BB ', 6CC ' -32CC ' and 6LL ' -32LL ' represent respectively along Figure 1A AA ', BB ', CC ' and the viewgraph of cross-section in LL ' faces.AA ' passes through the source/body joint in active gate raceway groove and active area, and eventually Stop active area and surround termination/gate runner raceway groove of active area.BB ' extends along a set of source/body joint, and horizontal The source polysilicon jointing raceway groove being placed through between source/body joint.CC ' prolongs along a set of active gate raceway groove Stretch, and pass across the source polysilicon jointing raceway groove between the active grid groove of this set.LL ' passes through terminator, and With grid connection raceway groove (in this example, this raceway groove be termination/gate runner raceway groove extension) and grid jointing Intersect.Figure 32 AA ', 32BB ', 32CC ' and 32LL ' represent the viewgraph of cross-section of device, and these accompanying drawings illustrate device Cross section.
In the following discussion, N-type device is only used for illustrating.P-type device can be prepared by similar technique.Scheming In 6AA ', 6BB ', 6CC ' and 6LL ', N-type substrate 602 (i.e. in one layer of N- epitaxial layer of N+ grown above silicon) is used as device Drain electrode.In certain embodiments, the doping concentration of epitaxial layer is about 3E16-1E17 dopants/cm3, thickness 2-4um, substrate Resistivity be 0.5-3mohm*cm.
By deposition or thermal oxide, a silicon dioxide layer 604 is formed on substrate.Nitration case 606 is deposited on titanium dioxide Silicon layer.In certain embodiments, the thickness of silicon dioxide layer is aboutThe thickness of nitration case is about
In one photoresist layer (PR) of nitration case disposed thereon, pattern is formed using first mask.Fig. 2 represents the The top view of one mask example, i.e. trench mask.Trench mask 200 is used for the pattern for forming photoresist layer.It is corresponding to cover The photoresist region in film shadow region is not exposure, and the photoresist region of corresponding mask nonshaded area is exposed 's.In the discussion below, in order to illustrate, if using positive photoresist, retain unexposed region, remove exposure Region.Negative photoresist can also be used, as long as according to circumstances correcting mask.Trench mask defines active gate Raceway groove 204, source polysilicon connection raceway groove (such as 208) and gate runner/termination raceway groove (such as 210).In this example, no The raceway groove of same type has different width：Active gate raceway groove is most narrow, the intermediate width of source polysilicon connection raceway groove, grid The width of slideway/termination raceway groove is most wide.In certain embodiments, active gate raceway groove, source polysilicon connection raceway groove and grid The width of pole slideway/termination raceway groove respectively may be about 0.6um, 1.0um and 2.0um.Such as critical dimension is the rudimentary of 0.35um Mask can be used for preparing this device, reduce used mask cost.
On AA ' sections in Fig. 7 AA ', remaining photoresist layer, which forms, terminates raceway groove opening 702 and active Grid groove opening 704.On BB ' sections in Fig. 7 BB ', remaining photoresist layer forms source polysilicon connection Joint opening 706.On CC ' sections in Fig. 7 CC ', all photoresist layers are all removed.In Fig. 7 LL ' On LL ' sections, remaining photoresist layer forms grid jointing opening 708.
Next, the partial etching that nitration case and silicon dioxide layer expose is fallen by dura mater etching.Silicon is etched into always Untill piece surface.Then remaining photoresist is removed.In Fig. 8 AA ', 8BB ' and 8LL ', raceway groove opening is formed on In exposed region.In Fig. 8 CC ', all nitration cases and silicon dioxide layer are removed along CC ' sections.
Then channel etching is carried out.In Fig. 9 AA ', 9BB ' and 9LL ', raceway groove opening is etched deeper.At some In embodiment, the target depth of raceway groove is about 0.3um~0.5um.In Fig. 9 CC ', disilicide layer is removed along CC ' sections.
In raceway groove opening, along raceway groove bottom and channel walls, a very thin oxide layer is deposited or thermally grown.In some implementations In example, the thickness of oxide layer is aboutAfter oxide layer is formed, an additional nitration case is just deposited, and along level Face back etches.In certain embodiments, the thickness of nitration case is aboutSuch as Figure 10 AA ', 10BB ' and 10CC ' institutes Show, after complete back etching, nitride spacers 1000,1002 and 1004 will be formed along channel walls.Due to the oxygen of the inside Compound and nitride have been etched away, therefore CC ' sections do not change.
Then, the inner oxide layer of raceway groove opening bottom-exposed is removed, by complete silicon etching, further deepens figure Raceway groove in 11AA ', 11BB ' and 11LL '.The channel depth ultimately formed is about 1.5um~2.5um, and being specifically dependent upon will The device of application, the inclination angle of channel walls is about 87 °~88 °.Nitride spacers can use self-alignment etching technics, not The calibration process such as additional calibration mask are needed, it is achieved that raceway groove bevel etched.Due to the property of the etch load coefficient of silicon Matter, raceway groove opening is wider, and the channel depth of acquisition is deeper.For example, because gate runner joint opening 702 is than active gate joint It is open 704 wide, therefore, as shown in Figure 11 AA ', the gate runner raceway groove 1102 of formation is deeper than active gate raceway groove 1104.Ditch The depth in road can change between hundreds of angstroms to several microns.Pass through Circular hole etching, make the turning of raceway groove It is more smooth, the high electric field caused by acute corners can be avoided.
There are one or more oxide layers being deposited or thermally grown in Figure 12 AA-12LL '.In certain embodiments, can train Support one aboutSacrificial oxide layer, then remove, to improve silicon face.First cultivate one aboutGrid Oxide layer, then it is further cultured for one aboutHigh temperature thermal oxidation compound layer.
As shown in Figure 13 AA ' -13LL ', deposit polycrystalline silicon.In certain embodiments, the thickness of polysilicon is about1/2 than most wide channel width is also big.Therefore, the polysilicon in side wall can mix, and be filled up completely with institute There is raceway groove.This polysilicon layer is sometimes referred to as source polysilicon, shielding polysilicon or polysilicon 1.
As shown in Figure 14 AA ' -14LL ', by dry etching, back etching is carried out to source polysilicon.In this example, it is remaining Polysilicon thickness be about
Then high-density plasma oxide is deposited, and is thickened.In certain embodiments, thickening temperature is about 1150 DEG C, Continue about 30 seconds.Make the thickness of the oxide in trench sidewalls on whole device all substantially uniformity it is consistent (such as Figure 15 AA '- T1 in 15LL ' is marked).In certain embodiments, t1 is aboutThis can only be filled up completely with narrow raceway groove (such as active gate raceway groove and source contact raceway groove), and (such as gate runner raceway groove 1502 and grid connect for wider raceway groove Connect raceway groove 1504) it can only realize and be partially filled with.Therefore, wider raceway groove is not filled up completely with so that the grid electricity being subsequently formed Pole, it is deposited on not by the complete filling of place of high-density plasma oxide in this wide raceway groove.(such as have in narrow raceway groove Source raceway groove 1506) in, the thickness t1 of oxide layer is 1/2 also bigger than channel width, therefore the oxide mixing of the inside and complete Fill raceway groove.
Carry out oxide chemical mechanical polish.As shown in Figure 16 AA ' -16LL ', chemically-mechanicapolish polish for oxidation of polishing Thing, untill the top surface of oxide is equal with nitride surface, at this moment etching terminates.
Figure 17 AA ' -17LL ' represent to add another oxide layer.In certain embodiments, the thickness of oxide layer is aboutThe thickness of this oxide layer can control the sagging angle of the wet etching below second mask. The oxide layer can be with the nitride in all non-active area of protection device.Next protected nitride contributes to silicon Progress etches completely without mask.
In one layer of photoresist layer of the body structure surface spin coating, and use second mask.Fig. 3 second mask of expression Top view.Dotted line represents the profile of upper a mask and trench mask.Using polysilicon cap film, be advantageous to internal polysilicon oxidation Area and the formation for terminating protection zone.Photoresist in the region 302 (shadow region) of polysilicon cap film does not expose, because This, the region covered below it would not be oxidized thing wet etching.And the photoresist in 304 grade regions of overlay film is sudden and violent Dew, it will be removed.The region that photoresist is not covered with just is etched away.In 304 grade openings, active gold can be formed Belong to oxide semiconductor field effect pipe unit.As being hereinafter described, the edge of these openings is very close to 306 Raceway groove is terminated with 308 grades, this is advantageous to etch the asymmetry of these raceway grooves.
The pattern of photoresist mask after Figure 18 AA ', 18BB ', 18CC ' and 18LL ' expression removing expose portions. Photoresist mask in AA ' transverse cross-sectional areas is extended in terminator at 1802, the filling termination raceway groove at 1804, and Extended continuously at 1806 in active area.With reference to shown in figure below 19AA ', by etching, it will remove below photoresist A part of oxide.The overlapping and wet etching of mask sagging has together decided on final pattern.Therefore, photoresist is covered The distance extended in active area of film, determine to a certain extent etching remove oxide number.Oxide sink depth Scope be 0.6um~1.5um.In Figure 18 BB ', photoresist mask shields source polysilicon connection raceway groove 1806, It is not etched it.In Figure 18 CC ', photoresist mask shields a part of nitride in required joint.Scheming In 18LL ', grid connection contact raceway groove and its peripheral region are all covered by photoresist.
Then, wet etching is carried out, such as Figure 19 AA ' -19LL ' are shown after etching.Not by the region of photoresist covering Oxide be removed, remaining oxide is remained in required height.Some oxygen in photoresist adjacent edges Compound is also removed.In Figure 19 AA ', below photoresist, the gate runner raceway groove close to photoresist edge A part of oxide in 1902, is also removed.The amount of the oxide of etching can be by adjusting photoresist layer edge 1904 Position control.Extension edge 1904 is closer to active area, and the oxide being etched is fewer, and extension edge is carved more from active area That loses is more.In various embodiments, the amount for the oxide being etched is also different.In this example, after abundant etching oxide, The thickness for the residual oxide being attached in vertical direction in channel walls is basically identical.Oxide layer above polysilicon, such as Oxide layer 1906 and 1908, is referred to as polysilicon spacer medium, and its scope is between hundreds of Dao thousands of angstroms.In Figure 19 BB ' and In 19CC ', the partial oxide near photoresist mask edge is removed.
Then photoresist is removed, is deposited or thermally grown one layer of gate oxide.In certain embodiments, Additional oxidation Layer thickness be aboutTherefore, in Figure 20 AA ', the channel walls such as 2002,2004,2006 and 2008 are all lined with oxide. Terminating raceway groove 2010 has asymmetric side wall, wherein oxidation thickness of the oxide layer of side wall 2008 than side wall 2002.
Carry out another polysilicon deposition and back etching.In Figure 21 AA ' -21LL ', deposited about in various raceway groovesPolysilicon.Back etching is carried out to the polysilicon of deposition, forms 2102,2104,2106 and 2108 Deng grid polycrystalline silicon.In this example, polysilicon surface is aboutUnder nitride spacers bottom reference grade. The metal level of a titanium or cobalt is deposited, and is annealed.In the place of metal and polysilicon contact, a polycrystalline silicon can be formed Layer.Titanium or cobalt above oxide or nitride are removed, and will not form silicide.As illustrated, in gate polycrystalline 2110,2112 above silicon electrode.2114th, polycrystalline silicon is formed at 2116 and 2118.
In Figure 22 AA ', the nitride spacers of exposure, are removed by wet etching in slideway grid groove and active gate raceway groove Go.In Figure 22 BB ', a part of nitration case below exposed nitride layer, and oxide 2202 is removed.Oxide layer is protected Nitride spacers 2204 and 2206 are not etched.In Figure 22 LL', oxide layer 2212 protects nitration case 2208.
In Figure 23 AA ' -23LL ', body implantation is carried out.Device is bombarded at a certain angle with Doped ions.Not by nitrogen In the active area of compound protection, implant forms the body zones such as 2304.In certain embodiments, in 60KEV~180KeV, make The boron ion for being about 1.8e13 with dosage, form N- channel devices.Other kinds of ion can also be used, such as use phosphonium ion Prepare P- channel devices.
In Figure 24 AA ' -24LL ', at zero inclination angle, source electrode implantation is carried out.Again device is bombarded with Doped ions. In some embodiments, in 40KeV~80KeV, arsenic ion that dosage is about 4e15.Formed in the body zones such as 2304 2402 grade source areas.
Without using extra mask, the body and source electrode of implant devices.In 2402 grade terminators, oxide-nitride The barrier implanting ions of thing-oxide, avoid the formation of source electrode and body zone, and this improves in closing or cut-off state Device performance.
In Figure 25 AA ' -25LL ', depositionOxide, fill raceway groove opening, and stop source electrode And gate polysilicon region.In certain embodiments, it is about using chemical vapor deposition thicknessLow temperature Oxide and the silica glass containing boron phosphorus.
In Figure 26 AA ' -26LL ', by dry etching method, back etching is carried out to oxide, etched into downwards active Terminal on unit silicon face.
As shown in Figure 27 AA ' -27LL ', carry out silicon and etch completely.Etching depth according to device requirement, 0.6um~ Between 0.9um.Exposed silicon area is etched, and is oxidized the region of thing and/or protecting nitride and will be not etched.Due to etching Process does not need extra mask, therefore this is also referred to as self aligned contact process.
Use another layer of photoresist and the 3rd mask.Fig. 4 represents the 3rd mask, and it is also referred to as polysilicon company Connect mask or contact mask.In this example, the function with mask includes grid polycrystalline silicon jointing (such as 402), and Source polysilicon jointing (such as 404)
In Figure 28 AA ' -28LL ', exposed photoresist is removed, forms joint pattern.Connected in source polysilicon Above joint, the joint opening as shown in Figure 28 BB ' and 28CC' is formed, and the source polysilicon shown in Figure 28 LL ' connects Head.
In Figure 29 AA ' -29LL ', contact etching is carried out, then removes photoresist.Carry out body contacts implantation. In this example, using P-type material, (such as in 40KeV, dopant dose is 1.0e15 BF2Ion) body contacts implantation is formed, Such as 2902.Contact implantation activation is carried out after implantation.In certain embodiments, contact implantation activation is rapid thermal treatment, big Continue 30 seconds at about 1000 DEG C.Also it may be selected, contact implantation activated using activation thermal drivers.In Figure 29 BB ' and 29CC ', Due to source polysilicon, such as 2904 and 2906, heavy doping is carried out with source dopant, therefore they will not be implanted into Influence.
In Figure 30 AA ' -30LL ', barrier metal, such as titanium and titanium nitride are deposited, then by rapid thermal treatment, is being connect Tactile area is formed about Titanium silicide.In certain embodiments, the thickness of used titanium and titanium nitride is respectivelyWithThen deposits tungsten.In certain embodiments, depositionTungsten.Back quarter is carried out to the tungsten of deposition Erosion, etches into oxide surface, forms independent tungsten plug, such as 3002,3004,3006 and 3008 all the way up.
Source metal area and gate metal area are formed using the 4th mask, and joint is in suitable position.Fig. 5 tables Show the 4th mask, also referred to as metal mask.Shadow region 502 and 504 corresponds to source metal and gate metal respectively.It is unshaded Part correspond to metal part, this metal part is etched away, to separate source electrode metal area and gate metal area.
In Figure 31 AA ' -31LL ', a metal level is deposited.In certain embodiments, using AlCu formed thickness about 3um~ A 6um metal level.Then photoresist is deposited, and is exposed with metal mask.In 3102 and 3104 grade exposed regions Metal be etched away.
The photoresist layer of residual is removed, and metal is annealed.In certain embodiments, metal is moved back at 450 DEG C Fire 30 minutes.Figure 32 AA ' -32LL ' represent the viewgraph of cross-section of resulting devices.
Figure 33 AA ' represent a kind of AA ' viewgraph of cross-section of example device.In this example, the source electrode of device, body and metal Area is as shown in the figure.Device 3300 contains asymmetric a raceway groove 3306 and active gate raceway groove 3302 and 3304.Asymmetric ditch From low-potential energy area (i.e. source electrode), high potential energy area (draining) is isolated as a termination raceway groove in road 3306.In raceway groove 3306 In, side wall 3308 is close to terminator, and side wall 3310 is close to active area.Liner side wall 3308 and top gate polysilicon silicon 3316 it Between oxide layer 3328, it is thicker than oxide layer 3328 of the liner between side wall 3310 and top gate polysilicon silicon 3316.It is thicker Oxide layer preferably can shield low-potential energy area (such as source electrode), and improve device from high potential energy area (such as drain electrode) Breakdown voltage.With reference to shown in figure below 33LL ', raceway groove 3306 also plays a part of gate runner raceway groove in addition, surrounds active area, It is connected with each other active gate raceway groove.
All asymmetric raceway groove and active gate raceway grooves are all containing top polysilicon silicon electrode (such as polysilicon 3316th, 3312 or 3314), because this electrode plays grid, therefore it is referred to as gate electrode；Again because it is to prepare During second polysilicon at formed, therefore it is also referred to as polysilicon 2.Each top polysilicon silicon electrode also includes one The individual multi-crystal silicification nitride layer 3340 being deposited on gate electrode top surface, to lift the electrical conductivity along grid.Each raceway groove also includes One bottom polysilicon electrode (such as polysilicon 3318,3320 and 3322), because this electrode is connected on source electrode, therefore its quilt Referred to as source polysilicon；Again because it is formed at first polysilicon in preparation process, thus it be also referred to as it is more Crystal silicon 1.The polysilicon spacer dielectric area formed by oxide, grid polycrystalline silicon is separated from source polysilicon.At this In active gate raceway groove shown in example, simultaneously oxide layer of the liner in channel top side wall is enclosed in around grid polycrystalline silicon (such as oxide layer in region 3324), than be enclosed in around source electrode/shielding polysilicon and liner in trench bottom side wall Oxide layer is thinner.Further, since oxide layer 3328 is formed with active gate oxide 3324 in same process, therefore it Thickness it is essentially identical.In active area, source metal 3334 is by dielectric layer (such as oxide 3309), with gate electrode 3312nd, 3314 and 3316 insulation.Source metal 3334 is electrically connected to source electrode by a conductor 3330 (such as tungsten plug) In area 3332 and body zone 3348, this conductor is filled with source-body joint opening, since source metal, through source area, Extend in body zone.Body contacts implantation region 3346 enhances the Ohmic contact between body zone and conductor 3330. In terminator, oxide 3338 extends along nitride spacers 3336, until being put down substantially same with the top surface of nitration case 3342 On face.Nitration case 3342 and nitride spacers 3336 seal the oxide layer 3344 being deposited on the epitaxial layers top surface of terminator. The bottom for the oxide layer 3344 being deposited on the epitaxial layers top surface of terminator, it is substantially right with the top surface of oxide layer in active area 3309 Together.Moreover, the bottom of nitride spacers 3336 is calibrated therewith as benchmark, the top surface of source area 3332.Top polysilicon silicon gate The top surface of electrode 3321,3314 and 3316 concaves towards this reference mark, and below the top surface of source area 3332.Such as figure Shown in 33LL ', the gate metal 3335 for being deposited on the top of nitration case 3342 separates with source metal, is made electrical contact with other positions Onto gate electrode.
Figure 33 BB ' represent a kind of BB ' viewgraph of cross-section of example device.In this example, source electrode connection raceway groove 3352 has One source polysilicon electrode 3354, (such as one in raceway groove 3352, fills up contact hole by a metallic conductor for this electrode 3358 tungsten plug) it is electrically connected on source metal 3356.The width of contact hole is less than polysilicon electrode, and contact hole is more from source electrode Crystal silicon electrode extends vertically up to the source metal 3356 being deposited on top surface.The top surface of source polysilicon electrode is located at body zone Below 3350 bottom surface (bulk junction).In certain embodiments, as shown in Figure 33 AA ', source electrode connection raceway groove 3352 may be than having Source grid groove 3302 and 3304 is wider, deeper.In some other embodiments, source electrode connection raceway groove may be than active gate ditch Road is narrower, more shallow.Because nitride spacers 3353 are deposited on the near top of source electrode connection raceway groove side wall, and extend to nitride On the top surface in region 3355, body implantation is blocked, therefore body is separated from the side wall of source electrode connection raceway groove.
Figure 33 CC ' represent a kind of CC ' viewgraph of cross-section of example device.As illustrated, source polysilicon 3360 passes through tungsten Plug 3362, it is connected in source metal 3356, tungsten plug is filled with contact hole in source polysilicon connection raceway groove, and from Source polysilicon electrode extends to source metal 3356.Source polysilicon 3360 has extended to also along active gate raceway groove In the space of the lower section of source gate electrode 3364, so as to form a bucking electrode (source electrode/shielding polysilicon), by gate electrode from Shield and come out in the drain region 3366 being deposited in Semiconductor substrate (generally connecting high voltage).
Figure 33 LL ' represent a kind of LL ' viewgraph of cross-section of example device.With the asymmetric raceway groove 3306 in Figure 33 AA ' not Together, the grid connection raceway groove 3370 in Figure 33 LL ' (being one of gate runner raceway groove 3306 extension raceway groove) have one on The structure of the center line almost symmetry of raceway groove.In this example, source electrode/shielding polysilicon 3372 and grid polycrystalline silicon 3374 are embedded in In grid connection raceway groove 3370.The thickness for the oxide layer 3373 being deposited between grid polycrystalline silicon 3374 and raceway groove upper part side wall Substantially uniform, this is than being enclosed in around source electrode/shielding polysilicon and oxide layer of the liner in two side walls of trench bottom (such as oxide layer 3378) is thick many.The top surface of grid polycrystalline silicon concaves towards the top surface of epitaxial substrate 3366, and it has one Individual multi-crystal silicification nitride layer 3375, to improve the grid conductance rate along grid groove.In grid connection raceway groove, filling contact hole The tungsten plug of 3376 openings, extends to the gate metal layer being deposited on the top surface of nitration case 3384 at the top of grid polycrystalline silicon 3378, and gate polycrystalline silicon electrode 3374 and gate metal 3378 are electrically connected.The nitrogen of grid connection raceway groove adjacent sidewalls Compound partition 3382, extend on the top surface of nitration case 3384.Nitration case 3384 and nitride spacers, which seal, is deposited on termination The oxide layer 3386 on epitaxial substrate top surface in area.The top surface of gate electrode 3374 is located at the lower section of nitride spacers 3382. Grid connection raceway groove 3370 is more wider than active gate raceway groove.
Above-described embodiment proposes a kind of metallic oxide semiconductor field effect tube with gate runner raceway groove, it (such as AA ') is dissymmetrical structure on some sections, and (such as LL ') is almost symmetry structure on other sections.Root According to mask design, optional embodiment can be prepared according to same process.In one alternate embodiment, such as Figure 18 AA ' institutes Second mask shown extends continuously to active area depths at 1806, so that photoresist can protect raceway groove 1804 completely Two side wall liners oxide, be not etched in follow-up wet etch process, according to such as Figure 18 LL ' and 19LL ' Suo Shi Similar method, according to the device 3400 just as shown in figure 34 of device architecture made of above-mentioned technique, with a termination/grid Pole slideway raceway groove 3402, there is an almost symmetry structure being similar to shown in Figure 33 LL ', rather than as shown in Figure 33 AA ' Dissymmetrical structure.Also it may be selected, can be directly transversal in AA ' by rearranging the gate connection position in the 3rd mask The top of termination/gate runner raceway groove 3402 in face forms gate contact opening 3376, so that termination/gate runner raceway groove 3402 Also serve as grid connection raceway groove.In certain embodiments, first and the 4th mask are changed so that termination/gate runner ditch The distance between active gate raceway groove 3302 near road 3402 and terminator increases, to have enough spaces from active Metal Separated grid metal 3406 in 3408.In other embodiment, gate contact hole can be deposited on asymmetric termination/grid Above the slideway raceway groove of pole, so as to which gate connection is directly delivered into gate metal.Therefore, termination/gate runner raceway groove can also As grid connection raceway groove.As shown in figure 35, except gate contact hole 3376 is located at asymmetric termination/gate runner raceway groove 3506 top, and in position on separate grid and source metal, outside gate contact, device 3500 Structure is all similar with the structure of the device 3300 shown in Figure 33 AA '.
Above-mentioned example represents N-type device more.After the polarity inversion of various dopants, the technology just can be applied to P-type device Part.
The details of above-described embodiment is only used for illustrating, and does not limit to the scope of the present invention.The present invention can also be by being permitted More other modes are realized.Above-described embodiment is only used as explanation, not restrictive.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (5)

1. a kind of semiconductor devices, including：
One substrate；
One active gate raceway groove in the substrate, including a gate electrode；And
One source polysilicon connection raceway groove in the substrate；Wherein：
Described active gate raceway groove extends and passes across described source polysilicon connection raceway groove, and described source polysilicon connects Connect raceway groove and contain a polysilicon electrode, described polysilicon electrode extends to described grid also along active gate raceway groove In the space of base part, a bucking electrode is formed；And
The top surface of described polysilicon electrode is located at the subjacent of body zone.
2. semiconductor devices as claimed in claim 1, it is characterised in that described semiconductor devices also uses metal including one Conductor filled contact hole, the source metal being deposited on semiconductor devices top surface is extended to from polysilicon electrode.
3. semiconductor devices as claimed in claim 2, it is characterised in that described contact hole width is less than polysilicon electrode Width.
4. semiconductor devices as claimed in claim 1, it is characterised in that the depth of described source polysilicon connection raceway groove is big In the depth of active gate raceway groove.
5. a kind of semiconductor devices, it is characterised in that the semiconductor devices includes：
One substrate；
One active gate raceway groove in the substrate, including a gate electrode；And
One in the substrate bottom be lined with the source polysilicon connection raceway groove of one layer of oxide；Wherein：
Described source polysilicon connection raceway groove contains a polysilicon electrode, and described polysilicon electrode is also along active gate Raceway groove, extend in the space below described gate electrode, form a bucking electrode；And
The top surface of described polysilicon electrode is located at the subjacent of body zone, and described source polysilicon connection raceway groove is than active Grid groove is narrow.
CN201410376659.7A 2009-08-14 2010-08-11 Shielded gate trench mosfet device and method of making the same Active CN104134696B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12/583191 2009-08-14
US12/583192 2009-08-14
US12/583,191 US8193580B2 (en) 2009-08-14 2009-08-14 Shielded gate trench MOSFET device and fabrication
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