CN101995712A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
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- CN101995712A CN101995712A CN2009100914882A CN200910091488A CN101995712A CN 101995712 A CN101995712 A CN 101995712A CN 2009100914882 A CN2009100914882 A CN 2009100914882A CN 200910091488 A CN200910091488 A CN 200910091488A CN 101995712 A CN101995712 A CN 101995712A
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Abstract
The invention relates an array substrate and a manufacturing method thereof. The array substrate comprises an underlayer substrate; a plurality of data lines and grate scanning lines are transversely and longitudinally crossed on the underlayer substrate to encircle to form pixel units arrayed in a matrix form; TFT (Thin Film Transistor) switches and pixel electrodes are formed in the pixel units; the array substrate also comprise data join lines and grating join lines; and the data join lines are mutually isolated, are formed on the same layer with the data lines, the grating scanning lines or the pixel electrodes, and are connected with all the data lines via data through holes in a first insulation layer; and the grating join lines are mutually isolated, are formed on the same layer with the data lines, the grating scanning lines or the pixel electrodes, and are connected with all the grating scanning lines via grating through holes in a second insulation layer. In the invention, by adopting the technical scheme that the grating scanning lines and the grating join lines, as well as the data lines and the data join lines are arranged at intervals on the same layer or different layers, the signal to noise ratio and the defect relevance ratio of detection signals are improved when defects of the grating scanning lines and the data lines are detected.
Description
Technical field
The present invention relates to the LCD TEST technology, relate in particular to a kind of array base palte and manufacture method thereof that possesses test circuit structure.
Background technology
Along with Thin Film Transistor-LCD (Thin Film Transistor Liquid CrystalDisplay, hereinafter to be referred as: TFT-LCD) constantly improving and the continuous reduction of cost of manufacturing technology, TFT-LCD is widely used.Liquid crystal panel is the main display unit among the TFT-LCD, box-like is become with array base palte by color membrane substrates usually.
The typical structure of array base palte is many data lines and the grid sweep trace that comprises horizontal vertical intersection, encloses to form the pixel cell that matrix form is arranged.In each pixel cell, be formed with the TFT switch, by TFT switch conduction data line and pixel electrode.For guaranteeing the normal demonstration of liquid crystal panel, in the manufacture process of carrying out array base palte, just need carry out short circuit and out of circuit test to data line and grid sweep trace, after forming array base palte, also to carry out the whether normally test of received signal of pixel electrode.
For realizing the above-mentioned test function of array base palte, need on array base palte, form test circuit structure.Existing manufacturing method of array base plate with test circuit comprises following flow process: at first, on underlay substrate 1, adopt composition technology to form the pattern that comprises grid sweep trace 3, gate electrode 14 and grid joint lines 6, as shown in Figure 1 (for clarity sake, accompanying drawing only illustrates the partial structurtes of array base palte top pixel cell herein), grid joint lines 6 all links to each other with an end of each grid sweep trace 3; Then, the bad detection (Gate OS test) of each grid sweep trace 3 being carried out short circuit and opening circuit; Deposition forms gate insulation layer on the underlay substrate 1 that forms grid sweep trace 3 and grid joint lines 6; Adopt composition technology to form the pattern of active layer 15, data line 2, source electrode 16, drain electrode 17 and data joint lines 5 then, (clear as shown in Figure 2 for making structure, rete transparence with insulating material in this paper accompanying drawing shows), this data joint lines 5 all links to each other with an end of each data line 2; Then, the bad detection (S/D OS test) of each data line 2 being carried out short circuit and opening circuit; On the underlay substrate 1 that forms active layer 15, data line 2, source electrode 16, drain electrode 17 and data joint lines 5, form passivation layer, and on passivation layer, form passivation layer via hole 22; Adopt composition technology to form pixel electrode 4, as shown in Figure 3A, pixel electrode 4 is connected with drain electrode 17 by passivation layer via hole 22, and Fig. 3 B is the structure for amplifying synoptic diagram in Fig. 3 A circle; At last, carry out the final bad detection (Array final test) of array base palte, grid joint lines 6 and data joint lines 5 are the patches that only play a role in final bad detection, need when the final integral wireline inspection, connect grid sweep trace 3 and data line 2 respectively, before array base palte carries out box, will be removed.Wherein, grid sweep trace 3, data line 2, pixel electrode 4, grid joint lines 6 and data joint lines 5 are conductive material and make.
The grid sweep trace 3 bad detections of being carried out in the said process and the mode of data line 2 bad detections are similar, are that example describes with the 3 bad detections of grid sweep trace below.As shown in Figure 4, after forming grid sweep trace 3 and grid joint lines 6, utilize a testing apparatus shifting axle 18 to test, shifting axle 18 is provided with first signal receiver 19, secondary signal receiver 20 and signal projector 21, the position relation is the end overlap joint that makes a signal projector 21 and a grid sweep trace 3, the other end overlap joint of first signal receiver 19 and this grid sweep trace 3, the end overlap joint of another grid sweep trace 3 that secondary signal receiver 20 and this grid sweep trace 3 are adjacent.Two signal receivers are positioned at the same end of shifting axle 18.In test process, by signal projector 21 output signals, when the signal of first signal receiver, 19 receptions is lower than setting value, prove that then this grid sweep trace 3 opens circuit, when the signal of secondary signal receiver 20 receptions is higher than setting value, then prove these adjacent two grid sweep trace 3 short circuits.Along with shifting axle 18 along the moving of array base palte surface, promptly can finish test to all grid sweep traces 3.
But, in carrying out research process of the present invention, the inventor finds above-mentioned test process, and there are the following problems: when being short-circuited between two grid sweep traces 3, as shown in Figure 4, because an end of each grid sweep trace 3 is connected by grid joint lines 6, so the test signal of signal projector 21 emissions not only can arrive secondary signal receiver 20 by location of short circuit, also can arrive by grid joint lines 6, therefore the reception to secondary signal receiver 20 causes interference, cause the signal to noise ratio (S/N ratio) of test signal to reduce, influenced the recall rate and the testing of equipment speed of poor short circuit.There is identical problem in the bad test of data line 2.
Summary of the invention
The purpose of this invention is to provide a kind of array base palte and manufacture method thereof, to improve the effect of bad test in the array base palte manufacture process.
For achieving the above object, the invention provides a kind of array base palte, comprise underlay substrate; Be formed with many data lines and the grid sweep trace of horizontal vertical intersection on the described underlay substrate, enclose and form the pixel cell that matrix form is arranged; Be formed with TFT switch and pixel electrode in the described pixel cell, wherein, also comprise:
The data joint lines forms with layer with described data line, grid sweep trace or pixel electrode, and each other at interval, described data joint lines links to each other by the data via hole in first insulation course with each described data line; And/or
The grid joint lines forms with layer with described data line, grid sweep trace or pixel electrode, and each other at interval, described grid joint lines links to each other by the grid via hole in second insulation course with each described grid sweep trace.
For achieving the above object, the present invention also provides a kind of manufacture method of array base palte, is included in the step that forms grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode on the underlay substrate, wherein:
When forming described grid sweep trace, described data line or described pixel electrode, also form the data joint lines, and each other at interval, described data joint lines links to each other by the data via hole in first insulation course with each described data line; And/or
When forming described grid sweep trace, described data line or described pixel electrode, also form the grid joint lines, and each other at interval, described grid joint lines links to each other by the grid via hole in second insulation course with each described grid sweep trace.
As shown from the above technical solution, the present invention adopts grid sweep trace and the same layer of grid joint lines, data line and data joint lines or different interlayer every the technical scheme that is provided with, make when carrying out the bad detection of grid sweep trace or data line, can not be subjected to the influence of joint lines, thereby can improve the detection signal signal to noise ratio (S/N ratio), improve bad recall rate.In addition, joint lines links to each other with data line with the grid sweep trace by the conductive material of via hole with another layer, thereby does not influence final wireline inspection.
Description of drawings
Fig. 1 is for forming the fragmentary top TV structure synoptic diagram behind grid sweep trace and the grid joint lines pattern on the existing array base palte;
Fig. 2 is for forming the fragmentary top TV structure synoptic diagram behind data line and the data joint lines pattern on the existing array base palte;
Fig. 3 A is for having the fragmentary top TV structure synoptic diagram after the formation pixel electrode pattern on the array base palte now;
Fig. 3 B is the structure for amplifying synoptic diagram in Fig. 3 A circle;
The fragmentary top TV structure synoptic diagram of Fig. 4 for carrying out the bad detection of grid sweep trace on the existing array base palte;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 5 provides for the embodiment of the invention one;
The fragmentary top TV structure synoptic diagram of grid sweep trace and data joint lines place layer pattern in the array base palte that Fig. 6 provides for the embodiment of the invention one;
The fragmentary top TV structure synoptic diagram of data line and grid joint lines place layer pattern in the array base palte that Fig. 7 provides for the embodiment of the invention one;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 8 provides for the embodiment of the invention two;
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 9 provides for the embodiment of the invention three;
The fragmentary top TV structure synoptic diagram of grid sweep trace and grid joint lines place layer pattern in the array base palte that Figure 10 provides for the embodiment of the invention three;
The fragmentary top TV structure synoptic diagram of data line and data joint lines place layer pattern in the array base palte that Figure 11 provides for the embodiment of the invention three;
The fragmentary top TV structure synoptic diagram of the array base palte that Figure 12 provides for the embodiment of the invention four;
The process flow diagram of the manufacture method of the array base palte that Figure 13 provides for the embodiment of the invention five;
The process flow diagram of the manufacture method of the array base palte that Figure 14 provides for the embodiment of the invention six;
The fragmentary top TV structure synoptic diagram of the array base palte of the manufacture method manufacturing of the array base palte that Figure 15 provides for the embodiment of the invention six;
The process flow diagram of the manufacture method of the array base palte that Figure 16 provides for the embodiment of the invention seven;
The fragmentary top TV structure synoptic diagram of the array base palte of the manufacture method manufacturing of the array base palte that Figure 17 provides for the embodiment of the invention seven;
The process flow diagram of the manufacture method of the array base palte that Figure 18 provides for the embodiment of the invention eight;
The process flow diagram of the manufacture method of the array base palte that Figure 19 provides for the embodiment of the invention nine.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Embodiment one
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 5 provides for the embodiment of the invention one.The array base palte of present embodiment comprises underlay substrate 1, and underlay substrate 1 mostly is glass substrate.Be formed with many data lines 2 and the grid sweep trace 3 of horizontal vertical intersection on the underlay substrate 1, enclose and form the pixel cell that matrix form is arranged.Be formed with TFT switch and pixel electrode 4 in each pixel cell.In TFT-LCD, the TFT switch in each pixel cell specifically comprises gate electrode 14, active layer 15, source electrode 16 and drain electrode 17.Gate electrode 14 connects grid sweep trace 3, and source electrode 16 connects data line 2, and drain electrode 17 connects pixel electrode 4, and source electrode 16 and drain electrode 17 are by active layer 15 folded being located on the gate electrode 14.Realize the conducting or the disconnection of source electrode 16 and drain electrode 17 by the high-low level of grid sweep trace 3 inputs, so that be communicated with or turn-off data line 2 and pixel electrode 4.Between grid sweep trace 3 place layers and data line 2 place layers, be formed with gate insulator and keep insulation, between data line 2 place layers and pixel electrode 4 place layers, be formed with passivation layer (PVX) and keep insulation.
On the array base palte of present embodiment, also comprise test circuit structure, i.e. data joint lines 5 and grid joint lines 6.Be illustrated in figure 6 as the pattern of data joint lines 5 and grid sweep trace 3 place layers on the array base palte, data joint lines 5 forms with layer with grid sweep trace 3, and each other at interval.As shown in Figure 5, data joint lines 5 links to each other by the data via hole 7 in first insulation course with each data line 2.Be illustrated in figure 7 as the pattern of grid joint lines 6 and data line 2 place layers on the array base palte, grid joint lines 6 forms with layer with data line 2, and each other at interval.As shown in Figure 5, grid joint lines 6 links to each other by the grid via hole 8 in second insulation course with each grid sweep trace 3.
Wherein, different according to manufacture craft and array base-plate structure, data joint lines 5 has different implementations with each data line 2 by the concrete structure that data via hole in first insulation course 7 connects.
As shown in Figure 5, when data joint lines 5 forms with layer with grid sweep trace 3, first insulation course specifically can comprise gate insulator and passivation layer, and data joint lines 5 links to each other by the pixel electrode material in the data via hole 7 that is filled in gate insulator and passivation layer with data line 2.Can when form pixel electrode 4 patterns, keep the pixel electrode material in data via hole 7 positions and realize connecting.
Those skilled in the art should it will also be appreciated that multiple connected mode, such as: data line can be formed on the top of data line joint lines, there is the subregion overlapping, then the data via hole runs through passivation layer, data line and gate insulator successively, and the pixel electrode material can pass the data via hole and connect the data joint lines.
Reliably be connected with guaranteeing for simplifying technological process, connected mode shown in Figure 5 is a kind of optimal way, be that data via hole 7 comprises first data via hole 71 that runs through gate insulator and passivation layer and the second data via hole 72 that runs through passivation layer, two data via holes 7 that link to each other in every data line 2 and data joint lines 5 are sentenced the pixel electrode material and are formed a data via hole connecting line 23 and be connected.Data via hole connecting line 23 connects data joint lines 5 by the first data via hole 71, and connects data line 2 by the second data via hole 72.
Perhaps, also can be to form a data via hole, occupy the position of the above-mentioned first data via hole and the second data via hole, thereby connect data line and data joint lines.
Similarly, when grid joint lines 6 formed with layer with data line 2, second insulation course specifically can comprise gate insulator and passivation layer, and grid joint lines 6 links to each other by the pixel electrode material in the grid via hole 8 that is filled in gate insulator and passivation layer with grid sweep trace 3.Can when form pixel electrode 4 patterns, keep the pixel electrode material in grid via hole 8 positions and realize connecting.
Reliably be connected with guaranteeing for simplifying technological process, connected mode shown in Figure 5 is a kind of optimal way, be that grid via hole 8 comprises the first grid via hole 81 that runs through passivation layer and runs through gate insulator and the second grid via hole 82 of passivation layer, two grid via holes 8 that link to each other in every grid sweep trace 3 and grid joint lines 6 are sentenced the pixel electrode material and are formed a grid via hole connecting line 24 and be connected.Grid via hole connecting line 24 connects grid joint lines 6 by first grid via hole 81, and connects grid sweep trace 3 by the second grid via hole 82.
Perhaps, it is overlapping that grid joint lines 6 and grid sweep trace 3 also can the subregions, links to each other with a grid via hole 8.Again or, also can be to form a grid via hole, occupy the position of the above-mentioned first grid via hole and the second grid via hole, thereby connect grid sweep trace and grid joint lines.
Perhaps, can also adopt other via hole connected modes, when being same layer of formation of data joint lines and grid sweep trace, first insulation course can only comprise gate insulator, and the data joint lines links to each other by the data line material in the data via hole that is filled in gate insulator with data line.Can when form the data line pattern, make data line extend to data and cross the hole site data joint lines connection corresponding with the below.Similarly, when grid joint lines and data line formed with layer, second insulation course can only comprise gate insulator, and the grid joint lines links to each other by the data line material in the grid via hole that is filled in gate insulator with the grid sweep trace.Can when form grid joint lines pattern, make the grid joint lines extend to grid and cross the hole site grid sweep trace connection corresponding with the below.Though the thickness of insulating layer that these two kinds of schemes make via hole run through reduces, thus the reliability that helps connecting, these two kinds of schemes can increase the mask number of times, and in concrete the production, those skilled in the art can select concrete production method with reference to technological requirement.
Adopt technique scheme, in the time of can guaranteeing that after forming the grid sweep trace grid sweep trace carried out the bad detection of short circuit, each grid sweep trace is not communicated with by the grid joint lines, and the Signal-to-Noise in the time of can effectively improving the poor short circuit test improves bad recall rate and testing of equipment speed.Similarly,, the Signal-to-Noise when testing be can improve, bad recall rate and testing of equipment speed improved because data line is not communicated with by the data joint lines when carrying out bad detections of short circuit after formation.And, adopt technique scheme, after the bad detection of data line and grid sweep trace is finished, the grid sweep trace is linked to each other with the grid joint lines by via hole, data line is connected with the data joint lines, do not influence final bad detection to whole circuit.
Embodiment two
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 8 provides for the embodiment of the invention two.The difference of array base palte in the present embodiment and embodiment one is: data joint lines 5 forms with layer with pixel electrode 4, and each other at interval, data joint lines 5 links to each other by the data via hole 7 in first insulation course with each data line 2; Grid joint lines 6 forms with layer with pixel electrode 4, and each other at interval, grid joint lines 6 links to each other by the grid via hole 8 in second insulation course with each grid sweep trace 3.
Concrete, when data joint lines 5 forms with layer with pixel electrode 4, first insulation course only comprises passivation layer, data via hole 7 promptly comprises the second data via hole that runs through passivation layer, the data via hole connecting line 23 that forms with the pixel electrode material directly connects data joint lines 5, and connects data line 2 by the second data via hole.When grid joint lines 6 forms with layer with pixel electrode 4, second insulation course comprises gate insulator and passivation layer, grid via hole 8 comprises the second grid via hole that runs through gate insulator and passivation layer, the grid via hole connecting line 24 that forms with the pixel electrode material directly connects grid joint lines 6, and connects grid sweep trace 3 by the second grid via hole.
Adopt technique scheme, can be when the poor short circuit of carrying out grid sweep trace and data line detects, be not subjected to the interference of joint lines, effectively improve the Signal-to-Noise of the poor short circuit test after grid sweep trace and data line form, improve bad recall rate and testing of equipment speed, and do not influence final bad detection whole circuit.
Embodiment three
The fragmentary top TV structure synoptic diagram of the array base palte that Fig. 9 provides for the embodiment of the invention three, the difference of present embodiment and embodiment one is: data joint lines 5 forms with layer with data line 2, and at interval, be the pattern of data line 2 and data joint lines 5 place layers as shown in figure 11 each other.As shown in Figure 9, data joint lines 5 links to each other by the data via hole 7 in first insulation course with each data line 2.Be the pattern of grid sweep trace 3 and grid joint lines 6 place layers as shown in figure 10, grid joint lines 6 forms with layer with grid sweep trace 3, and each other at interval.As shown in Figure 9, grid joint lines 6 links to each other by the grid via hole 8 in second insulation course with each grid sweep trace 3.
Concrete, when data joint lines 5 forms with layer with data line 2, first insulation course comprises passivation layer, data via hole 7 comprises the first data via hole 71 and the second data via hole 72 that runs through passivation layer respectively, the data via hole connecting line 23 that forms with the pixel electrode material connects data joint lines 5 by the first data via hole 71, and connects data line 2 by the second data via hole 72.
When grid joint lines 6 forms with layer with grid sweep trace 3, second insulation course comprises gate insulator and passivation layer, grid via hole 8 comprises the first grid via hole 81 and the second grid via hole 82 that runs through gate insulator and passivation layer respectively, and the grid via hole connecting line 24 that forms with the pixel electrode material connects grid joint lines 6 by first grid via hole 81.And connect grid sweep trace 3 by the second grid via hole 82.Perhaps, when grid joint lines 6 forms with layer with grid sweep trace 3, second insulation course can only comprise gate insulator, grid joint lines 6 links to each other by the data line material formation grid via hole connecting line 24 that is filled in the gate insulator grid via hole 8 with grid sweep trace 3, and producers can free as required selection scheme.
Adopt technique scheme, can effectively improve the Signal-to-Noise of the poor short circuit test after grid sweep trace and data line form, improve bad recall rate and testing of equipment speed, and do not influence final bad detection whole circuit.
In concrete the application, the data joint lines can form with layer with data line, grid sweep trace or pixel electrode, and the grid joint lines can form with layer with data line, grid sweep trace or pixel electrode.The formation position of data joint lines and grid sweep trace is not limited to the array mode of the foregoing description one, embodiment two and embodiment three, as long as when guaranteeing that after forming the grid sweep trace grid sweep trace carried out the bad detection of short circuit, each grid sweep trace is not communicated with by the grid joint lines, when guaranteeing that after forming data data line carried out the bad detection of short circuit, each data line is not communicated with by the data joint lines and gets final product.For example can also for, data joint lines and grid sweep trace form with layer, grid joint lines and pixel electrode are with layer formation; Perhaps data joint lines and pixel electrode form with layer, and grid joint lines and data line are with layer formation etc.As long as the data joint lines can be provided with at interval with data line, realize that with the conductive material in another layer connection gets final product by the data via hole on first insulation course, similarly, as long as the grid joint lines can be provided with the grid scan line spacings, realize that with the conductive material in another layer connection gets final product by the grid via hole on second insulation course.
Embodiment four
The fragmentary top TV structure synoptic diagram of the array base palte that Figure 12 provides for the embodiment of the invention four.In the various embodiments described above, be and adopt the technical scheme of grid sweep trace 3 (Gate line) as memory capacitance, it is the pattern of pixel electrode 4 and grid sweep trace 3 partly overlapping " CST on Gate ", in the present embodiment, the concrete scheme that memory capacitance independently is set, the i.e. pattern of " CST on Common " of adopting.In the case, also comprise storage capacitance line 11 in the array base palte, storage capacitance line 11 general and grid sweep trace 3 layer formation together, and each other at interval; Generally be parallel, in each pixel cell of colleague with grid sweep trace 3.Also comprise electric capacity joint lines 12 in the array base palte, form with layer with grid sweep trace 3, data line 2 or pixel electrode 4, and each other at interval, electric capacity joint lines 12 links to each other by the electric capacity via hole 13 in second insulation course with each storage capacitance line 11.Be specially electric capacity joint lines 12 shown in Figure 12 and form with layer, and electric capacity joint lines 12 forms the situation that electric capacity via hole connecting line 25 links to each other with storage capacitance line 11 by the pixel electrode material that is filled in the electric capacity via hole 13 with data line 2.
The specific implementation that electric capacity joint lines 12 and each storage capacitance line 11 link to each other by electric capacity via hole in second insulation course 13 can be connected the scheme of grid sweep trace 3 with reference to grid joint lines 6 by the grid via hole 8 in second insulation course.
After forming, storage capacitance line also needs the bad detection carrying out short circuit and open circuit, adopt technique scheme, then can effectively improve the Signal-to-Noise that storage capacitance line forms back poor short circuit test, improve bad recall rate and testing of equipment speed, and do not influence final bad detection whole circuit.
In concrete the application, if existing other circuits that independently form need carry out poor short circuit on the array base palte detects, and need in final whole wireline inspection, link to each other with joint lines, then can adopt technical scheme of the present invention, survey line to be checked and survey line joint lines to be checked are provided with at interval, can be with interlayer every, also can be different interlayer every, then the conductive material with another layer is connected by the via hole on the insulation course.Adopt this technical scheme, each survey line to be checked carries out poor short circuit when detecting, with survey line joint lines to be checked be independently, not disturbed by it, can improve Signal-to-Noise, improve bad recall rate, and not influence and finally utilize survey line joint lines to be checked to carry out whole wireline inspection.Obtain under the situation of identical recall rate requiring,, can improve the test speed of equipment for array base-plate structure of the present invention.The testing of equipment sweep velocity is about 200 mm/second (mm/s) at present, adopts array base-plate structure of the present invention, speed can be increased to 250～300mm/s.
The present invention also provides a kind of manufacture method of array base palte, is included in the step that forms grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode on the underlay substrate, wherein:
When forming grid sweep trace, data line or pixel electrode, also form the data joint lines, and each other at interval, the data joint lines links to each other by the data via hole in first insulation course with each data line; And/or
When forming grid sweep trace, data line or pixel electrode, also form the grid joint lines, and each other at interval, the grid joint lines links to each other by the grid via hole in second insulation course with each grid sweep trace.
The manufacture method of array base palte of the present invention can adopt original manufacturing process of array base palte and material, forms data joint lines and grid joint lines, and little to the change of existing technology, cost is low, is easy to promote realize.And the manufacture method of array base palte of the present invention can be used to prepare array base palte of the present invention, possesses the good detection performance, has guaranteed yield rate.
Based on existing Different Preparation, for example three masking process, four masking process and five masking process etc., the manufacture method of array base palte of the present invention can have different ways of realization, will technical scheme of the present invention be described by the part preferred embodiment below.
Embodiment five
The process flow diagram of the manufacture method of the array base palte that Figure 13 provides for the embodiment of the invention five, the method for present embodiment comprises the steps:
The operation that composition technology described in present embodiment and the subsequent embodiment is specifically as follows mask exposure, development, etching, peels off, specifically, composition technology to data line film and active layer film can be half exposure of adopting intermediate tone mask plate or gray tone mask plate to carry out, i.e. mask exposure, the operation of multiple etching, the data line below of formation remains with the active layer film.
The technical scheme of present embodiment can be used to make array base palte of the present invention, in the manufacture process of array base palte, grid sweep trace and data line opened circuit and the bad detection of short circuit, because when grid sweep trace and data line detect, can be connected with the data joint lines by the grid joint lines, so can not influence the detection effect, the signal to noise ratio (S/N ratio) of detection can be provided, improve bad recall rate.
On the basis of present embodiment, can also adopt the structure that memory capacitance independently is set, that is:
When formation comprises the pattern of grid sweep trace 3, gate electrode 14 and data joint lines 5, also form the pattern of storage capacitance line 11 simultaneously;
When formation comprises the pattern of active layer 15, source electrode 16, drain electrode 17, data line 2 and grid joint lines 6, also form the pattern of electric capacity joint lines 12 simultaneously, the pattern each interval of electric capacity joint lines 12 and place layer is then carried out the bad detection of storage capacitance line 11;
When forming passivation layer via hole 22, grid via hole 8 and data via hole 7, also form electric capacity via hole 13 simultaneously, the position difference corresponding stored electric capacity line 11 of electric capacity via hole 13 and the position of electric capacity joint lines 12;
When formation comprises the pattern of pixel electrode 4, grid via hole connecting line 24 and data via hole connecting line 23, also form the pattern of electric capacity via hole connecting line 25 simultaneously, electric capacity via hole connecting line 25 connects storage capacitance line 11 and electric capacity joint lines 12 by electric capacity via hole 13.
Said structure can be referring to shown in Figure 12.Also may exist other need carry out the circuit of bad detection on the array base palte, and when final wireline inspection, need link to each other with joint lines, adopt the technical scheme of present embodiment that circuit and its joint lines are provided with at interval, neither influence the independent detection bad to circuit, when not influencing final wireline inspection again to the application of joint lines.
Embodiment six
The process flow diagram of the manufacture method of the array base palte that Figure 14 provides for the embodiment of the invention six, the method for present embodiment comprises the steps:
The method of present embodiment can be used to make array base palte of the present invention, and formed structure can be referring to shown in Figure 15.
The technical scheme of present embodiment can be used to make array base palte of the present invention, in the manufacture process of array base palte, grid sweep trace and data line opened circuit and the bad detection of short circuit, because when grid sweep trace and data line detect, can be connected with the data joint lines by the grid joint lines, so can not influence the detection effect, the signal to noise ratio (S/N ratio) of detection can be provided, improve bad recall rate.
Embodiment seven
The process flow diagram of the manufacture method of the array base palte that Figure 16 provides for the embodiment of the invention seven, the method for present embodiment comprises the steps:
The method of present embodiment can be used to make array base palte of the present invention, and formed structure can be referring to shown in Figure 17.
The technical scheme of present embodiment can be used to make array base palte of the present invention, in the manufacture process of array base palte, grid sweep trace and data line opened circuit and the bad detection of short circuit, because when grid sweep trace and data line detect, can be connected with the data joint lines by the grid joint lines, so can not influence the detection effect, the signal to noise ratio (S/N ratio) of detection can be provided, improve bad recall rate.
Embodiment eight
The process flow diagram of the manufacture method of the array base palte that Figure 18 provides for the embodiment of the invention eight, the method for present embodiment comprises the steps:
Step 1801, on underlay substrate 1 deposition grid sweep trace film;
Step 1802, grid sweep trace film is carried out composition technology, form the pattern that comprises grid sweep trace 3 and gate electrode 14;
Step 1803, grid sweep trace 3 is carried out bad detection, the bad detection that specifically can adopt equipment shown in Figure 4 to carry out short circuit and open circuit, bad detection is the detection step of carrying out in the array base palte manufacturing process, can be all to detect, and also can be to spot-check detection;
Step 1804, forming deposition gate insulator layer film on the underlay substrate 1 of above-mentioned pattern;
Step 1805, on the gate insulator layer film deposition active layer film and data line film;
Step 1806, data line film and active layer film are carried out composition technology, form the pattern that comprises active layer 15, source electrode 16, drain electrode 17 and data line 2;
Step 1807, data line 2 is carried out bad detection, the bad detection that specifically can adopt equipment shown in Figure 4 to carry out short circuit and open circuit, bad detection is the detection step of carrying out in the array base palte manufacturing process, can be all to detect, and also can be to spot-check detection;
Step 1808, forming deposit passivation layer film on the underlay substrate 1 of above-mentioned pattern;
Step 1809, passivation layer film and gate insulator layer film are carried out composition technology, form passivation layer via hole 22, grid via hole 8 and data via hole 7, the position of grid via hole 8 is corresponding grid sweep trace 3 respectively, and data via hole 7 is the position of respective data lines 2 respectively;
Step 1810, forming pixel deposition electrode film on the underlay substrate 1 of above-mentioned pattern;
Step 1811, the pixel electrode film is carried out composition technology, formation comprises the pattern of pixel electrode 4, grid joint lines 6, data joint lines 5, grid via hole connecting line 24 and data via hole connecting line 23, pixel electrode 4, grid joint lines 6 and data joint lines 5 each intervals, grid via hole connecting line 24 connects grid joint lines 6 and grid sweep trace 3 by grid via hole 8, data via hole connecting line 23 connects data joint lines 5 and data line 2 by data via hole 7, can be referring to structure shown in Figure 8.
The technical scheme of present embodiment can be used to make array base palte of the present invention, in the manufacture process of array base palte, grid sweep trace and data line opened circuit and the bad detection of short circuit, because when grid sweep trace and data line detect, can be connected with the data joint lines by the grid joint lines, so can not influence the detection effect, the signal to noise ratio (S/N ratio) of detection can be provided, improve bad recall rate.
Embodiment nine
The process flow diagram of the manufacture method of the array base palte that Figure 19 provides for the embodiment of the invention nine, the method for present embodiment comprises the steps:
The technical scheme of present embodiment can be used to make array base palte of the present invention, in the manufacture process of array base palte, grid sweep trace and data line opened circuit and the bad detection of short circuit, because when grid sweep trace and data line detect, can be connected with the data joint lines by the grid joint lines, so can not influence the detection effect, the signal to noise ratio (S/N ratio) of detection can be provided, improve bad recall rate.
Manufacture method of the present invention is not limited to embodiment five to nine described schemes, the structure of the elaboration of concrete manufacture method in can reference example one to four, the independent assortment scheme, as long as guarantee in the manufacture process of array base palte the grid sweep trace and data line opens circuit and during the bad detection of short circuit, can be connected with the data joint lines, can not influence the detection effect and get final product by the grid joint lines.
According to the difference of array base palte mask etching technological process, grid joint lines, data joint lines equijoin line can have the different positions that is provided with on the array base palte.When adopting twice masking process the active layer film of etching and data line film form data line and active layer respectively, can make data line below not have active layer material, then the data line material can be packed into the effect of playing the via hole connecting line in the via hole of its lower floor.
The technical scheme of each embodiment of manufacture method of array base palte of the present invention has made full use of the original manufacturing process and the material of array base palte, only need to change mask plate and can change the pattern that etches, thereby easy to the change of prior art, it is low to improve cost, is easy to promote carry out.
Array base palte of the present invention and manufacture method the foregoing description thereof are that example describes with the linear formula of bottom gate that the grid sweep trace is formed on data line lower floor all, it will be appreciated by those skilled in the art that, in concrete the application, the grid sweep trace is formed on the top grid line form on data line upper strata or form that other rete changes in proper order and can pushes away by technical scheme of the present invention too.In addition according to actual conditions,, grid joint lines or data joint lines can be set as required if when only wanting to detect grid sweep trace or data line in the production line.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (15)
1. an array base palte comprises underlay substrate; Be formed with many data lines and the grid sweep trace of horizontal vertical intersection on the described underlay substrate, enclose and form the pixel cell that matrix form is arranged; Be formed with TFT switch and pixel electrode in the described pixel cell, it is characterized in that, also comprise:
The data joint lines forms with layer with described data line, grid sweep trace or pixel electrode, and each other at interval, described data joint lines links to each other by the data via hole in first insulation course with each described data line; And/or
The grid joint lines forms with layer with described data line, grid sweep trace or pixel electrode, and each other at interval, described grid joint lines links to each other by the grid via hole in second insulation course with each described grid sweep trace.
2. array base palte according to claim 1 is characterized in that, also comprises:
Storage capacitance line forms with layer with described grid sweep trace, and each other at interval;
The electric capacity joint lines forms with layer with described grid sweep trace, data line or pixel electrode, and each other at interval, described electric capacity joint lines links to each other by the electric capacity via hole in second insulation course with each described storage capacitance line.
3. array base palte according to claim 1 and 2 is characterized in that:
When described data joint lines and described grid sweep trace form with layer, described first insulation course comprises gate insulator and passivation layer, and described data joint lines and described data line link to each other with pixel electrode material in the passivation layer data via hole by being filled in gate insulator.
4. array base palte according to claim 1 and 2 is characterized in that:
When described data joint lines and described pixel electrode formed with layer, described first insulation course comprised passivation layer, and described data joint lines links to each other by the pixel electrode material that is filled in the passivation layer data via hole with described data line.
5. array base palte according to claim 1 and 2 is characterized in that:
When described data joint lines and described data line formed with layer, described first insulation course comprised passivation layer, and described data joint lines links to each other by the pixel electrode material that is filled in the passivation layer data via hole with described data line.
6. array base palte according to claim 1 and 2 is characterized in that:
When described grid joint lines and described data line formed with layer, described second insulation course comprised gate insulator and passivation layer, and described grid joint lines and described grid sweep trace link to each other with pixel electrode material in the passivation layer grid via hole by being filled in gate insulator.
7. array base palte according to claim 1 and 2 is characterized in that:
When described grid joint lines and described pixel electrode formed with layer, described second insulation course comprised gate insulator and passivation layer, and described grid joint lines and described grid sweep trace link to each other with pixel electrode material in the passivation layer grid via hole by being filled in gate insulator.
8. array base palte according to claim 1 and 2 is characterized in that:
When described grid joint lines and described grid sweep trace formed with layer, described second insulation course comprised gate insulator and passivation layer, and described grid joint lines and described grid sweep trace link to each other with pixel electrode material in the passivation layer grid via hole by being filled in gate insulator.
9. the manufacture method of an array base palte is included in the step that forms grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode on the underlay substrate, it is characterized in that:
When forming described grid sweep trace, described data line or described pixel electrode, also form the data joint lines, and each other at interval, described data joint lines links to each other by the data via hole in first insulation course with each described data line; And/or
When forming described grid sweep trace, described data line or described pixel electrode, also form the grid joint lines, and each other at interval, described grid joint lines links to each other by the grid via hole in second insulation course with each described grid sweep trace.
10. the manufacture method of array base palte according to claim 9, it is characterized in that, on underlay substrate, form grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode, and when forming described grid sweep trace, also form the data joint lines, when forming described data line, also form the grid joint lines and comprise:
Deposition grid sweep trace film forms the pattern that comprises grid sweep trace, gate electrode and data joint lines, described data joint lines and described grid sweep trace each interval by composition technology on underlay substrate;
Deposition gate insulator layer film, active layer film and data line film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises active layer, source electrode, drain electrode, data line and grid joint lines, described grid joint lines and described data line each interval by composition technology;
Deposit passivation layer film on the underlay substrate that forms above-mentioned pattern;
Described passivation layer film and described gate insulator layer film are carried out composition technology, form passivation layer via hole, grid via hole and data via hole, the position corresponding grid joint lines of difference of described grid via hole and the position of grid sweep trace, the position difference corresponding data joint lines of described data via hole and the position of data line;
Pixel deposition electrode film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises pixel electrode, grid via hole connecting line and data via hole connecting line by composition technology, each described grid via hole connecting line connects described grid joint lines and grid sweep trace by the grid via hole respectively, and each described data via hole connecting line connects described data joint lines and data line by the data via hole respectively.
11. the manufacture method of array base palte according to claim 10 is characterized in that:
When formation comprises the pattern of grid sweep trace, gate electrode and data joint lines, also form the pattern of storage capacitance line simultaneously;
When formation comprises the pattern of active layer, source electrode, drain electrode, data line and grid joint lines, also form the pattern of electric capacity joint lines simultaneously, the pattern each interval of electric capacity joint lines and place layer;
When forming passivation layer via hole, grid via hole and data via hole, also form the electric capacity via hole simultaneously, the position difference corresponding stored electric capacity line of described electric capacity via hole and the position of electric capacity joint lines;
When formation comprises the pattern of pixel electrode, grid via hole connecting line and data via hole connecting line, also form the pattern of electric capacity via hole connecting line simultaneously, electric capacity via hole connecting line connects storage capacitance line and electric capacity joint lines by the electric capacity via hole.
12. the manufacture method of array base palte according to claim 9, it is characterized in that, on underlay substrate, form grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode, and when forming described pixel electrode, also form the data joint lines, when forming described data line, also form the grid joint lines and comprise:
Deposition grid sweep trace film forms the pattern that comprises grid sweep trace and gate electrode by composition technology on underlay substrate;
Deposition gate insulator layer film on the underlay substrate that forms above-mentioned pattern.Active layer film and data line film form the pattern that comprises active layer, source electrode, drain electrode, data line and grid joint lines, described grid joint lines and described data line each interval by composition technology;
Deposit passivation layer film on the underlay substrate that forms above-mentioned pattern;
Described passivation layer film and described gate insulator layer film are carried out composition technology, form passivation layer via hole, grid via hole and data via hole, the position corresponding grid joint lines of difference of described grid via hole and the position of grid sweep trace, the position of described data via hole respective data lines;
Pixel deposition electrode film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises pixel electrode, data joint lines, grid via hole connecting line and data via hole connecting line by composition technology, described data joint lines and described pixel electrode each interval, data via hole connecting line connects described data joint lines and data line by the data via hole, and each described grid via hole connecting line connects described grid joint lines and grid sweep trace by the grid via hole respectively.
13. the manufacture method of array base palte according to claim 9, it is characterized in that, on underlay substrate, form grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode, and when forming described grid sweep trace, also form the data joint lines, when forming described pixel electrode, also form the grid joint lines and comprise:
Deposition grid sweep trace film forms the pattern that comprises grid sweep trace, gate electrode and data joint lines, described data joint lines and described grid sweep trace each interval by composition technology on underlay substrate;
Deposition gate insulator layer film, active layer film and data line film form the pattern that comprises active layer, source electrode, drain electrode and data line by composition technology on the underlay substrate that forms above-mentioned pattern;
Deposit passivation layer film on the underlay substrate that forms above-mentioned pattern;
Described passivation layer film and described gate insulator layer film are carried out composition technology, form passivation layer via hole, grid via hole and data via hole, the position of the corresponding grid sweep trace in the position of described grid via hole, the position difference corresponding data joint lines of described data via hole and the position of data line;
Pixel deposition electrode film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises pixel electrode, grid joint lines, grid via hole connecting line and data via hole connecting line by composition technology, described grid joint lines and described pixel electrode each interval, grid via hole connecting line connects described grid joint lines and grid sweep trace by the grid via hole, and each described data via hole connecting line connects described data joint lines and data line by the data via hole respectively.
14. the manufacture method of array base palte according to claim 9, it is characterized in that, on underlay substrate, form grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode, and when forming described pixel electrode, also form the data joint lines and the grid joint lines comprises:
Deposition grid sweep trace film forms the pattern that comprises grid sweep trace and gate electrode by composition technology on underlay substrate;
Deposition gate insulator layer film, active layer film and data line film form the pattern that comprises active layer, source electrode, drain electrode and data line by composition technology on the underlay substrate that forms above-mentioned pattern;
Deposit passivation layer film on the underlay substrate that forms above-mentioned pattern;
Described passivation layer film and described gate insulator layer film are carried out composition technology, form passivation layer via hole, grid via hole and data via hole, the position of described grid via hole is the position of corresponding grid sweep trace respectively, and the position of described data via hole is the position of respective data lines respectively;
Pixel deposition electrode film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises pixel electrode, grid joint lines, data joint lines, grid via hole connecting line and data via hole connecting line by composition technology, described pixel electrode, grid joint lines and data joint lines each interval, described grid via hole connecting line connects grid joint lines and grid sweep trace by the grid via hole, and described data via hole connecting line connects data joint lines and data line by the data via hole.
15. the manufacture method of array base palte according to claim 9, it is characterized in that, on underlay substrate, form grid sweep trace, gate electrode, active layer, source electrode, drain electrode, data line and pixel electrode, and when forming described grid sweep trace, also form the grid joint lines, when forming described data line, also form the data joint lines and comprise:
Deposition grid sweep trace film forms the pattern that comprises grid sweep trace, gate electrode and grid joint lines, described grid joint lines and described grid sweep trace each interval by composition technology on underlay substrate;
Deposition gate insulator layer film, active layer film and data line film on the underlay substrate that forms above-mentioned pattern, form the pattern that comprises active layer, source electrode, drain electrode, data line and data joint lines, described data joint lines and described data line each interval by composition technology;
Deposit passivation layer film on the underlay substrate that forms above-mentioned pattern;
Described passivation layer film and described gate insulator layer film are carried out composition technology, form passivation layer via hole, grid via hole and data via hole, the position corresponding grid joint lines of difference of described grid via hole and the position of grid sweep trace, the position difference corresponding data joint lines of described data via hole and the position of data line;
Pixel deposition electrode film on the underlay substrate that forms above-mentioned pattern, by composition technology, formation comprises the pattern of pixel electrode, grid via hole connecting line and data via hole connecting line, each described grid via hole connecting line connects described grid joint lines and grid sweep trace by the grid via hole respectively, and each described data via hole connecting line connects described data joint lines and data line by the data via hole respectively.
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| CN2009100914882A CN101995712A (en) | 2009-08-21 | 2009-08-21 | Array substrate and manufacturing method thereof |
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| CN107045994A (en) * | 2016-11-11 | 2017-08-15 | 上海天马微电子有限公司 | Detection method and detection device of array substrate, array substrate and manufacturing method of array substrate |
| CN109885196A (en) * | 2017-12-04 | 2019-06-14 | 乐金显示有限公司 | The method of display device and manufacture display device including touch sensor |
| CN113848658A (en) * | 2021-09-16 | 2021-12-28 | 信利(仁寿)高端显示科技有限公司 | Automatic production scheduling system and method for linkage of gate and source-drain equipment |
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| JP2003157053A (en) * | 2001-11-19 | 2003-05-30 | Matsushita Electric Ind Co Ltd | Liquid crystal display device, and inspection method and device therefor |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107045994A (en) * | 2016-11-11 | 2017-08-15 | 上海天马微电子有限公司 | Detection method and detection device of array substrate, array substrate and manufacturing method of array substrate |
| CN107045994B (en) * | 2016-11-11 | 2019-12-10 | 上海天马微电子有限公司 | detection method and detection device of array substrate, array substrate and manufacturing method of array substrate |
| CN109885196A (en) * | 2017-12-04 | 2019-06-14 | 乐金显示有限公司 | The method of display device and manufacture display device including touch sensor |
| CN113848658A (en) * | 2021-09-16 | 2021-12-28 | 信利(仁寿)高端显示科技有限公司 | Automatic production scheduling system and method for linkage of gate and source-drain equipment |
| CN113848658B (en) * | 2021-09-16 | 2023-11-14 | 信利(仁寿)高端显示科技有限公司 | Automatic grid and source drain equipment linkage scheduling system and method |
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